summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/bus/saitek_osa/maestro.cpp
blob: c0b388213c3737f6c1505055aa669523b7a73e9e (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
// license:BSD-3-Clause
// copyright-holders:hap
// thanks-to:Berger
/***************************************************************************

Saitek OSA Module: Kasparov Maestro/Analyst (1987-1990)
This is for the newer versions. For Maestro A, see maestroa.*

The hardware and chess engine is similar to the Stratos/Turbo King series.

Version B is compatible with the 1st EGR expansion ROM, version C/D uses
EGR II. Versions D+ and D++ are post-production improvements, they were not
sold officially.

Hardware notes:
- CPU: see notes below
- 64KB ROM (2*27C256)
- 16KB RAM (2*HY62C64P-70), one of them is optional
- 1 ROM socket for EGR expansion ROM

Analyst adds a HD44780A00H and a small 16-char LCD screen.

Both were sold at 4MHz, 6MHz, 8MHz speeds, Maestro also had a 10MHz version.
CPUs used were: R65C02P4, RP65C02F, W65C02P-8. In almost all cases with the
higher speed versions, they overclocked the CPU. And if the CPU couldn't
handle the overclock well enough, they went for a slightly lower speed XTAL.

TODO:
- does not work if cpu speed is 4MHz
- cpu clock divider after writing to 0x2000/0x2200

***************************************************************************/

#include "emu.h"
#include "maestro.h"

#include "bus/generic/carts.h"
#include "cpu/m6502/r65c02.h"

#include "softlist.h"


DEFINE_DEVICE_TYPE(OSA_MAESTRO, saitekosa_maestro_device, "osa_maestro", "Maestro B-D")
DEFINE_DEVICE_TYPE(OSA_ANALYST, saitekosa_analyst_device, "osa_analyst", "Analyst")


//-------------------------------------------------
//  initialization
//-------------------------------------------------

saitekosa_maestro_device::saitekosa_maestro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) :
	device_t(mconfig, type, tag, owner, clock),
	device_saitekosa_expansion_interface(mconfig, *this),
	m_maincpu(*this, "maincpu"),
	m_banked_ram(*this, "banked_ram", 0x2000, ENDIANNESS_LITTLE),
	m_rambank(*this, "rambank"),
	m_rombank(*this, "rombank"),
	m_extrom(*this, "extrom")
{ }

saitekosa_maestro_device::saitekosa_maestro_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
	saitekosa_maestro_device(mconfig, OSA_MAESTRO, tag, owner, clock)
{ }

saitekosa_analyst_device::saitekosa_analyst_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
	saitekosa_maestro_device(mconfig, OSA_ANALYST, tag, owner, clock),
	m_lcd(*this, "lcd")
{ }

void saitekosa_maestro_device::device_start()
{
	// init banks
	m_rombank->configure_entries(0, 2, memregion("maincpu")->base(), 0x8000);
	m_rambank->configure_entries(0, 2, m_banked_ram, 0x1000);

	// register for savestates
	save_item(NAME(m_latch_enable));
	save_item(NAME(m_latch));
	save_item(NAME(m_extrom_bank));
}

void saitekosa_maestro_device::device_reset()
{
	set_cpu_freq();
	control_w(0);
}

void saitekosa_maestro_device::set_cpu_freq()
{
	static const XTAL xtal[6] = { 4_MHz_XTAL, 5.67_MHz_XTAL, 6_MHz_XTAL, 7.2_MHz_XTAL, 8_MHz_XTAL, 10_MHz_XTAL };
	m_maincpu->set_unscaled_clock(xtal[ioport("FAKE")->read() % 6]);
}


//-------------------------------------------------
//  rom_region - device-specific ROM region
//-------------------------------------------------

ROM_START( maestro )
	ROM_REGION(0x10000, "maincpu", 0)

	ROM_DEFAULT_BIOS("d1")

	// B (Maestro only)
	ROM_SYSTEM_BIOS(0, "b1", "Maestro B (set 1)")
	ROMX_LOAD("m6c_807c_u2.u2", 0x0000, 0x8000, CRC(57c34b4d) SHA1(1f436687f90b1afd4646e90d5617cf05c4465c98), ROM_BIOS(0))
	ROMX_LOAD("b6c_721_u3.u3",  0x8000, 0x8000, CRC(b1e57023) SHA1(6cec5cdc0bf4f8ac88afb0397fcb4738136b0431), ROM_BIOS(0))

	ROM_SYSTEM_BIOS(1, "b2", "Maestro B (set 2)")
	ROMX_LOAD("m6c_807e_u2.u2", 0x0000, 0x8000, CRC(a6b11715) SHA1(18e086353d9122034f78bcd75ef5b3462c5983ac), ROM_BIOS(1))
	ROMX_LOAD("b6c_721_u3.u3",  0x8000, 0x8000, CRC(b1e57023) SHA1(6cec5cdc0bf4f8ac88afb0397fcb4738136b0431), ROM_BIOS(1))

	// C (C and above are shared Maestro/Analyst)
	ROM_SYSTEM_BIOS(2, "c", "Maestro C")
	ROMX_LOAD("m6l_b30d_u2.u2", 0x0000, 0x8000, CRC(bb10e15c) SHA1(7b0fb987c49da76a03b46c80d2b4eacaa785ee75), ROM_BIOS(2))
	ROMX_LOAD("b6c_721_u3.u3",  0x8000, 0x8000, CRC(b1e57023) SHA1(6cec5cdc0bf4f8ac88afb0397fcb4738136b0431), ROM_BIOS(2))

	// D
	ROM_SYSTEM_BIOS(3, "d1", "Maestro D (set 1)")
	ROMX_LOAD("ma3_714a_u2.u2", 0x0000, 0x8000, CRC(435e1e30) SHA1(0d82df7c40443cb341dacebdf65f33c3e03bce70), ROM_BIOS(3))
	ROMX_LOAD("b6m_b15_u3.u3",  0x8000, 0x8000, CRC(6155de90) SHA1(bb5cdf061dde2d1dc7925d455891c3ade1d274e3), ROM_BIOS(3))

	ROM_SYSTEM_BIOS(4, "d2", "Maestro D (set 2)")
	ROMX_LOAD("ma3_714a_u2.u2", 0x0000, 0x8000, CRC(435e1e30) SHA1(0d82df7c40443cb341dacebdf65f33c3e03bce70), ROM_BIOS(4))
	ROMX_LOAD("b6m_629_u3.u3",  0x8000, 0x8000, CRC(15e7b1f1) SHA1(d2a757114f13c6141d74a15671aa06b675304b4a), ROM_BIOS(4))

	// D+
	ROM_SYSTEM_BIOS(5, "dp", "Maestro D+")
	ROMX_LOAD("m6m_625_u2.u2",  0x0000, 0x8000, CRC(aa7b5cfd) SHA1(e909108fdace633a519fecf0b9876fe6a46b2067), ROM_BIOS(5))
	ROMX_LOAD("b6m_614_u3.u3",  0x8000, 0x8000, CRC(eff75543) SHA1(d7c1b3824bc87d5ffada6f5c8c72a8b292ff3d46), ROM_BIOS(5))

	// D++
	ROM_SYSTEM_BIOS(6, "dpp", "Maestro D++")
	ROMX_LOAD("d++_u2.u2",      0x0000, 0x8000, CRC(48ef032c) SHA1(d336cb2096780b4d3bcceda0d2ed1246e780cd8d), ROM_BIOS(6))
	ROMX_LOAD("b6m_614_u3.u3",  0x8000, 0x8000, CRC(eff75543) SHA1(d7c1b3824bc87d5ffada6f5c8c72a8b292ff3d46), ROM_BIOS(6))
ROM_END

ROM_START( analyst )
	ROM_REGION(0x10000, "maincpu", 0)

	ROM_DEFAULT_BIOS("d1")

	// B (Analyst only)
	ROM_SYSTEM_BIOS(0, "b", "Analyst B")
	ROMX_LOAD("m6l_a15_u2.u2",  0x0000, 0x8000, CRC(91570897) SHA1(e6db36ffc87ce3941a3e12222678069cff9e47f6), ROM_BIOS(0))
	ROMX_LOAD("b6c_721_u3.u3",  0x8000, 0x8000, CRC(b1e57023) SHA1(6cec5cdc0bf4f8ac88afb0397fcb4738136b0431), ROM_BIOS(0))

	// C (C and above are shared Maestro/Analyst)
	ROM_SYSTEM_BIOS(1, "c", "Analyst C")
	ROMX_LOAD("m6l_b30d_u2.u2", 0x0000, 0x8000, CRC(bb10e15c) SHA1(7b0fb987c49da76a03b46c80d2b4eacaa785ee75), ROM_BIOS(1))
	ROMX_LOAD("b6c_721_u3.u3",  0x8000, 0x8000, CRC(b1e57023) SHA1(6cec5cdc0bf4f8ac88afb0397fcb4738136b0431), ROM_BIOS(1))

	// D
	ROM_SYSTEM_BIOS(2, "d1", "Analyst D (set 1)")
	ROMX_LOAD("ma3_714a_u2.u2", 0x0000, 0x8000, CRC(435e1e30) SHA1(0d82df7c40443cb341dacebdf65f33c3e03bce70), ROM_BIOS(2))
	ROMX_LOAD("b6m_b15_u3.u3",  0x8000, 0x8000, CRC(6155de90) SHA1(bb5cdf061dde2d1dc7925d455891c3ade1d274e3), ROM_BIOS(2))

	ROM_SYSTEM_BIOS(3, "d2", "Analyst D (set 2)")
	ROMX_LOAD("ma3_714a_u2.u2", 0x0000, 0x8000, CRC(435e1e30) SHA1(0d82df7c40443cb341dacebdf65f33c3e03bce70), ROM_BIOS(3))
	ROMX_LOAD("b6m_629_u3.u3",  0x8000, 0x8000, CRC(15e7b1f1) SHA1(d2a757114f13c6141d74a15671aa06b675304b4a), ROM_BIOS(3))

	// D+
	ROM_SYSTEM_BIOS(4, "dp", "Analyst D+")
	ROMX_LOAD("m6m_625_u2.u2",  0x0000, 0x8000, CRC(aa7b5cfd) SHA1(e909108fdace633a519fecf0b9876fe6a46b2067), ROM_BIOS(4))
	ROMX_LOAD("b6m_614_u3.u3",  0x8000, 0x8000, CRC(eff75543) SHA1(d7c1b3824bc87d5ffada6f5c8c72a8b292ff3d46), ROM_BIOS(4))

	// D++
	ROM_SYSTEM_BIOS(5, "dpp", "Analyst D++")
	ROMX_LOAD("d++_u2.u2",      0x0000, 0x8000, CRC(48ef032c) SHA1(d336cb2096780b4d3bcceda0d2ed1246e780cd8d), ROM_BIOS(5))
	ROMX_LOAD("b6m_614_u3.u3",  0x8000, 0x8000, CRC(eff75543) SHA1(d7c1b3824bc87d5ffada6f5c8c72a8b292ff3d46), ROM_BIOS(5))
ROM_END

const tiny_rom_entry *saitekosa_maestro_device::device_rom_region() const
{
	return ROM_NAME(maestro);
}

const tiny_rom_entry *saitekosa_analyst_device::device_rom_region() const
{
	return ROM_NAME(analyst);
}


//-------------------------------------------------
//  input_ports - device-specific input ports
//-------------------------------------------------

static INPUT_PORTS_START( maestro )
	PORT_START("FAKE")
	PORT_CONFNAME( 0x07, 0x04, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitekosa_maestro_device, switch_cpu_freq, 0) // factory set
	PORT_CONFSETTING(    0x00, "4MHz" )
	PORT_CONFSETTING(    0x01, "5.67MHz" )
	PORT_CONFSETTING(    0x02, "6MHz" )
	PORT_CONFSETTING(    0x03, "7.2MHz" )
	PORT_CONFSETTING(    0x04, "8MHz" )
	PORT_CONFSETTING(    0x05, "10MHz" )
INPUT_PORTS_END

ioport_constructor saitekosa_maestro_device::device_input_ports() const
{
	return INPUT_PORTS_NAME(maestro);
}


//-------------------------------------------------
//  device_add_mconfig - add device configuration
//-------------------------------------------------

void saitekosa_maestro_device::device_add_mconfig(machine_config &config)
{
	// basic machine hardware
	R65C02(config, m_maincpu, 8_MHz_XTAL);
	m_maincpu->set_addrmap(AS_PROGRAM, &saitekosa_maestro_device::main_map);

	// extension rom
	GENERIC_SOCKET(config, "extrom", generic_plain_slot, "saitek_egr");
	SOFTWARE_LIST(config, "cart_list").set_original("saitek_egr");
}

void saitekosa_analyst_device::device_add_mconfig(machine_config &config)
{
	saitekosa_maestro_device::device_add_mconfig(config);

	// video hardware
	HD44780(config, m_lcd, 0);
	m_lcd->set_lcd_size(2, 8);
}


//-------------------------------------------------
//  internal i/o
//-------------------------------------------------

u8 saitekosa_maestro_device::extrom_r(offs_t offset)
{
	u16 bank = m_extrom_bank * 0x4000;
	return (m_extrom->exists()) ? m_extrom->read_rom(offset | bank) : 0xff;
}

template <int N> void saitekosa_maestro_device::stall_w(u8 data)
{
	// cpu clock divider
}

u8 saitekosa_maestro_device::rts_r()
{
	if (!machine().side_effects_disabled())
	{
		// strobe RTS-P
		m_expansion->rts_w(1);
		m_expansion->rts_w(0);
	}

	return 0xff;
}

void saitekosa_maestro_device::xdata_w(u8 data)
{
	// clock latch
	m_latch = data;
}

u8 saitekosa_maestro_device::xdata_r()
{
	return m_expansion->data_state();
}

void saitekosa_maestro_device::control_w(u8 data)
{
	// d0: main rom bank
	m_rombank->set_entry(data & 1);

	// d1: ext rom bank
	// d1: ram bank
	m_extrom_bank = BIT(data, 1);
	m_rambank->set_entry(m_extrom_bank);

	// d3: enable latch output
	m_latch_enable = bool(data & 8);

	// d2: STB-P
	m_expansion->stb_w(BIT(data, 2));
}

u8 saitekosa_maestro_device::ack_r()
{
	// d6: ?
	// d7: ACK-P
	return m_expansion->ack_state() ? 0x80 : 0x00;
}

void saitekosa_maestro_device::main_map(address_map &map)
{
	map(0x0000, 0x1fff).ram();
	map(0x2000, 0x2000).mirror(0x01ff).w(FUNC(saitekosa_maestro_device::stall_w<0>));
	map(0x2200, 0x2200).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::rts_r), FUNC(saitekosa_maestro_device::stall_w<1>));
	map(0x2400, 0x2400).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::xdata_r), FUNC(saitekosa_maestro_device::xdata_w));
	map(0x2600, 0x2600).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::ack_r), FUNC(saitekosa_maestro_device::control_w));
	map(0x2800, 0x37ff).bankrw("rambank");
	map(0x4000, 0x7fff).r(FUNC(saitekosa_maestro_device::extrom_r));
	map(0x8000, 0xffff).bankr("rombank");
}

void saitekosa_analyst_device::main_map(address_map &map)
{
	saitekosa_maestro_device::main_map(map);
	map(0x3800, 0x3801).mirror(0x07fe).rw(m_lcd, FUNC(hd44780_device::read), FUNC(hd44780_device::write));
}


//-------------------------------------------------
//  host i/o
//-------------------------------------------------

u8 saitekosa_maestro_device::data_r()
{
	return m_latch_enable ? m_latch : 0xff;
}

void saitekosa_maestro_device::nmi_w(int state)
{
	m_maincpu->set_input_line(0, !state ? ASSERT_LINE : CLEAR_LINE);
}

void saitekosa_maestro_device::ack_w(int state)
{
	if (state != m_expansion->ack_state())
		machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
}

u32 saitekosa_analyst_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
	bitmap.fill(0xffffff, cliprect);
	const u8 *render = m_lcd->render();

	// draw lcd characters
	for (int i = 0; i < 16; i++)
	{
		const u8 *src = render + 16 * ((i & 7) + BIT(i, 3) * 40);
		for (int y = 0; y < 8; y++)
			for (int x = 0; x < 5; x++)
				bitmap.pix(y + 4, i * 6 + x + 2) = (BIT(src[y], 4 - x) && m_expansion->pw_state()) ? 0x282828 : 0xe8e8e8;
	}

	return 0;
}