summaryrefslogtreecommitdiffstatshomepage
path: root/docs/source/initialsetup/compilingmame.rst
blob: 177e22fb07209d34e4fe494d5b5f7e0f4171b968 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
Compiling MAME
==============

.. contents:: :local:

.. _compiling-all:

All Platforms
-------------

* Whenever you are changing build parameters, (such as switching between a SDL-based build and a native Windows renderer one, or adding tools to the compile list) you need to run a **make REGENIE=1** to allow the settings to be regenerated. Failure to do this will cause you very difficult to troubleshoot problems.

* If you want to add various additional tools to the compile, such as *CHDMAN*, add a **TOOLS=1** to your make statement, like **make REGENIE=1 TOOLS=1**

* You can do driver specific builds by using *SOURCES=<driver>* in your make statement. For instance, building Pac-Man by itself would be **make SOURCES=src/mame/drivers/pacman.cpp REGENIE=1** including the necessary *REGENIE* for rebuilding the settings.

* Speeding up the compilation can be done by using more cores from your CPU. This is done with the **-j** parameter. *Note: the maximum number you should use is the number of cores your CPU has, plus one. No higher than that will speed up the compilation, and may in fact slow it down.* For instance, **make -j5** on a quad-core CPU will provide optimal speed.

* Debugging information can be added to a compile using *SYMBOLS=1* though most users will not want or need to use this.

Putting all of these together, we get a couple of examples:

Rebuilding MAME for just the Pac-Man driver, with tools, on a quad-core (e.g. i5 or i7) machine:

| **make SOURCES=src/mame/drivers/pacman.cpp TOOLS=1 REGENIE=1 -j5**
|

Rebuilding MAME on a dual-core (e.g. i3 or laptop i5) machine:

| **make -j3**
|


.. _compiling-windows:

Microsoft Windows
-----------------

MAME for Windows is built using the MSYS2 environment.  You will need Windows 7
or later and a reasonably up-to-date MSYS2 installation.  We strongly recommend
building MAME on a 64-bit system.  Instructions may need to be adjusted for
32-bit systems.

* A pre-packaged MSYS2 installation including the prerequisites for building
  MAME can be downloaded from the `MAME Build Tools
  <http://mamedev.org/tools/>`_ page.
* After initial installation, you can update the MSYS2 environment using the
  **pacman** (Arch package manage) command.
* By default, MAME will be built using native Windows OS interfaces for
  window management, audio/video output, font rendering, etc.  If you want to
  use the portable SDL (Simple DirectMedia Layer) interfaces instead, you can
  add **OSD=sdl** to the make options.  The main emulator binary will have an
  ``sdl`` prefix prepended (e.g. ``sdlmame64.exe`` or ``sdlmame.exe``).  You
  will need to install the MSYS2 packages for SDL 2 version 2.0.3 or later.
* By default, MAME will include the native Windows debugger.  To also inculde
  the portable Qt debugger, add **USE_QTDEBUG=1** to the make options.  You
  will need to install the MSYS2 packages for Qt 5.

Using a standard MSYS2 installation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

You may also build MAME using a standard MSYS2 installation and adding the tools
needed for building MAME.  These instructions assume you have some familiarity
with MSYS2 and the **pacman** package manager.

* Install the MSYS2 environment from  the `MSYS2 homepage
  <https://www.msys2.org/>`_.
* Download the latest version of the ``mame-essentials`` package from the
  `MAME package repository <https://repo.mamedev.org/x86_64/>`_ and install it
  using the **pacman** command.
* Add the ``mame`` repository to ``/etc/pacman.conf`` using
  ``/etc/pacman.d/mirrorlist.mame`` for locations.
* Install packages necessary to build MAME.  At the very least, you'll need
  ``bash``, ``git``, ``make``.
* For 64-bit builds you'll need ``mingw-w64-x86_64-gcc`` and
  ``mingw-w64-x86_64-python2``.
* For 32-bit builds you'll need ``mingw-w64-i686-gcc`` and
  ``mingw-w64-i686-python2``.
* For debugging you may want to install ``gdb``.
* To build against the portable SDL interfaces, you'll need
  ``mingw-w64-x86_64-SDL2`` and ``mingw-w64-x86_64-SDL2_ttf`` for 64-bit builds,
  or ``mingw-w64-i686-SDL2`` and ``mingw-w64-i686-SDL2_ttf`` for 32-bit builds.
* To build the Qt debugger, you'll need ``mingw-w64-x86_64-qt5`` for 64-bit
  builds, or ``mingw-w64-i686-qt5`` for 32-bit builds.
* To generate API documentation from source, you'll need ``doxygen``.
* For 64-bit builds, open **MSYS2 MinGW 64-bit** from the start menu, and set
  up the environment variables ``MINGW64`` to ``/mingw64`` and ``MINGW32`` to an
  empty string (e.g. using the command **export MINGW64=/mingw64 MINGW32=** in
  the Bash shell).
* For 32-bit builds, open **MSYS2 MinGW 32-bit** from the start menu, and set
  up the environment variables ``MINGW32`` to ``/mingw32`` and ``MINGW64`` to an
  empty string (e.g. using the command **export MINGW32=/mingw32 MINGW64=** in
  the Bash shell).

Building with Microsoft Visual Studio
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

* You can generate Visual Studio 2017 projects using **make vs2017**.  The
  solution and project files will be created in
  ``build/projects/windows/mame/vs2017`` by default (the name of the ``build``
  folder can be changed using the ``BUILDDIR`` option).  This will always
  regenerate the settings, so **REGENIE=1** is *not* needed.
* Adding **MSBUILD=1** to the make options will build build the solution using
  the Microsoft Build Engine after generating the project files.  Note that this
  requires paths and environment variables to be configured so the correct
  Visual Studio tools can be located.
* MAME can only be compiled with the Visual Studio 15.7.6 tools.  Bugs in newer
  versions of the Microsoft Visual C/C++ compiler prevent it from compiling
  MAME.
* The MSYS2 environment is still required to generate the project files, convert
  built-in layouts, compile UI translations, etc.


.. _compiling-fedora:

Fedora Linux
------------

You'll need a few prerequisites from your distro. Make sure you get SDL2 2.0.3 or 2.0.4 as earlier versions are buggy.

**sudo dnf install gcc gcc-c++ SDL2-devel SDL2_ttf-devel libXi-devel libXinerama-devel qt5-qtbase-devel qt5-qttools expat-devel fontconfig-devel alsa-lib-devel**

Compilation is exactly as described above in All Platforms.


.. _compiling-ubuntu:

Debian and Ubuntu (including Raspberry Pi and ODROID devices)
-------------------------------------------------------------

You'll need a few prerequisites from your distro. Make sure you get SDL2 2.0.3 or 2.0.4 as earlier versions are buggy.

**sudo apt-get install git build-essential python libsdl2-dev libsdl2-ttf-dev libfontconfig-dev qt5-default**

Compilation is exactly as described above in All Platforms.


.. _compiling-arch:

Arch Linux
----------

You'll need a few prerequisites from your distro.

**sudo pacman -S base-devel git sdl2 gconf sdl2_ttf gcc qt5**

Compilation is exactly as described above in All Platforms.


.. _compiling-macos:

Apple Mac OS X
--------------

You'll need a few prerequisites to get started. Make sure you're on OS X 10.9 Mavericks or later. You will NEED SDL2 2.0.4 for OS X.

* Install **Xcode** from the Mac App Store
* Launch **Xcode**. It will download a few additional prerequisites. Let this run through before proceeding.
* Once that's done, quit **Xcode** and open a **Terminal** window
* Type **xcode-select --install** to install additional tools necessary for MAME

Next you'll need to get SDL2 installed.

* Go to `this site <http://libsdl.org/download-2.0.php>`_ and download the *Mac OS X* .dmg file
* If the .dmg doesn't auto-open, open it
* Click 'Macintosh HD' (or whatever your Mac's hard disk is named) in the left pane of a **Finder** window, then open the **Library** folder and drag the **SDL2.framework** folder from the SDL disk image into the **Frameworks** folder

Lastly to begin compiling, use Terminal to navigate to where you have the MAME source tree (*cd* command) and follow the normal compilation instructions from above in All Platforms.

It's possible to get MAME working from 10.6, but a bit more complicated:

* You'll need to install clang-3.7, ld64, libcxx and python27 from MacPorts
* Then add these options to your make command or useroptions.mak:

|
| OVERRIDE_CC=/opt/local/bin/clang-mp-3.7
| OVERRIDE_CXX=/opt/local/bin/clang++-mp-3.7
| PYTHON_EXECUTABLE=/opt/local/bin/python2.7
| ARCHOPTS=-stdlib=libc++
|


.. _compiling-emscripten:

Emscripten Javascript and HTML
------------------------------

First, download and install Emscripten 1.37.29 or later by following the instructions at the `official site <https://kripken.github.io/emscripten-site/docs/getting_started/downloads.html>`_

Once Emscripten has been installed, it should be possible to compile MAME out-of-the-box using Emscripten's '**emmake**' tool. Because a full MAME compile is too large to load into a web browser at once, you will want to use the SOURCES parameter to compile only a subset of the project, e.g. (in the mame directory):

**emmake make SUBTARGET=pacmantest SOURCES=src/mame/drivers/pacman.cpp**

The SOURCES parameter should have the path to at least one driver .cpp file. The make process will attempt to locate and include all dependencies necessary to produce a complete build including the specified driver(s). However, sometimes it is necessary to manually specify additional files (using commas) if this process misses something. E.g.:

**emmake make SUBTARGET=apple2e SOURCES=src/mame/drivers/apple2e.cpp,src/mame/machine/applefdc.cpp**

The value of the SUBTARGET parameter serves only to differentiate multiple builds and need not be set to any specific value.

Emscripten supports compiling to WebAssembly with a JavaScript loader instead of all-JavaScript, and in later versions this is actually the default. To force WebAssembly on or off, add WEBASSEMBLY=1 or WEBASSEMBLY=0 to the make command line.

Other make parameters can also be used, e.g. *-j* for multithreaded compilation as described earlier.

When the compilation reaches the emcc phase, you may see a number of *"unresolved symbol"* warnings. At the moment, this is expected for OpenGL-related functions such as glPointSize. Any others may indicate that an additional dependency file needs to be specified in the SOURCES list. Unfortunately this process is not automated and you will need to search the source tree to locate the files supplying the missing symbols. You may also be able to get away with ignoring the warnings if the code path referencing them is not used at run-time.

If all goes well, a .js file will be output to the current directory. This file cannot be run by itself, but requires an HTML loader to provide it with a canvas to output to and pass in command-line parameters. The `Emularity project <https://github.com/db48x/emularity>`_ provides such a loader.

There are example .html files in that repository which can be edited to point to your newly compiled MAME js filename and pass in whatever parameters you desire. You will then need to place all of the following on a web server:

* The compiled MAME .js file
* The compiled MAME .wasm file if using WebAssembly
* The .js files from the Emularity package (loader.js, browserfs.js, etc.)
* A .zip file with the ROMs for the MAME driver you would like to run (if any)
* Any software files you would like to run with the MAME driver
* An Emularity loader .html modified to point to all of the above

You need to use a web server instead of opening the local files directly due to security restrictions in modern web browsers.

If the result fails to run, you can open the Web Console in your browser to see any error output which may have been produced (e.g. missing or incorrect ROM files). A "ReferenceError: foo is not defined" error most likely indicates that a needed source file was omitted from the SOURCES list.


.. _compiling-options:

Useful Options
--------------

This section summarises some of the more useful options recognised by the main
makefile.  You use these options by appending them to the **make** command,
setting them as environment variables, or adding them to your prefix makefile.
Note that in order to apply many of these settings when rebuilding, you need to
set **REGENIE=1** the first time you build after changing the option(s).  Also
note that GENie *does not* automatically rebuild affected files when you change
an option that affects compiler settings.

Overall build options
~~~~~~~~~~~~~~~~~~~~~

PREFIX_MAKEFILE
   Name of a makefile to include for additional options if found (defaults to
   **useroptions.mak**).  May be useful if you want to quickly switch between
   different build configurations.
BUILDDIR
   Set to change the name of the subfolder used for project files, generated
   sources, object files, and intermediate libraries (defaults to **build**).
REGENIE
   Set to **1** to force project files to be regenerated.
VERBOSE
   Set to **1** to show full commands when using GNU make as the build tool.
   This option applies immediately without needing regenerate project files.
IGNORE_GIT
   Set to **1** to skip the working tree scan and not attempt to embed a git
   revision description in the version string.

Tool locations
~~~~~~~~~~~~~~

OVERRIDE_CC
   Set the C/Objective-C compiler command.  (This sets the target C compiler
   command when cross-compiling.)
OVERRIDE_CXX
   Set the C++/Objective-C++ compiler command.  (This sets the target C++
   compiler command when cross-compiling.)
OVERRIDE_LD
   Set the linker command.  This is often not necessary or useful because the C
   or C++ compiler command is used to invoke the linker.  (This sets the target
   linker command when cross-compiling.)
PYTHON_EXECUTABLE
   Set the Python interpreter command.  You need Python 2.7 or Python 3 to build
   MAME.
CROSS_BUILD
   Set to **1** to use separate host and target compilers and linkers, as
   required for cross-compilation.  In this case, **OVERRIDE_CC**,
   **OVERRIDE_CXX** and **OVERRIDE_LD** set the target C compiler, C++ compiler
   and linker commands, while **CC**, **CXX** and **LD** set the host C
   compiler, C++ compiler and linker commands.

Optional features
~~~~~~~~~~~~~~~~~

TOOLS
   Set to **1** to build additional tools along with the emulator, including
   **unidasm**, **chdman**, **romcmp**, and **srcclean**.
NO_USE_PORTAUDIO
   Set to **1** to disable building the PortAudio sound output module.
USE_QTDEBUG
   Set to **1** to include the Qt debugger on platforms where it's not built by
   default (e.g. Windows or MacOS), or to **0** to disable it.  You'll need to
   install Qt development libraries and tools to build the Qt debugger.  The
   process depends on the platform.

Compilation options
~~~~~~~~~~~~~~~~~~~

NOWERROR
   Set to **1** to disable treating compiler warnings as errors.  This may be
   needed in marginally supported configurations.
DEPRECATED
   Set to **0** to disable deprecation warnings (note that deprecation warnings
   are not treated as errors).
DEBUG
   Set to **1** to enable runtime assertion checks and additional diagnostics.
   Note that this has a performance cost, and is most useful for developers.
OPTIMIZE
   Set optimisation level.  The default is **3** to favour performance at the
   expense of larger executable size.  Set to **0** to disable optimisation (can
   make debugging easier), **1** for basic optimisation that doesn't have a
   space/speed trade-off and doesn't have a large impact on compile time, **2**
   to enable most optimisation that improves performance and reduces size, or
   **s** to enable only optimisations that generally don't increase executable
   size.  The exact set of supported values depends on your compiler.
SYMBOLS
   Set to **1** to include additional debugging symbols over the default for the
   target platform (many target platforms include function name symbols by
   default).
SYMLEVEL
   Numeric value that controls the level of detail in debugging symbols.  Higher
   numbers make debugging easier at the cost of increased build time and
   executable size.  The supported values depend on your compiler.  For GCC and
   similar compilers, **1** includes line number tables and external variables,
   **2** also includes local variables, and **3** also includes macro
   definitions.
ARCHOPTS
   Additional command-line options to pass to the compiler and linker.  This is
   useful for supplying code generation or ABI options, for example to enable
   support for optional CPU features.
ARCHOPTS_C
   Additional command-line options to pass to the compiler when compiling C
   source files.
ARCHOPTS_CXX
   Additional command-line options to pass to the compiler when compiling C++
   source files.
ARCHOPTS_OBJC
   Additional command-line options to pass to the compiler when compiling
   Objective-C source files.
ARCHOPTS_OBJCXX
   Additional command-line options to pass to the compiler when compiling
   Objective-C++ source files.

Library/framework locations
~~~~~~~~~~~~~~~~~~~~~~~~~~~

SDL_INSTALL_ROOT
   SDL installation root directory for shared library style SDL.
SDL_FRAMEWORK_PATH
   Search path for SDL framework.
USE_LIBSDL
   Set to **1** to use shared library style SDL on targets where framework is
   default.
USE_SYSTEM_LIB_ASIO
   Set to **1** to prefer the system installation of the Asio C++ asynchronous
   I/O library over the version provided with the MAME source.
USE_SYSTEM_LIB_EXPAT
   Set to **1** to prefer the system installation of the Expat XML parser
   library over the version provided with the MAME source.
USE_SYSTEM_LIB_ZLIB
   Set to **1** to prefer the system installation of the zlib data compression
   library over the version provided with the MAME source.
USE_SYSTEM_LIB_JPEG
   Set to **1** to prefer the system installation of the libjpeg image
   compression library over the version provided with the MAME source.
USE_SYSTEM_LIB_FLAC
   Set to **1** to prefer the system installation of the libFLAC audio
   compression library over the version provided with the MAME source.
USE_SYSTEM_LIB_LUA
   Set to **1** to prefer the system installation of the embedded Lua
   interpreter over the version provided with the MAME source.
USE_SYSTEM_LIB_SQLITE3
   Set to **1** to prefer the system installation of the SQLITE embedded
   database engine over the version provided with the MAME source.
USE_SYSTEM_LIB_PORTMIDI
   Set to **1** to prefer the system installation of the PortMidi library over
   the version provided with the MAME source.
USE_SYSTEM_LIB_PORTAUDIO
   Set to **1** to prefer the system installation of the PortAudio library over
   the version provided with the MAME source.
USE_BUNDLED_LIB_SDL2
   Set to **1** to prefer the version of SDL provided with the MAME source over
   the system installation.  (This is enabled by default for Visual Studio and
   Android builds.  For other configurations, the system installation of SDL is
   preferred.)
USE_SYSTEM_LIB_UTF8PROC
   Set to **1** to prefer the system installation of the Julia utf8proc library
   over the version provided with the MAME source.
USE_SYSTEM_LIB_GLM
   Set to **1** to prefer the system installation of the GLM OpenGL Mathematics
   library over the version provided with the MAME source.
USE_SYSTEM_LIB_RAPIDJSON
   Set to **1** to prefer the system installation of the Tencent RapidJSON
   library over the version provided with the MAME source.
USE_SYSTEM_LIB_PUGIXML
   Set to **1** to prefer the system installation of the pugixml library over
   the version provided with the MAME source.


.. _compiling-issues:

Known Issues
------------

Issues with specific compiler versions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

* GCC 5 for Linux reports spurious errors on encountering deprecation warnings.
  Adding **DEPRECATED=0** to your build options works around this by disabling
  deprecation warnings.
* MinGW GCC 7 for Windows i386 produces spurious out-of-bounds access warnings.
  Adding **NOWERROR=1** to your build options works around this by not treating
  warnings as errors.
* Initial versions of GNU libstdc++ 6 have a broken ``std::unique_ptr``
  implementation.  If you encounter errors with ``std::unique_ptr`` you need to
  upgrade to a newer version of libstdc++ that fixes the issue.

GNU C Library fortify source feature
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The GNU C Library has options to perform additional compile- and run-time
checks on string operations, enabled by defining the ``_FORTIFY_SOURCE``
preprocessor macro.  This is intended to improve security at the cost of a
small amount of overhead.  MAME is not secure software, and we do not
support building with ``_FORTIFY_SOURCE`` defined.

Some Linux distributions (including Gentoo and Ubuntu) have patched GCC to
define ``_FORTIFY_SOURCE`` to ``1`` as a built-in macro.  This is problematic
for more projects than just MAME, as it makes it hard to disable the additional
checks (e.g. if you don't want the performance impact of the run-time checks),
and it also makes it hard to define ``_FORTIFY_SOURCE`` to ``2`` if you want to
enable stricter checks.  You should really take it up with the distribution
maintainers, and make it clear you don't want non-standard GCC behaviour. It
would be better if these distributions defined this macro by default in their
packaging environments if they think it's important, rather than trying to force
it on everything compiled on their distributions. (This is what Red Hat does:
the ``_FORTIFY_SOURCE`` macro is set in the RPM build environment, and not by
distributing a modified version of GCC.)

If you get compilation errors in ``bits/string_fortified.h`` you should first
ensure that the ``_FORTIY_SOURCE`` macro is defined via the environment (e.g.
a **CFLAGS** or **CXXFLAGS** environment variable).  You can check to see
whether the ``_FORTIFY_SOURCE`` macro is a built-in macro with your version of
GCC with a command like this:

**gcc -dM -E - < /dev/null | grep _FORTIFY_SOURCE**

If ``_FORTIFY_SOURCE`` is defined to a non-zero value by default, you can work
around it by adding **-U_FORTIFY_SOURCE** to the compiler flags (e.g. by using
the **ARCHOPTS** setting, or setting the **CFLAGS** and **CXXFLAGS** environment
variables.


.. _compiling-unusual:

Unusual Build Configurations
----------------------------

Cross-compiling MAME
~~~~~~~~~~~~~~~~~~~~

MAME's build system has basic support for cross-compilation.  Set
**CROSS_BUILD=1** to enable separate host and target compilers, set
**OVERRIDE_CC** and **OVERRIDE_CXX** to the target C/C++ compiler commands, and
if necessary set **CC** and **CXX** to the host C/C++ compiler commands.  If the
target OS is different to the host OS, set it with **TARGETOS**.  For example it
may be possible to build a MinGW32 x64 build on a Linux host using a command
like this:

**make TARGETOS=windows PTR64=1 OVERRIDE_CC=x86_64-w64-mingw32-gcc OVERRIDE_CXX=x86_64-w64-mingw32-g++ OVERRIDE_LD=x86_64-w64-mingw32-ld MINGW64=/usr**

(The additional packages required for producing a standard MinGW32 x64 build on
a Fedora Linux host are ``mingw64-gcc-c++``, ``mingw64-winpthreads-static`` and
their dependencies.  Non-standard builds may require additional packages.)

Using libc++ on Linux
~~~~~~~~~~~~~~~~~~~~~

MAME may be built using the LLVM project's "libc++" C++ Standard Library.  The
prerequisites are a working clang/LLVM installation, and the libc++ development
libraries.  On Fedora Linux, the necessary packages are **libcxx**,
**libcxx-devel**, **libcxxabi** and **libcxxabi-devel**.  Set the C and C++
compiler commands to use clang, and add **-stdlib=libc++** to the C++ compiler
and linker options.  You could use a command like this:

**env LDFLAGS=-stdlib=libc++ make OVERRIDE_CC=clang OVERRIDE_CXX=clang++ ARCHOPTS_CXX=-stdlib=libc++ ARCHOPTS_OBJCXX=-stdlib=libc++**

The options following the **make** command may be placed in a prefix makefile if
you want to use this configuration regularly, but **LDFLAGS** needs to be be set
in the environment.

Using a GCC/GNU libstdc++ installation in a non-standard location on Linux
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

GCC may be built and installed to a custom location, typically by supplying the
**--prefix=** option to the **configure** command.  This may be useful if you
want to build MAME on a Linux distribution that still uses a version of GNU
libstdC++ that predates C++14 support.  To use an alternate GCC installation to,
build MAME, set the C and C++ compilers to the full paths to the **gcc** and
**g++** commands, and add the library path to the run-time search path.  If you
installed GCC in /opt/local/gcc63, you might use a command like this:

**make OVERRIDE_CC=/opt/local/gcc63/bin/gcc OVERRIDE_CXX=/opt/local/gcc63/bin/g++ ARCHOPTS=-Wl,-R,/opt/local/gcc63/lib64**

You can add these options to a prefix makefile if you plan to use this
configuration regularly.
62 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
// license:BSD-3-Clause
// copyright-holders:Aaron Giles
/* PowerPC common opcodes */

// it really seems like this should be elsewhere - like maybe the floating point checks can hang out someplace else
#include <math.h>

#ifndef PPC_DRC
static void ppc_unimplemented(UINT32 op)
{
	fatalerror("ppc: Unimplemented opcode %08X at %08X\n", op, ppc.pc);
}

static void ppc_addx(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);

	REG(RT) = ra + rb;

	if( OEBIT ) {
		SET_ADD_OV(REG(RT), ra, rb);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_addcx(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);

	REG(RT) = ra + rb;

	SET_ADD_CA(REG(RT), ra, rb);

	if( OEBIT ) {
		SET_ADD_OV(REG(RT), ra, rb);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}
#endif

static void ppc_addex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);
	UINT32 carry = (XER >> 29) & 0x1;
	UINT32 tmp;

	tmp = rb + carry;
	REG(RT) = ra + tmp;

	if( ADD_CA(tmp, rb, carry) || ADD_CA(REG(RT), ra, tmp) )
		XER |= XER_CA;
	else
		XER &= ~XER_CA;

	if( OEBIT ) {
		SET_ADD_OV(REG(RT), ra, rb);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

#ifndef PPC_DRC
static void ppc_addi(UINT32 op)
{
	UINT32 i = SIMM16;
	UINT32 a = RA;

	if( a )
		i += REG(a);

	REG(RT) = i;
}

static void ppc_addic(UINT32 op)
{
	UINT32 i = SIMM16;
	UINT32 ra = REG(RA);

	REG(RT) = ra + i;

	if( ADD_CA(REG(RT), ra, i) )
		XER |= XER_CA;
	else
		XER &= ~XER_CA;
}

static void ppc_addic_rc(UINT32 op)
{
	UINT32 i = SIMM16;
	UINT32 ra = REG(RA);

	REG(RT) = ra + i;

	if( ADD_CA(REG(RT), ra, i) )
		XER |= XER_CA;
	else
		XER &= ~XER_CA;

	SET_CR0(REG(RT));
}

static void ppc_addis(UINT32 op)
{
	UINT32 i = UIMM16 << 16;
	UINT32 a = RA;

	if( a )
		i += REG(a);

	REG(RT) = i;
}
#endif

static void ppc_addmex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 carry = (XER >> 29) & 0x1;
	UINT32 tmp;

	tmp = ra + carry;
	REG(RT) = tmp + -1;

	if( ADD_CA(tmp, ra, carry) || ADD_CA(REG(RT), tmp, -1) )
		XER |= XER_CA;
	else
		XER &= ~XER_CA;

	if( OEBIT ) {
		SET_ADD_OV(REG(RT), ra, carry - 1);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_addzex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 carry = (XER >> 29) & 0x1;

	REG(RT) = ra + carry;

	if( ADD_CA(REG(RT), ra, carry) )
		XER |= XER_CA;
	else
		XER &= ~XER_CA;

	if( OEBIT ) {
		SET_ADD_OV(REG(RT), ra, carry);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

#ifndef PPC_DRC
static void ppc_andx(UINT32 op)
{
	REG(RA) = REG(RS) & REG(RB);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_andcx(UINT32 op)
{
	REG(RA) = REG(RS) & ~REG(RB);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_andi_rc(UINT32 op)
{
	UINT32 i = UIMM16;

	REG(RA) = REG(RS) & i;

	SET_CR0(REG(RA));
}

static void ppc_andis_rc(UINT32 op)
{
	UINT32 i = UIMM16 << 16;

	REG(RA) = REG(RS) & i;

	SET_CR0(REG(RA));
}

static void ppc_bx(UINT32 op)
{
	INT32 li = op & 0x3fffffc;
	if( li & 0x2000000 )
		li |= 0xfc000000;

	if( AABIT ) {
		ppc.npc = li;
	} else {
		ppc.npc = ppc.pc + li;
	}

	if( LKBIT ) {
		LR = ppc.pc + 4;
	}
}

static void ppc_bcx(UINT32 op)
{
	int condition = check_condition_code(BO, BI);

	if( condition ) {
		if( AABIT ) {
			ppc.npc = SIMM16 & ~0x3;
		} else {
			ppc.npc = ppc.pc + (SIMM16 & ~0x3);
		}
	}

	if( LKBIT ) {
		LR = ppc.pc + 4;
	}
}

static void ppc_bcctrx(UINT32 op)
{
	int condition = check_condition_code(BO, BI);

	if( condition ) {
		ppc.npc = CTR & ~0x3;
	}

	if( LKBIT ) {
		LR = ppc.pc + 4;
	}
}

static void ppc_bclrx(UINT32 op)
{
	int condition = check_condition_code(BO, BI);

	if( condition ) {
		ppc.npc = LR & ~0x3;
	}

	if( LKBIT ) {
		LR = ppc.pc + 4;
	}
}

static void ppc_cmp(UINT32 op)
{
	INT32 ra = REG(RA);
	INT32 rb = REG(RB);
	int d = CRFD;

	if( ra < rb )
		CR(d) = 0x8;
	else if( ra > rb )
		CR(d) = 0x4;
	else
		CR(d) = 0x2;

	if( XER & XER_SO )
		CR(d) |= 0x1;
}

static void ppc_cmpi(UINT32 op)
{
	INT32 ra = REG(RA);
	INT32 i = SIMM16;
	int d = CRFD;

	if( ra < i )
		CR(d) = 0x8;
	else if( ra > i )
		CR(d) = 0x4;
	else
		CR(d) = 0x2;

	if( XER & XER_SO )
		CR(d) |= 0x1;
}

static void ppc_cmpl(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);
	int d = CRFD;

	if( ra < rb )
		CR(d) = 0x8;
	else if( ra > rb )
		CR(d) = 0x4;
	else
		CR(d) = 0x2;

	if( XER & XER_SO )
		CR(d) |= 0x1;
}

static void ppc_cmpli(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 i = UIMM16;
	int d = CRFD;

	if( ra < i )
		CR(d) = 0x8;
	else if( ra > i )
		CR(d) = 0x4;
	else
		CR(d) = 0x2;

	if( XER & XER_SO )
		CR(d) |= 0x1;
}

static void ppc_cntlzw(UINT32 op)
{
	int n = 0;
	int t = RT;
	UINT32 m = 0x80000000;

	while(n < 32)
	{
		if( REG(t) & m )
			break;
		m >>= 1;
		n++;
	}

	REG(RA) = n;

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}
#endif

static void ppc_crand(UINT32 op)
{
	int bit = RT;
	int b = CRBIT(RA) & CRBIT(RB);
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_crandc(UINT32 op)
{
	int bit = RT;
	int b = CRBIT(RA) & ~CRBIT(RB);
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_creqv(UINT32 op)
{
	int bit = RT;
	int b = ~(CRBIT(RA) ^ CRBIT(RB));
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_crnand(UINT32 op)
{
	int bit = RT;
	int b = ~(CRBIT(RA) & CRBIT(RB));
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_crnor(UINT32 op)
{
	int bit = RT;
	int b = ~(CRBIT(RA) | CRBIT(RB));
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_cror(UINT32 op)
{
	int bit = RT;
	int b = CRBIT(RA) | CRBIT(RB);
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_crorc(UINT32 op)
{
	int bit = RT;
	int b = CRBIT(RA) | ~CRBIT(RB);
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

static void ppc_crxor(UINT32 op)
{
	int bit = RT;
	int b = CRBIT(RA) ^ CRBIT(RB);
	if( b & 0x1 )
		CR(bit / 4) |= _BIT(3-(bit % 4));
	else
		CR(bit / 4) &= ~_BIT(3-(bit % 4));
}

#ifndef PPC_DRC
static void ppc_dcbf(UINT32 op)
{
}

static void ppc_dcbi(UINT32 op)
{
}

static void ppc_dcbst(UINT32 op)
{
}

static void ppc_dcbt(UINT32 op)
{
}

static void ppc_dcbtst(UINT32 op)
{
}

static void ppc_dcbz(UINT32 op)
{
}
#endif

static void ppc_divwx(UINT32 op)
{
	if( REG(RB) == 0 && REG(RA) < 0x80000000 )
	{
		REG(RT) = 0;
		if( OEBIT ) {
			XER |= XER_SO | XER_OV;
		}
	}
	else if( REG(RB) == 0 || (REG(RB) == 0xffffffff && REG(RA) == 0x80000000) )
	{
		REG(RT) = 0xffffffff;
		if( OEBIT ) {
			XER |= XER_SO | XER_OV;
		}
	}
	else
	{
		REG(RT) = (INT32)REG(RA) / (INT32)REG(RB);
		if( OEBIT ) {
			XER &= ~XER_OV;
		}
	}

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_divwux(UINT32 op)
{
	if( REG(RB) == 0 )
	{
		REG(RT) = 0;
		if( OEBIT ) {
			XER |= XER_SO | XER_OV;
		}
	}
	else
	{
		REG(RT) = (UINT32)REG(RA) / (UINT32)REG(RB);
		if( OEBIT ) {
			XER &= ~XER_OV;
		}
	}

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

#ifndef PPC_DRC
static void ppc_eieio(UINT32 op)
{
}

static void ppc_eqvx(UINT32 op)
{
	REG(RA) = ~(REG(RS) ^ REG(RB));

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_extsbx(UINT32 op)
{
	REG(RA) = (INT32)(INT8)REG(RS);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_extshx(UINT32 op)
{
	REG(RA) = (INT32)(INT16)REG(RS);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_icbi(UINT32 op)
{
}

static void ppc_isync(UINT32 op)
{
}

static void ppc_lbz(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	REG(RT) = (UINT32)READ8(ea);
}

static void ppc_lbzu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	REG(RT) = (UINT32)READ8(ea);
	REG(RA) = ea;
}

static void ppc_lbzux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	REG(RT) = (UINT32)READ8(ea);
	REG(RA) = ea;
}

static void ppc_lbzx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	REG(RT) = (UINT32)READ8(ea);
}

static void ppc_lha(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	REG(RT) = (INT32)(INT16)READ16(ea);
}

static void ppc_lhau(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	REG(RT) = (INT32)(INT16)READ16(ea);
	REG(RA) = ea;
}

static void ppc_lhaux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	REG(RT) = (INT32)(INT16)READ16(ea);
	REG(RA) = ea;
}

static void ppc_lhax(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	REG(RT) = (INT32)(INT16)READ16(ea);
}

static void ppc_lhbrx(UINT32 op)
{
	UINT32 ea;
	UINT16 w;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	w = READ16(ea);
	REG(RT) = (UINT32)BYTE_REVERSE16(w);
}

static void ppc_lhz(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	REG(RT) = (UINT32)READ16(ea);
}

static void ppc_lhzu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	REG(RT) = (UINT32)READ16(ea);
	REG(RA) = ea;
}

static void ppc_lhzux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	REG(RT) = (UINT32)READ16(ea);
	REG(RA) = ea;
}

static void ppc_lhzx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	REG(RT) = (UINT32)READ16(ea);
}
#endif

static void ppc_lmw(UINT32 op)
{
	int r = RT;
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	while( r <= 31 )
	{
		REG(r) = READ32(ea);
		ea += 4;
		r++;
	}
}

static void ppc_lswi(UINT32 op)
{
	int n, r, i;
	UINT32 ea = 0;
	if( RA != 0 )
		ea = REG(RA);

	if( RB == 0 )
		n = 32;
	else
		n = RB;

	r = RT - 1;
	i = 0;

	while(n > 0)
	{
		if (i == 0) {
			r = (r + 1) % 32;
			REG(r) = 0;
		}
		REG(r) |= ((READ8(ea) & 0xff) << (24 - i));
		i += 8;
		if (i == 32) {
			i = 0;
		}
		ea++;
		n--;
	}
}

static void ppc_lswx(UINT32 op)
{
	int n, r, i;
	UINT32 ea = 0;
	if( RA != 0 )
		ea = REG(RA);

	ea += REG(RB);

	n = ppc.xer & 0x7f;

	r = RT - 1;
	i = 0;

	while(n > 0)
	{
		if (i == 0) {
			r = (r + 1) % 32;
			REG(r) = 0;
		}
		REG(r) |= ((READ8(ea) & 0xff) << (24 - i));
		i += 8;
		if (i == 32) {
			i = 0;
		}
		ea++;
		n--;
	}
}

static void ppc_lwarx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	ppc.reserved_address = ea;
	ppc.reserved = 1;

	REG(RT) = READ32(ea);
}

#ifndef PPC_DRC
static void ppc_lwbrx(UINT32 op)
{
	UINT32 ea;
	UINT32 w;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	w = READ32(ea);
	REG(RT) = BYTE_REVERSE32(w);
}

static void ppc_lwz(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	REG(RT) = READ32(ea);
}

static void ppc_lwzu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	REG(RT) = READ32(ea);
	REG(RA) = ea;
}

static void ppc_lwzux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	REG(RT) = READ32(ea);
	REG(RA) = ea;
}

static void ppc_lwzx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	REG(RT) = READ32(ea);
}

static void ppc_mcrf(UINT32 op)
{
	CR(RT >> 2) = CR(RA >> 2);
}

static void ppc_mcrxr(UINT32 op)
{
	CR(RT >> 2) = (XER >> 28) & 0x0F;
	XER &= ~0xf0000000;
}

static void ppc_mfcr(UINT32 op)
{
	REG(RT) = ppc_get_cr();
}

static void ppc_mfmsr(UINT32 op)
{
	REG(RT) = ppc_get_msr();
}

static void ppc_mfspr(UINT32 op)
{
	REG(RT) = ppc_get_spr(SPR);
}
#endif

static void ppc_mtcrf(UINT32 op)
{
	int fxm = FXM;
	int t = RT;

	if( fxm & 0x80 )    CR(0) = (REG(t) >> 28) & 0xf;
	if( fxm & 0x40 )    CR(1) = (REG(t) >> 24) & 0xf;
	if( fxm & 0x20 )    CR(2) = (REG(t) >> 20) & 0xf;
	if( fxm & 0x10 )    CR(3) = (REG(t) >> 16) & 0xf;
	if( fxm & 0x08 )    CR(4) = (REG(t) >> 12) & 0xf;
	if( fxm & 0x04 )    CR(5) = (REG(t) >> 8) & 0xf;
	if( fxm & 0x02 )    CR(6) = (REG(t) >> 4) & 0xf;
	if( fxm & 0x01 )    CR(7) = (REG(t) >> 0) & 0xf;
}

#ifndef PPC_DRC
static void ppc_mtmsr(UINT32 op)
{
	ppc_set_msr(REG(RS));
}

static void ppc_mtspr(UINT32 op)
{
	ppc_set_spr(SPR, REG(RS));
}

static void ppc_mulhwx(UINT32 op)
{
	INT64 ra = (INT64)(INT32)REG(RA);
	INT64 rb = (INT64)(INT32)REG(RB);

	REG(RT) = (UINT32)((ra * rb) >> 32);

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_mulhwux(UINT32 op)
{
	UINT64 ra = (UINT64)REG(RA);
	UINT64 rb = (UINT64)REG(RB);

	REG(RT) = (UINT32)((ra * rb) >> 32);

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_mulli(UINT32 op)
{
	INT32 ra = (INT32)REG(RA);
	INT32 i = SIMM16;

	REG(RT) = ra * i;
}

static void ppc_mullwx(UINT32 op)
{
	INT64 ra = (INT64)(INT32)REG(RA);
	INT64 rb = (INT64)(INT32)REG(RB);
	INT64 r;

	r = ra * rb;
	REG(RT) = (UINT32)r;

	if( OEBIT ) {
		XER &= ~XER_OV;

		if( r != (INT64)(INT32)r )
			XER |= XER_OV | XER_SO;
	}

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_nandx(UINT32 op)
{
	REG(RA) = ~(REG(RS) & REG(RB));

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_negx(UINT32 op)
{
	REG(RT) = -REG(RA);

	if( OEBIT ) {
		if( REG(RT) == 0x80000000 )
			XER |= XER_OV | XER_SO;
		else
			XER &= ~XER_OV;
	}

	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_norx(UINT32 op)
{
	REG(RA) = ~(REG(RS) | REG(RB));

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_orx(UINT32 op)
{
	REG(RA) = REG(RS) | REG(RB);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_orcx(UINT32 op)
{
	REG(RA) = REG(RS) | ~REG(RB);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_ori(UINT32 op)
{
	REG(RA) = REG(RS) | UIMM16;
}

static void ppc_oris(UINT32 op)
{
	REG(RA) = REG(RS) | (UIMM16 << 16);
}

static void ppc_rfi(UINT32 op)
{
	UINT32 msr;
	ppc.npc = ppc_get_spr(SPR_SRR0);
	msr = ppc_get_spr(SPR_SRR1);
	ppc_set_msr( msr );
}

static void ppc_rlwimix(UINT32 op)
{
	UINT32 r;
	UINT32 mask = GET_ROTATE_MASK(MB, ME);
	UINT32 rs = REG(RS);
	int sh = SH;

	r = (rs << sh) | (rs >> (32-sh));
	REG(RA) = (REG(RA) & ~mask) | (r & mask);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_rlwinmx(UINT32 op)
{
	UINT32 r;
	UINT32 mask = GET_ROTATE_MASK(MB, ME);
	UINT32 rs = REG(RS);
	int sh = SH;

	r = (rs << sh) | (rs >> (32-sh));
	REG(RA) = r & mask;

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_rlwnmx(UINT32 op)
{
	UINT32 r;
	UINT32 mask = GET_ROTATE_MASK(MB, ME);
	UINT32 rs = REG(RS);
	int sh = REG(RB) & 0x1f;

	r = (rs << sh) | (rs >> (32-sh));
	REG(RA) = r & mask;

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}
#endif

#ifndef PPC_DRC
static void ppc_sc(UINT32 op)
{
	if (ppc.is603) {
		ppc603_exception(EXCEPTION_SYSTEM_CALL);
	}
	if (ppc.is602) {
		ppc602_exception(EXCEPTION_SYSTEM_CALL);
	}
	if (IS_PPC403()) {
		ppc403_exception(EXCEPTION_SYSTEM_CALL);
	}
}
#endif

static void ppc_slwx(UINT32 op)
{
	int sh = REG(RB) & 0x3f;

	if( sh > 31 ) {
		REG(RA) = 0;
	}
	else {
		REG(RA) = REG(RS) << sh;
	}

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_srawx(UINT32 op)
{
	int sh = REG(RB) & 0x3f;

	XER &= ~XER_CA;

	if( sh > 31 ) {
		if (REG(RS) & 0x80000000)
			REG(RA) = 0xffffffff;
		else
			REG(RA) = 0;
		if( REG(RA) )
			XER |= XER_CA;
	}
	else {
		REG(RA) = (INT32)(REG(RS)) >> sh;
		if( ((INT32)(REG(RS)) < 0) && (REG(RS) & BITMASK_0(sh)) )
			XER |= XER_CA;
	}

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_srawix(UINT32 op)
{
	int sh = SH;

	XER &= ~XER_CA;
	if( ((INT32)(REG(RS)) < 0) && (REG(RS) & BITMASK_0(sh)) )
		XER |= XER_CA;

	REG(RA) = (INT32)(REG(RS)) >> sh;

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_srwx(UINT32 op)
{
	int sh = REG(RB) & 0x3f;

	if( sh > 31 ) {
		REG(RA) = 0;
	}
	else {
		REG(RA) = REG(RS) >> sh;
	}

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

#ifndef PPC_DRC
static void ppc_stb(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	WRITE8(ea, (UINT8)REG(RS));
}

static void ppc_stbu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	WRITE8(ea, (UINT8)REG(RS));
	REG(RA) = ea;
}

static void ppc_stbux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	WRITE8(ea, (UINT8)REG(RS));
	REG(RA) = ea;
}

static void ppc_stbx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	WRITE8(ea, (UINT8)REG(RS));
}

static void ppc_sth(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	WRITE16(ea, (UINT16)REG(RS));
}

static void ppc_sthbrx(UINT32 op)
{
	UINT32 ea;
	UINT16 w;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	w = REG(RS);
	WRITE16(ea, (UINT16)BYTE_REVERSE16(w));
}

static void ppc_sthu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	WRITE16(ea, (UINT16)REG(RS));
	REG(RA) = ea;
}

static void ppc_sthux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	WRITE16(ea, (UINT16)REG(RS));
	REG(RA) = ea;
}

static void ppc_sthx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	WRITE16(ea, (UINT16)REG(RS));
}
#endif

static void ppc_stmw(UINT32 op)
{
	UINT32 ea;
	int r = RS;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	while( r <= 31 )
	{
		WRITE32(ea, REG(r));
		ea += 4;
		r++;
	}
}

static void ppc_stswi(UINT32 op)
{
	int n, r, i;
	UINT32 ea = 0;
	if( RA != 0 )
		ea = REG(RA);

	if( RB == 0 )
		n = 32;
	else
		n = RB;

	r = RT - 1;
	i = 0;

	while(n > 0)
	{
		if (i == 0) {
			r = (r + 1) % 32;
		}
		WRITE8(ea, (REG(r) >> (24-i)) & 0xff);
		i += 8;
		if (i == 32) {
			i = 0;
		}
		ea++;
		n--;
	}
}

static void ppc_stswx(UINT32 op)
{
	int n, r, i;
	UINT32 ea = 0;
	if( RA != 0 )
		ea = REG(RA);

	ea += REG(RB);

	n = ppc.xer & 0x7f;

	r = RT - 1;
	i = 0;

	while(n > 0)
	{
		if (i == 0) {
			r = (r + 1) % 32;
		}
		WRITE8(ea, (REG(r) >> (24-i)) & 0xff);
		i += 8;
		if (i == 32) {
			i = 0;
		}
		ea++;
		n--;
	}
}

#ifndef PPC_DRC
static void ppc_stw(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = SIMM16;
	else
		ea = REG(RA) + SIMM16;

	WRITE32(ea, REG(RS));
}

static void ppc_stwbrx(UINT32 op)
{
	UINT32 ea;
	UINT32 w;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	w = REG(RS);
	WRITE32(ea, BYTE_REVERSE32(w));
}
#endif

static void ppc_stwcx_rc(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	if( ppc.reserved ) {
		WRITE32(ea, REG(RS));

		ppc.reserved = 0;
		ppc.reserved_address = 0;

		CR(0) = 0x2;
		if( XER & XER_SO )
			CR(0) |= 0x1;
	} else {
		CR(0) = 0;
		if( XER & XER_SO )
			CR(0) |= 0x1;
	}
}

#ifndef PPC_DRC
static void ppc_stwu(UINT32 op)
{
	UINT32 ea = REG(RA) + SIMM16;

	WRITE32(ea, REG(RS));
	REG(RA) = ea;
}

static void ppc_stwux(UINT32 op)
{
	UINT32 ea = REG(RA) + REG(RB);

	WRITE32(ea, REG(RS));
	REG(RA) = ea;
}

static void ppc_stwx(UINT32 op)
{
	UINT32 ea;

	if( RA == 0 )
		ea = REG(RB);
	else
		ea = REG(RA) + REG(RB);

	WRITE32(ea, REG(RS));
}

static void ppc_subfx(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);
	REG(RT) = rb - ra;

	if( OEBIT ) {
		SET_SUB_OV(REG(RT), rb, ra);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}
#endif

static void ppc_subfcx(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);
	REG(RT) = rb - ra;

	SET_SUB_CA(REG(RT), rb, ra);

	if( OEBIT ) {
		SET_SUB_OV(REG(RT), rb, ra);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

#ifndef PPC_DRC
static void ppc_subfex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 rb = REG(RB);
	UINT32 carry = (XER >> 29) & 0x1;
	UINT32 r;

	r = ~ra + carry;
	REG(RT) = rb + r;

	SET_ADD_CA(r, ~ra, carry);      /* step 1 carry */
	if( REG(RT) < r )               /* step 2 carry */
		XER |= XER_CA;

	if( OEBIT ) {
		SET_SUB_OV(REG(RT), rb, ra);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_subfic(UINT32 op)
{
	UINT32 i = SIMM16;
	UINT32 ra = REG(RA);

	REG(RT) = i - ra;

	SET_SUB_CA(REG(RT), i, ra);
}
#endif

static void ppc_subfmex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 carry = (XER >> 29) & 0x1;
	UINT32 r;

	r = ~ra + carry;
	REG(RT) = r - 1;

	SET_SUB_CA(r, ~ra, carry);      /* step 1 carry */
	if( REG(RT) < r )
		XER |= XER_CA;              /* step 2 carry */

	if( OEBIT ) {
		SET_SUB_OV(REG(RT), -1, ra);
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

static void ppc_subfzex(UINT32 op)
{
	UINT32 ra = REG(RA);
	UINT32 carry = (XER >> 29) & 0x1;

	REG(RT) = ~ra + carry;

	SET_ADD_CA(REG(RT), ~ra, carry);

	if( OEBIT ) {
		SET_SUB_OV(REG(RT), 0, REG(RA));
	}
	if( RCBIT ) {
		SET_CR0(REG(RT));
	}
}

#ifndef PPC_DRC
static void ppc_sync(UINT32 op)
{
}
#endif

#ifndef PPC_DRC
static void ppc_tw(UINT32 op)
{
	int exception = 0;
	INT32 a = REG(RA);
	INT32 b = REG(RB);
	int to = RT;

	if( (a < b) && (to & 0x10) ) {
		exception = 1;
	}
	if( (a > b) && (to & 0x08) ) {
		exception = 1;
	}
	if( (a == b) && (to & 0x04) ) {
		exception = 1;
	}
	if( ((UINT32)a < (UINT32)b) && (to & 0x02) ) {
		exception = 1;
	}
	if( ((UINT32)a > (UINT32)b) && (to & 0x01) ) {
		exception = 1;
	}

	if (exception) {
		if (ppc.is603) {
			ppc603_exception(EXCEPTION_TRAP);
		}
		if (ppc.is602) {
			ppc602_exception(EXCEPTION_TRAP);
		}
		if (IS_PPC403()) {
			ppc403_exception(EXCEPTION_TRAP);
		}
	}
}
#endif

#ifndef PPC_DRC
static void ppc_twi(UINT32 op)
{
	int exception = 0;
	INT32 a = REG(RA);
	INT32 i = SIMM16;
	int to = RT;

	if( (a < i) && (to & 0x10) ) {
		exception = 1;
	}
	if( (a > i) && (to & 0x08) ) {
		exception = 1;
	}
	if( (a == i) && (to & 0x04) ) {
		exception = 1;
	}
	if( ((UINT32)a < (UINT32)i) && (to & 0x02) ) {
		exception = 1;
	}
	if( ((UINT32)a > (UINT32)i) && (to & 0x01) ) {
		exception = 1;
	}

	if (exception) {
		if (ppc.is603) {
			ppc603_exception(EXCEPTION_TRAP);
		}
		if (ppc.is602) {
			ppc602_exception(EXCEPTION_TRAP);
		}
		if (IS_PPC403()) {
			ppc403_exception(EXCEPTION_TRAP);
		}
	}
}
#endif

#ifndef PPC_DRC
static void ppc_xorx(UINT32 op)
{
	REG(RA) = REG(RS) ^ REG(RB);

	if( RCBIT ) {
		SET_CR0(REG(RA));
	}
}

static void ppc_xori(UINT32 op)
{
	REG(RA) = REG(RS) ^ UIMM16;
}

static void ppc_xoris(UINT32 op)
{
	REG(RA) = REG(RS) ^ (UIMM16 << 16);
}



static void ppc_invalid(UINT32 op)
{
	fatalerror("ppc: Invalid opcode %08X PC : %X\n", op, ppc.pc);
}
#endif


// Everything below is new from AJG

////////////////////////////
// !here are the 6xx ops! //
////////////////////////////

#define DOUBLE_SIGN     (U64(0x8000000000000000))
#define DOUBLE_EXP      (U64(0x7ff0000000000000))
#define DOUBLE_FRAC     (U64(0x000fffffffffffff))
#define DOUBLE_ZERO     (0)

/*
  Floating point operations.
*/

INLINE int is_nan_double(FPR x)
{
	return( ((x.id & DOUBLE_EXP) == DOUBLE_EXP) &&
			((x.id & DOUBLE_FRAC) != DOUBLE_ZERO) );
}

INLINE int is_qnan_double(FPR x)
{
	return( ((x.id & DOUBLE_EXP) == DOUBLE_EXP) &&
			((x.id & U64(0x0007fffffffffff)) == U64(0x000000000000000)) &&
			((x.id & U64(0x000800000000000)) == U64(0x000800000000000)) );
}

INLINE int is_snan_double(FPR x)
{
	return( ((x.id & DOUBLE_EXP) == DOUBLE_EXP) &&
			((x.id & DOUBLE_FRAC) != DOUBLE_ZERO) &&
			((x.id & U64(0x0008000000000000)) == DOUBLE_ZERO) );
}

INLINE int is_infinity_double(FPR x)
{
	return( ((x.id & DOUBLE_EXP) == DOUBLE_EXP) &&
			((x.id & DOUBLE_FRAC) == DOUBLE_ZERO) );
}

INLINE int is_normalized_double(FPR x)
{
	UINT64 exp;

	exp = (x.id & DOUBLE_EXP) >> 52;

	return (exp >= 1) && (exp <= 2046);
}

INLINE int is_denormalized_double(FPR x)
{
	return( ((x.id & DOUBLE_EXP) == 0) &&
			((x.id & DOUBLE_FRAC) != DOUBLE_ZERO) );
}

INLINE int sign_double(FPR x)
{
	return ((x.id & DOUBLE_SIGN) != 0);
}

INLINE INT64 round_to_nearest(FPR f)
{
	if (f.fd >= 0)
	{
		return (INT64)(f.fd + 0.5);
	}
	else
	{
		return -(INT64)(-f.fd + 0.5);
	}
}

INLINE INT64 round_toward_zero(FPR f)
{
	return (INT64)(f.fd);
}

INLINE INT64 round_toward_positive_infinity(FPR f)
{
	double r = ceil(f.fd);
	return (INT64)(r);
}

INLINE INT64 round_toward_negative_infinity(FPR f)
{
	double r = floor(f.fd);
	return (INT64)(r);
}


INLINE void set_fprf(FPR f)
{
	UINT32 fprf;

	// see page 3-30, 3-31

	if (is_qnan_double(f))
	{
		fprf = 0x11;
	}
	else if (is_infinity_double(f))
	{
		if (sign_double(f))     // -INF
			fprf = 0x09;
		else                    // +INF
			fprf = 0x05;
	}
	else if (is_normalized_double(f))
	{
		if (sign_double(f))     // -Normalized
			fprf = 0x08;
		else                    // +Normalized
			fprf = 0x04;
	}
	else if (is_denormalized_double(f))
	{
		if (sign_double(f))     // -Denormalized
			fprf = 0x18;
		else                    // +Denormalized
			fprf = 0x14;
	}
	else    // Zero
	{
		if (sign_double(f))     // -Zero
			fprf = 0x12;
		else                    // +Zero
			fprf = 0x02;
	}

	ppc.fpscr &= ~0x0001f000;
	ppc.fpscr |= (fprf << 12);
}



#define SET_VXSNAN(a, b)    if (is_snan_double(a) || is_snan_double(b)) ppc.fpscr |= 0x80000000
#define SET_VXSNAN_1(c)     if (is_snan_double(c)) ppc.fpscr |= 0x80000000




static void ppc_lfs(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	if(a)
		ea += REG(a);

	f.i = READ32(ea);
	FPR(t).fd = (double)(f.f);
}

static void ppc_lfsu(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	ea += REG(a);

	f.i = READ32(ea);
	FPR(t).fd = (double)(f.f);

	REG(a) = ea;
}

#ifndef PPC_DRC
static void ppc_lfd(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;

	if(a)
		ea += REG(a);

	FPR(t).id = READ64(ea);
}

static void ppc_lfdu(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 d = RD;

	ea += REG(a);

	FPR(d).id = READ64(ea);

	REG(a) = ea;
}
#endif

static void ppc_stfs(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	if(a)
		ea += REG(a);

	f.f = (float)(FPR(t).fd);
	WRITE32(ea, f.i);
}

static void ppc_stfsu(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	ea += REG(a);

	f.f = (float)(FPR(t).fd);
	WRITE32(ea, f.i);

	REG(a) = ea;
}

#ifndef PPC_DRC
static void ppc_stfd(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;

	if(a)
		ea += REG(a);

	WRITE64(ea, FPR(t).id);
}

static void ppc_stfdu(UINT32 op)
{
	UINT32 ea = SIMM16;
	UINT32 a = RA;
	UINT32 t = RT;

	ea += REG(a);

	WRITE64(ea, FPR(t).id);

	REG(a) = ea;
}

static void ppc_lfdux(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 d = RD;

	ea += REG(a);

	FPR(d).id = READ64(ea);

	REG(a) = ea;
}

static void ppc_lfdx(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 d = RD;

	if(a)
		ea += REG(a);

	FPR(d).id = READ64(ea);
}
#endif

static void ppc_lfsux(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	ea += REG(a);

	f.i = READ32(ea);
	FPR(t).fd = (double)(f.f);

	REG(a) = ea;
}

static void ppc_lfsx(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	if(a)
		ea += REG(a);

	f.i = READ32(ea);
	FPR(t).fd = (double)(f.f);
}

static void ppc_mfsr(UINT32 op)
{
	UINT32 sr = (op >> 16) & 15;
	UINT32 t = RT;

	CHECK_SUPERVISOR();

	REG(t) = ppc.sr[sr];
}

static void ppc_mfsrin(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_SUPERVISOR();

	REG(t) = ppc.sr[REG(b) >> 28];
}

static void ppc_mftb(UINT32 op)
{
	UINT32 x = SPRF;

	switch(x)
	{
		case 268:   REG(RT) = (UINT32)(ppc_read_timebase()); break;
		case 269:   REG(RT) = (UINT32)(ppc_read_timebase() >> 32); break;
		default:    fatalerror("ppc: Invalid timebase register %d at %08X\n", x, ppc.pc); break;
	}
}

static void ppc_mtsr(UINT32 op)
{
	UINT32 sr = (op >> 16) & 15;
	UINT32 t = RT;

	CHECK_SUPERVISOR();

	ppc.sr[sr] = REG(t);
}

static void ppc_mtsrin(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_SUPERVISOR();

	ppc.sr[REG(b) >> 28] = REG(t);
}

#ifndef PPC_DRC
static void ppc_dcba(UINT32 op)
{
	/* TODO: Cache not emulated so this opcode doesn't need to be implemented */
}

static void ppc_stfdux(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;

	ea += REG(a);

	WRITE64(ea, FPR(t).id);

	REG(a) = ea;
}
#endif

static void ppc_stfdx(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;

	if(a)
		ea += REG(a);

	WRITE64(ea, FPR(t).id);
}

static void ppc_stfiwx(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;

	if(a)
		ea += REG(a);

	WRITE32(ea, (UINT32)FPR(t).id);
}

static void ppc_stfsux(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	ea += REG(a);

	f.f = (float)(FPR(t).fd);
	WRITE32(ea, f.i);

	REG(a) = ea;
}

static void ppc_stfsx(UINT32 op)
{
	UINT32 ea = REG(RB);
	UINT32 a = RA;
	UINT32 t = RT;
	FPR32 f;

	if(a)
		ea += REG(a);

	f.f = (float)(FPR(t).fd);

	WRITE32(ea, f.i);
}

#ifndef PPC_DRC
static void ppc_tlbia(UINT32 op)
{
	/* TODO: TLB not emulated so this opcode doesn't need to implemented */
}

static void ppc_tlbie(UINT32 op)
{
	/* TODO: TLB not emulated so this opcode doesn't need to implemented */
}

static void ppc_tlbsync(UINT32 op)
{
	/* TODO: TLB not emulated so this opcode doesn't need to implemented */
}

static void ppc_eciwx(UINT32 op)
{
	ppc_unimplemented(op);
}

static void ppc_ecowx(UINT32 op)
{
	ppc_unimplemented(op);
}
#endif

static void ppc_fabsx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	FPR(t).id = FPR(b).id & ~DOUBLE_SIGN;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_faddx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = FPR(a).fd + FPR(b).fd;

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fcmpo(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = (RT >> 2);
	UINT32 c;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	if(is_nan_double(FPR(a)) || is_nan_double(FPR(b)))
	{
		c = 1; /* OX */
		if(is_snan_double(FPR(a)) || is_snan_double(FPR(b))) {
			ppc.fpscr |= 0x01000000; /* VXSNAN */

			if(!(ppc.fpscr & 0x40000000) || is_qnan_double(FPR(a)) || is_qnan_double(FPR(b)))
				ppc.fpscr |= 0x00080000; /* VXVC */
		}
	}
	else if(FPR(a).fd < FPR(b).fd){
		c = 8; /* FX */
	}
	else if(FPR(a).fd > FPR(b).fd){
		c = 4; /* FEX */
	}
	else {
		c = 2; /* VX */
	}

	CR(t) = c;

	ppc.fpscr &= ~0x0001F000;
	ppc.fpscr |= (c << 12);
}

static void ppc_fcmpu(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = (RT >> 2);
	UINT32 c;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	if(is_nan_double(FPR(a)) || is_nan_double(FPR(b)))
	{
		c = 1; /* OX */
		if(is_snan_double(FPR(a)) || is_snan_double(FPR(b))) {
			ppc.fpscr |= 0x01000000; /* VXSNAN */
		}
	}
	else if(FPR(a).fd < FPR(b).fd){
		c = 8; /* FX */
	}
	else if(FPR(a).fd > FPR(b).fd){
		c = 4; /* FEX */
	}
	else {
		c = 2; /* VX */
	}

	CR(t) = c;

	ppc.fpscr &= ~0x0001F000;
	ppc.fpscr |= (c << 12);
}

static void ppc_fctiwx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;
	INT64 r = 0;

	// TODO: fix FPSCR flags FX,VXSNAN,VXCVI

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	switch(ppc.fpscr & 3)
	{
		case 0: r = (INT64)round_to_nearest(FPR(b)); break;
		case 1: r = (INT64)round_toward_zero(FPR(b)); break;
		case 2: r = (INT64)round_toward_positive_infinity(FPR(b)); break;
		case 3: r = (INT64)round_toward_negative_infinity(FPR(b)); break;
	}

	if(r > (INT64)((INT32)0x7FFFFFFF))
	{
		FPR(t).id = 0x7FFFFFFF;
		// FPSCR[FR] = 0
		// FPSCR[FI] = 1
		// FPSCR[XX] = 1
	}
	else if(FPR(b).fd < (INT64)((INT32)0x80000000))
	{
		FPR(t).id = 0x80000000;
		// FPSCR[FR] = 1
		// FPSCR[FI] = 1
		// FPSCR[XX] = 1
	}
	else
	{
		FPR(t).id = (UINT32)r;
		// FPSCR[FR] = t.iw > t.fd
		// FPSCR[FI] = t.iw == t.fd
		// FPSCR[XX] = ?
	}

	// FPSCR[FPRF] = undefined (leave it as is)
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fctiwzx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;
	INT64 r;

	// TODO: fix FPSCR flags FX,VXSNAN,VXCVI

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));
	r = round_toward_zero(FPR(b));

	if(r > (INT64)((INT32)0x7fffffff))
	{
		FPR(t).id = 0x7fffffff;
		// FPSCR[FR] = 0
		// FPSCR[FI] = 1
		// FPSCR[XX] = 1

	}
	else if(r < (INT64)((INT32)0x80000000))
	{
		FPR(t).id = 0x80000000;
		// FPSCR[FR] = 1
		// FPSCR[FI] = 1
		// FPSCR[XX] = 1
	}
	else
	{
		FPR(t).id = (UINT32)r;
		// FPSCR[FR] = t.iw > t.fd
		// FPSCR[FI] = t.iw == t.fd
		// FPSCR[XX] = ?
	}

	// FPSCR[FPRF] = undefined (leave it as is)
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fdivx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = FPR(a).fd / FPR(b).fd;

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmrx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	FPR(t).fd = FPR(b).fd;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnabsx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	FPR(t).id = FPR(b).id | DOUBLE_SIGN;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnegx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	FPR(t).id = FPR(b).id ^ DOUBLE_SIGN;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_frspx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	FPR(t).fd = (float)FPR(b).fd;

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_frsqrtex(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	FPR(t).fd = 1.0 / sqrt(FPR(b).fd);  /* verify this */

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fsqrtx(UINT32 op)
{
	/* NOTE: PPC603e doesn't support this opcode */
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	FPR(t).fd = (double)(sqrt(FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fsubx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = FPR(a).fd - FPR(b).fd;

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mffsx(UINT32 op)
{
	FPR(RT).id = (UINT32)ppc.fpscr;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mtfsb0x(UINT32 op)
{
	UINT32 crbD;

	crbD = (op >> 21) & 0x1F;

	if (crbD != 1 && crbD != 2) // these bits cannot be explicitly cleared
		ppc.fpscr &= ~(1 << (31 - crbD));

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mtfsb1x(UINT32 op)
{
	UINT32 crbD;

	crbD = (op >> 21) & 0x1F;

	if (crbD != 1 && crbD != 2) // these bits cannot be explicitly cleared
		ppc.fpscr |= (1 << (31 - crbD));

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mtfsfx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 f = FM;

	f = ppc_field_xlat[FM];

	ppc.fpscr &= (~f) | ~(FPSCR_FEX | FPSCR_VX);
	ppc.fpscr |= (UINT32)(FPR(b).id) & ~(FPSCR_FEX | FPSCR_VX);

	// FEX, VX

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mtfsfix(UINT32 op)
{
	UINT32 crfd = CRFD;
	UINT32 imm = (op >> 12) & 0xF;

	/*
	 * According to the manual:
	 *
	 * If bits 0 and 3 of FPSCR are to be modified, they take the immediate
	 * value specified. Bits 1 and 2 (FEX and VX) are set according to the
	 * "usual rule" and not from IMM[1-2].
	 *
	 * The "usual rule" is not emulated, so these bits simply aren't modified
	 * at all here.
	 */

	crfd = (7 - crfd) * 4;  // calculate LSB position of field

	if (crfd == 28)         // field containing FEX and VX is special...
	{                       // bits 1 and 2 of FPSCR must not be altered
		ppc.fpscr &= 0x9fffffff;
		ppc.fpscr |= (imm & 0x9fffffff);
	}

	ppc.fpscr &= ~(0xf << crfd);    // clear field
	ppc.fpscr |= (imm << crfd);     // insert new data

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_mcrfs(UINT32 op)
{
	UINT32 crfs, f;
	crfs = CRFA;

	f = ppc.fpscr >> ((7 - crfs) * 4);  // get crfS field from FPSCR
	f &= 0xf;

	switch(crfs)    // determine which exception bits to clear in FPSCR
	{
		case 0:     // FX, OX
			ppc.fpscr &= ~0x90000000;
			break;
		case 1:     // UX, ZX, XX, VXSNAN
			ppc.fpscr &= ~0x0f000000;
			break;
		case 2:     // VXISI, VXIDI, VXZDZ, VXIMZ
			ppc.fpscr &= ~0x00F00000;
			break;
		case 3:     // VXVC
			ppc.fpscr &= ~0x00080000;
			break;
		case 5:     // VXSOFT, VXSQRT, VXCVI
			ppc.fpscr &= ~0x00000e00;
			break;
		default:
			break;
	}

	CR(CRFD) = f;
}

static void ppc_faddsx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = (float)(FPR(a).fd + FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fdivsx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = (float)(FPR(a).fd / FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fresx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	FPR(t).fd = 1.0 / FPR(b).fd; /* ??? */

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fsqrtsx(UINT32 op)
{
	/* NOTE: This opcode is not supported in PPC603e */
	UINT32 b = RB;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN_1(FPR(b));

	FPR(t).fd = (float)(sqrt(FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fsubsx(UINT32 op)
{
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));

	FPR(t).fd = (float)(FPR(a).fd - FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmaddx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = ((FPR(a).fd * FPR(c).fd) + FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmsubx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = ((FPR(a).fd * FPR(c).fd) - FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmulx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(c));

	FPR(t).fd = (FPR(a).fd * FPR(c).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnmaddx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (-((FPR(a).fd * FPR(c).fd) + FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnmsubx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (-((FPR(a).fd * FPR(c).fd) - FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fselx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	FPR(t).fd = (FPR(a).fd >= 0.0) ? FPR(c).fd : FPR(b).fd;

	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmaddsx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (float)((FPR(a).fd * FPR(c).fd) + FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmsubsx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (float)((FPR(a).fd * FPR(c).fd) - FPR(b).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fmulsx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();
	SET_VXSNAN(FPR(a), FPR(c));

	FPR(t).fd = (float)(FPR(a).fd * FPR(c).fd);

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnmaddsx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (float)(-((FPR(a).fd * FPR(c).fd) + FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}

static void ppc_fnmsubsx(UINT32 op)
{
	UINT32 c = RC;
	UINT32 b = RB;
	UINT32 a = RA;
	UINT32 t = RT;

	CHECK_FPU_AVAILABLE();

	SET_VXSNAN(FPR(a), FPR(b));
	SET_VXSNAN_1(FPR(c));

	FPR(t).fd = (float)(-((FPR(a).fd * FPR(c).fd) - FPR(b).fd));

	set_fprf(FPR(t));
	if( RCBIT ) {
		SET_CR1();
	}
}