// license:BSD-3-Clause // copyright-holders:Raphael Nabet, Michael Zapf /* Intel 28F640J5 Flash ROM emulation (could also handle 28F320J5 with minor changes, and possibly 28F256J3, 28F128J3, 28F640J3 and 28F320J3) The 28F640J5 is a 64Mbit FEEPROM that can be accessed either on an 8-bit or a 16-bit bus. References: Datasheets were found on Intel's site (www.intel.com) Raphael Nabet 2004, based on MAME's intelfsh.c core Device is currently only used in ti99/tn_usbsm Rewritten as class Michael Zapf, 2014 TODO: Make it work */ #include "emu.h" #include "strata.h" #define FEEPROM_SIZE 0x800000 // 64Mbit #define BLOCK_SIZE 0x020000 #define BLOCKLOCK_SIZE ((FEEPROM_SIZE/BLOCK_SIZE+7)/8) #define WRBUF_SIZE 32 #define PROT_REGS_SIZE 18 #define COMPLETE_SIZE FEEPROM_SIZE + WRBUF_SIZE + PROT_REGS_SIZE + BLOCKLOCK_SIZE #define ADDRESS_MASK 0x7fffff #define BLOCK_ADDRESS_MASK 0x7e0000 #define BLOCK_ADDRESS_SHIFT 17 #define BYTE_ADDRESS_MASK 0x01ffff /* accessors for individual block lock flags */ #define READ_BLOCKLOCK(block) ((m_blocklock[(block) >> 3] >> ((block) & 7)) & 1) #define SET_BLOCKLOCK(block) (m_blocklock[(block) >> 3] |= 1 << ((block) & 7)) #define CLEAR_BLOCKLOCK(block) (m_blocklock[(block) >> 3] &= ~(1 << ((block) & 7))) DEFINE_DEVICE_TYPE(STRATAFLASH, strataflash_device, "strataflash", "Intel 28F640J5") strataflash_device::strataflash_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, STRATAFLASH, tag, owner, clock) , device_nvram_interface(mconfig, *this) { } //------------------------------------------------- // nvram_default - called to initialize NVRAM to // its default state //------------------------------------------------- void strataflash_device::nvram_default() { memset(m_flashmemory.get(), 0, COMPLETE_SIZE); } //------------------------------------------------- // nvram_read - called to read NVRAM from the // .nv file //------------------------------------------------- void strataflash_device::nvram_read(emu_file &file) { file.read(m_flashmemory.get(), COMPLETE_SIZE); // TODO /* uint8_t buf; int i; // version flag if (file->read(& buf, 1) != 1) return 1; if (buf != 0) return 1; // chip state: master lock if (file->read(& buf, 1) != 1) return 1; m_master_lock = buf & 1; // main FEEPROM area if (file->read(m_flashmemory, FEEPROM_SIZE) != FEEPROM_SIZE) return 1; for (i = 0; i < FEEPROM_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_flashmemory[i]); *ptr = little_endianize_int16(*ptr); } // protection registers if (file->read(m_prot_regs, PROT_REGS_SIZE) != PROT_REGS_SIZE) return 1; for (i = 0; i < PROT_REGS_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_prot_regs[i]); *ptr = little_endianize_int16(*ptr); } // block lock flags if (file->read(m_blocklock, BLOCKLOCK_SIZE) != BLOCKLOCK_SIZE) return 1; return 0; */ } //------------------------------------------------- // nvram_write - called to write NVRAM to the // .nv file //------------------------------------------------- void strataflash_device::nvram_write(emu_file &file) { // TODO /* uint8_t buf; int i; // version flag buf = 0; if (file->write(& buf, 1) != 1) return 1; // chip state: lower boot block lockout, higher boot block lockout, software data protect buf = m_master_lock; if (file->write(& buf, 1) != 1) return 1; // main FEEPROM area for (i = 0; i < FEEPROM_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_flashmemory[i]); *ptr = little_endianize_int16(*ptr); } if (file->write(m_flashmemory, FEEPROM_SIZE) != FEEPROM_SIZE) return 1; for (i = 0; i < FEEPROM_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_flashmemory[i]); *ptr = little_endianize_int16(*ptr); } // protection registers for (i = 0; i < PROT_REGS_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_prot_regs[i]); *ptr = little_endianize_int16(*ptr); } if (file->write(m_prot_regs, PROT_REGS_SIZE) != PROT_REGS_SIZE) return 1; for (i = 0; i < PROT_REGS_SIZE; i += 2) { uint16_t *ptr = (uint16_t *) (&m_prot_regs[i]); *ptr = little_endianize_int16(*ptr); } // block lock flags if (file->write(m_blocklock, BLOCKLOCK_SIZE) != BLOCKLOCK_SIZE) return 1; return 0; */ file.write(m_flashmemory.get(), COMPLETE_SIZE); } //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- void strataflash_device::device_start() { m_mode = FM_NORMAL; m_status = 0x80; m_master_lock = 0; m_flashmemory = std::make_unique(COMPLETE_SIZE); m_wrbuf = m_flashmemory.get() + FEEPROM_SIZE; m_prot_regs = m_wrbuf + WRBUF_SIZE; m_blocklock = m_prot_regs + PROT_REGS_SIZE; // clear various FEEPROM areas memset(m_prot_regs, 0xff, 18); memset(m_flashmemory.get(), 0xff, FEEPROM_SIZE); memset(m_blocklock, 0x00, BLOCKLOCK_SIZE); // set-up factory-programmed protection register segment m_prot_regs[BYTE_XOR_LE(0)] &= 0xfe; for (int i=2; i<10; i++) m_prot_regs[i] = machine().rand(); } /* read a 8/16-bit word from FEEPROM */ uint16_t strataflash_device::read8_16(offs_t offset, bus_width_t bus_width) { switch (bus_width) { case bw_8: offset &= ADDRESS_MASK; break; case bw_16: offset &= ADDRESS_MASK & ~1; } switch (m_mode) { default: case FM_NORMAL: switch (bus_width) { case bw_8: return m_flashmemory[BYTE_XOR_LE(offset)]; case bw_16: return *(uint16_t*)(m_flashmemory.get()+offset); } break; case FM_READSTATUS: return m_status; case FM_WRBUFPART1: return 0x80; case FM_READID: if ((offset >= 0x100) && (offset < 0x112)) { /* protection registers */ switch (bus_width) { case bw_8: return m_prot_regs[BYTE_XOR_LE(offset)]; case bw_16: return *(uint16_t*)(m_prot_regs+offset); } } else switch (offset >> 1) { case 0: // maker ID return 0x89; // Intel case 1: // chip ID return 0x15; // 64 Mbit default: if (((offset & BYTE_ADDRESS_MASK) >> 1) == 2) { // block lock config return READ_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT); } return 0; // default case case 3: // master lock config if (m_master_lock) return 1; else return 0; } break; case FM_READQUERY: switch (offset >> 1) { case 0x00: // maker ID return 0x89; // Intel case 0x01: // chip ID return 0x15; // 64 Mbit default: if (((offset & BYTE_ADDRESS_MASK) >> 1) == 2) { // block lock config return READ_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT); } return 0; // default case #if 0 case 0x03: // master lock config if (m_flash_master_lock) return 1; else return 0; #endif /* CFI query identification string */ case 0x10: return 'Q'; case 0x11: return 'R'; case 0x12: return 'Y'; case 0x13: return 0x01; case 0x14: return 0x00; case 0x15: return 0x31; case 0x16: return 0x00; case 0x17: case 0x18: case 0x19: case 0x1a: return 0x00; /* system interface information: voltage */ case 0x1b: return 0x45; case 0x1c: return 0x55; case 0x1d: return 0x00; case 0x1e: return 0x00; /* system interface information: timings */ case 0x1f: return /*0x07*/0x00; case 0x20: return /*0x07*/0x00; case 0x21: return /*0x0a*/0x00; case 0x22: return 0x00; case 0x23: return /*0x04*/0x00; case 0x24: return /*0x04*/0x00; case 0x25: return /*0x04*/0x00; case 0x26: return 0x00; /* device geometry definition */ case 0x27: return 0x17; case 0x28: return 0x02; case 0x29: return 0x00; case 0x2a: return 0x05; case 0x2b: return 0x00; case 0x2c: return 0x01; case 0x2d: return 0x3f; case 0x2e: return 0x00; case 0x2f: return 0x00; case 0x30: return 0x02; /* primary vendor-specific extended query */ case 0x31: return 'P'; case 0x32: return 'R'; case 0x33: return 'I'; case 0x34: return '1'; case 0x35: return '1'; case 0x36: return 0x0a; case 0x37: return 0x00; case 0x38: return 0x00; case 0x39: return 0x00; case 0x3a: return 0x01; case 0x3b: return 0x01; case 0x3c: return 0x00; case 0x3d: return 0x50; case 0x3e: return 0x00; case 0x3f: return 0x00; } } return 0; } /* write a 8/16-bit word to FEEPROM */ void strataflash_device::write8_16(offs_t offset, uint16_t data, bus_width_t bus_width) { switch (bus_width) { case bw_8: offset &= ADDRESS_MASK; break; case bw_16: offset &= ADDRESS_MASK & ~1; break; } switch (m_mode) { case FM_NORMAL: case FM_READID: case FM_READQUERY: case FM_READSTATUS: switch (data) { case 0xff: // read array m_mode = FM_NORMAL; break; case 0x90: // read identifier codes m_mode = FM_READID; break; case 0x98: // read query m_mode = FM_READQUERY; break; case 0x70: // read status register m_mode = FM_READSTATUS; break; case 0x50: // clear status register m_mode = FM_READSTATUS; m_status &= 0xC5; break; case 0xe8: // write to buffer m_mode = FM_WRBUFPART1; m_wrbuf_base = offset & BLOCK_ADDRESS_MASK; /*m_status &= 0xC5;*/ break; case 0x40: case 0x10: // program m_mode = FM_WRITEPART1; m_status &= 0xC5; break; case 0x20: // block erase m_mode = FM_CLEARPART1; m_status &= 0xC5; break; case 0xb0: // block erase, program suspend /* not emulated (erase is instantaneous) */ break; case 0xd0: // block erase, program resume /* not emulated (erase is instantaneous) */ break; case 0xb8: // configuration m_mode = FM_CONFPART1; m_status &= 0xC5; break; case 0x60: // set master lock m_mode = FM_SETLOCK; m_status &= 0xC5; break; case 0xc0: // protection program m_mode = FM_WRPROTPART1; m_status &= 0xC5; break; default: logerror("Unknown flash mode byte %x\n", data); break; } break; case FM_WRBUFPART1: m_mode = FM_WRBUFPART2; if (((offset & BLOCK_ADDRESS_MASK) != m_wrbuf_base) || (data >= 0x20)) { m_status |= 0x30; m_wrbuf_len = 0; m_wrbuf_count = data; } else { switch (bus_width) { case bw_8: m_wrbuf_len = data+1; break; case bw_16: m_wrbuf_len = (data+1) << 1; break; } m_wrbuf_count = data; } break; case FM_WRBUFPART2: m_mode = FM_WRBUFPART3; if (((offset & BLOCK_ADDRESS_MASK) != m_wrbuf_base) || (((offset & BYTE_ADDRESS_MASK) + m_wrbuf_len) > BLOCK_SIZE)) { m_status |= 0x30; m_wrbuf_len = 0; m_wrbuf_base = 0; } else m_wrbuf_base = offset; memset(m_wrbuf, 0xff, m_wrbuf_len); /* right??? */ [[fallthrough]]; case FM_WRBUFPART3: if ((offset < m_wrbuf_base) || (offset >= (m_wrbuf_base + m_wrbuf_len))) m_status |= 0x30; else { switch (bus_width) { case bw_8: m_wrbuf[offset-m_wrbuf_base] = data; break; case bw_16: m_wrbuf[offset-m_wrbuf_base] = data & 0xff; m_wrbuf[offset-m_wrbuf_base+1] = data >> 8; break; } } if (m_wrbuf_count == 0) m_mode = FM_WRBUFPART4; else m_wrbuf_count--; break; case FM_WRBUFPART4: if (((offset & BLOCK_ADDRESS_MASK) != (m_wrbuf_base & BLOCK_ADDRESS_MASK)) || (data != 0xd0)) { m_status |= 0x30; } else if (READ_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT) && !m_hard_unlock) { m_status |= 0x12; } else if (!(m_status & 0x30)) { int i; for (i=0; i> BLOCK_ADDRESS_SHIFT) && !m_hard_unlock) { m_status |= 0x12; } else { switch (bus_width) { case bw_8: m_flashmemory[BYTE_XOR_LE(offset)] &= data; break; case bw_16: *(uint16_t*)(m_flashmemory.get()+offset) &= data; break; } } m_mode = FM_READSTATUS; break; case FM_CLEARPART1: if (data == 0xd0) { // clear the 128k block containing the current address // to all 0xffs if (READ_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT) && !m_hard_unlock) { m_status |= 0x22; } else { offset &= BLOCK_ADDRESS_MASK; memset(&m_flashmemory[offset], 0xff, BLOCK_SIZE); } m_mode = FM_READSTATUS; } break; case FM_SETLOCK: switch (data) { case 0xf1: if (!m_hard_unlock) m_status |= 0x12; else m_master_lock = 1; break; case 0x01: if (m_master_lock && !m_hard_unlock) m_status |= 0x12; else SET_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT); break; case 0xd0: if (m_master_lock && !m_hard_unlock) m_status |= 0x22; else CLEAR_BLOCKLOCK(offset >> BLOCK_ADDRESS_SHIFT); break; case 0x03: // Set Read configuration /* ignore command */ break; default: m_status |= 0x30; break; } m_mode = FM_READSTATUS; break; case FM_CONFPART1: /* configuration register is not emulated because the sts pin is not */ //m_configuration = data; m_mode = FM_READSTATUS; /* right??? */ break; case FM_WRPROTPART1: if ((offset < 0x100) || (offset >= 0x112)) m_status |= 0x10; else if ((offset >= 0x102) && !((m_prot_regs[BYTE_XOR_LE(0)] >> ((offset - 0x102) >> 3)) & 1)) m_status |= 0x12; else { switch (bus_width) { case bw_8: m_prot_regs[BYTE_XOR_LE(offset-0x100)] &= data; break; case bw_16: *(uint16_t*)(m_prot_regs+(offset-0x100)) &= data; break; } } m_mode = FM_READSTATUS; /* right??? */ break; } } /* read a byte from FEEPROM */ uint8_t strataflash_device::read8(offs_t offset) { return read8_16(offset, bw_8); } /* Write a byte to FEEPROM */ void strataflash_device::write8(offs_t offset, uint8_t data) { write8_16(offset, data, bw_8); } /* read a 16-bit word from FEEPROM */ uint16_t strataflash_device::read16(offs_t offset) { return read8_16(offset, bw_16); } /* Write a byte to FEEPROM */ void strataflash_device::write16(offs_t offset, uint16_t data) { write8_16(offset, data, bw_16); } /a> 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145