From 7717489f3ed419c5fb1814be5504e07e9c07b83a Mon Sep 17 00:00:00 2001 From: fulivi Date: Wed, 3 Jun 2015 14:22:59 +0200 Subject: hp64k: Preliminary version of HP Hybrid CPU (no interrupts & no DMA yet) --- src/emu/cpu/hphybrid/hphybrid.c | 859 +++++++++++++++++++++++++++++++++++ src/emu/cpu/hphybrid/hphybrid.h | 141 ++++++ src/emu/cpu/hphybrid/hphybrid_dasm.c | 281 ++++++++++++ 3 files changed, 1281 insertions(+) create mode 100644 src/emu/cpu/hphybrid/hphybrid.c create mode 100644 src/emu/cpu/hphybrid/hphybrid.h create mode 100644 src/emu/cpu/hphybrid/hphybrid_dasm.c (limited to 'src/emu/cpu') diff --git a/src/emu/cpu/hphybrid/hphybrid.c b/src/emu/cpu/hphybrid/hphybrid.c new file mode 100644 index 00000000000..bef8da6ddb2 --- /dev/null +++ b/src/emu/cpu/hphybrid/hphybrid.c @@ -0,0 +1,859 @@ +// license:BSD-3-Clause +// copyright-holders:F. Ulivi + +#include "emu.h" +#include "debugger.h" +#include "hphybrid.h" + +enum { + HPHYBRID_A, + HPHYBRID_B, + HPHYBRID_C, + HPHYBRID_D, + HPHYBRID_P, + HPHYBRID_R, + HPHYBRID_IV, + HPHYBRID_PA, + HPHYBRID_DMAPA, + HPHYBRID_DMAMA, + HPHYBRID_DMAC, + HPHYBRID_I +}; + +#define BIT_MASK(n) (1U << (n)) + +// Macros to clear/set single bits +#define BIT_CLR(w , n) ((w) &= ~BIT_MASK(n)) +#define BIT_SET(w , n) ((w) |= BIT_MASK(n)) + +// Bits in m_flags +#define HPHYBRID_C_BIT 0 // Carry/extend +#define HPHYBRID_O_BIT 1 // Overflow +#define HPHYBRID_CB_BIT 2 // Cb +#define HPHYBRID_DB_BIT 3 // Db +#define HPHYBRID_INTEN_BIT 4 // Interrupt enable +#define HPHYBRID_DMAEN_BIT 5 // DMA enable +#define HPHYBRID_DMADIR_BIT 6 // DMA direction (1 = OUT) +#define HPHYBRID_HALT_BIT 7 // Halt flag +#define HPHYBRID_IRH_BIT 8 // IRH requested +#define HPHYBRID_IRL_BIT 9 // IRL requested +#define HPHYBRID_IRH_SVC_BIT 10 // IRH in service +#define HPHYBRID_IRL_SVC_BIT 11 // IRL in service + +#define HPHYBRID_IV_MASK 0xfff0 // IV mask + +#define CURRENT_PA (m_reg_PA[ 0 ]) + +#define HP_RESET_ADDR 0x0020 + +#define MAKE_IOADDR(pa , ic) (((pa) << HP_IOADDR_PA_SHIFT) | ((ic) << HP_IOADDR_IC_SHIFT)) + +const device_type HP_5061_3011 = &device_creator; + +hp_hybrid_cpu_device::hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__), + m_program_config("program", ENDIANNESS_BIG, 16, 16, -1), + m_io_config("io", ENDIANNESS_BIG, 16, 6, -1) +{ +} + +void hp_hybrid_cpu_device::device_start() +{ + m_reg_A = 0; + m_reg_B = 0; + m_reg_P = HP_RESET_ADDR; + m_reg_R = 0; + m_reg_C = 0; + m_reg_D = 0; + m_reg_IV = 0; + m_reg_PA[ 0 ] = 0; + m_reg_PA[ 1 ] = 0; + m_reg_PA[ 2 ] = 0; + m_flags = 0; + m_dmapa = 0; + m_dmama = 0; + m_dmac = 0; + m_reg_I = 0; + + { + state_add(HPHYBRID_A, "A", m_reg_A); + state_add(HPHYBRID_B, "B", m_reg_B); + state_add(HPHYBRID_C, "C", m_reg_C); + state_add(HPHYBRID_D, "D", m_reg_D); + state_add(HPHYBRID_P, "P", m_reg_P); + state_add(STATE_GENPC, "GENPC", m_reg_P).noshow(); + state_add(HPHYBRID_R, "R", m_reg_R); + state_add(STATE_GENSP, "GENSP", m_reg_R).noshow(); + state_add(HPHYBRID_IV, "IV", m_reg_IV); + state_add(HPHYBRID_PA, "PA", m_reg_PA[ 0 ]); + state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%9s"); + state_add(HPHYBRID_DMAPA , "DMAPA" , m_dmapa).noshow(); + state_add(HPHYBRID_DMAMA , "DMAMA" , m_dmama).noshow(); + state_add(HPHYBRID_DMAC , "DMAC" , m_dmac).noshow(); + state_add(HPHYBRID_I , "I" , m_reg_I).noshow(); + } + + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_io = &space(AS_IO); + + save_item(NAME(m_reg_A)); + save_item(NAME(m_reg_B)); + save_item(NAME(m_reg_C)); + save_item(NAME(m_reg_D)); + save_item(NAME(m_reg_P)); + save_item(NAME(m_reg_R)); + save_item(NAME(m_reg_IV)); + save_item(NAME(m_reg_PA[0])); + save_item(NAME(m_reg_PA[1])); + save_item(NAME(m_reg_PA[2])); + save_item(NAME(m_flags)); + save_item(NAME(m_dmapa)); + save_item(NAME(m_dmama)); + save_item(NAME(m_dmac)); + save_item(NAME(m_reg_I)); + + m_icountptr = &m_icount; +} + +void hp_hybrid_cpu_device::device_reset() +{ + m_reg_P = HP_RESET_ADDR; + m_reg_I = RM(m_reg_P); + m_flags = 0; +} + +void hp_hybrid_cpu_device::execute_run() +{ + do { + debugger_instruction_hook(this, m_reg_P); + // TODO: check interrupts + // TODO: check dma + m_reg_I = execute_one(m_reg_I); + } while (m_icount > 0); +} + +void hp_hybrid_cpu_device::execute_set_input(int inputnum, int state) +{ +} + +/** + * Execute 1 instruction + * + * @param opcode Opcode to be executed + * + * @return Next opcode to be executed + */ +UINT16 hp_hybrid_cpu_device::execute_one(UINT16 opcode) +{ + if ((opcode & 0x7fe0) == 0x7000) { + // EXE + m_icount -= 8; + return RM(opcode & 0x1f); + } else { + m_reg_P = execute_one_sub(opcode); + return RM(m_reg_P); + } +} + +/** + * Execute 1 instruction (except EXE) + * + * @param opcode Opcode to be executed (no EXE instructions) + * + * @return new value of P register + */ +UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode) +{ + UINT16 ea; + UINT16 tmp; + + switch (opcode & 0x7800) { + case 0x0000: + // LDA + m_icount -= 13; + m_reg_A = RM(get_ea(opcode)); + break; + + case 0x0800: + // LDB + m_icount -= 13; + m_reg_B = RM(get_ea(opcode)); + break; + + case 0x1000: + // CPA + m_icount -= 16; + if (m_reg_A != RM(get_ea(opcode))) { + // Skip next instruction + return m_reg_P + 2; + } + break; + + case 0x1800: + // CPB + m_icount -= 16; + if (m_reg_B != RM(get_ea(opcode))) { + // Skip next instruction + return m_reg_P + 2; + } + break; + + case 0x2000: + // ADA + m_icount -= 13; + do_add(m_reg_A , RM(get_ea(opcode))); + break; + + case 0x2800: + // ADB + m_icount -= 13; + do_add(m_reg_B , RM(get_ea(opcode))); + break; + + case 0x3000: + // STA + m_icount -= 13; + WM(get_ea(opcode) , m_reg_A); + break; + + case 0x3800: + // STB + m_icount -= 13; + WM(get_ea(opcode) , m_reg_B); + break; + + case 0x4000: + // JSM + m_icount -= 17; + WM(++m_reg_R , m_reg_P); + return get_ea(opcode); + + case 0x4800: + // ISZ + m_icount -= 19; + ea = get_ea(opcode); + tmp = RM(ea) + 1; + WM(ea , tmp); + if (tmp == 0) { + // Skip next instruction + return m_reg_P + 2; + } + break; + + case 0x5000: + // AND + m_icount -= 13; + m_reg_A &= RM(get_ea(opcode)); + break; + + case 0x5800: + // DSZ + m_icount -= 19; + ea = get_ea(opcode); + tmp = RM(ea) - 1; + WM(ea , tmp); + if (tmp == 0) { + // Skip next instruction + return m_reg_P + 2; + } + break; + + case 0x6000: + // IOR + m_icount -= 13; + m_reg_A |= RM(get_ea(opcode)); + break; + + case 0x6800: + // JMP + m_icount -= 8; + return get_ea(opcode); + + default: + switch (opcode & 0xfec0) { + case 0x7400: + // RZA + // SZA + m_icount -= 14; + return get_skip_addr(opcode , m_reg_A == 0); + + case 0x7440: + // RIA + // SIA + m_icount -= 14; + return get_skip_addr(opcode , m_reg_A++ == 0); + + case 0x7480: + // SFS + // SFC + m_icount -= 14; + // TODO: read flag bit + return get_skip_addr(opcode , true); + + case 0x7C00: + // RZB + // SZB + m_icount -= 14; + return get_skip_addr(opcode , m_reg_B == 0); + + case 0x7C40: + // RIB + // SIB + m_icount -= 14; + return get_skip_addr(opcode , m_reg_B++ == 0); + + case 0x7c80: + // SSS + // SSC + m_icount -= 14; + // TODO: read status bit + return get_skip_addr(opcode , true); + + case 0x7cc0: + // SHS + // SHC + m_icount -= 14; + return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_HALT_BIT)); + + default: + switch (opcode & 0xfe00) { + case 0x7600: + // SLA + // RLA + m_icount -= 14; + return get_skip_addr_sc(opcode , m_reg_A , 0); + + case 0x7e00: + // SLB + // RLB + m_icount -= 14; + return get_skip_addr_sc(opcode , m_reg_B , 0); + + case 0xf400: + // SAP + // SAM + m_icount -= 14; + return get_skip_addr_sc(opcode , m_reg_A , 15); + + case 0xf600: + // SOC + // SOS + m_icount -= 14; + return get_skip_addr_sc(opcode , m_flags , HPHYBRID_O_BIT); + + case 0xfc00: + // SBP + // SBM + m_icount -= 14; + return get_skip_addr_sc(opcode , m_reg_B , 15); + + case 0xfe00: + // SEC + // SES + m_icount -= 14; + return get_skip_addr_sc(opcode , m_flags , HPHYBRID_C_BIT); + + default: + switch (opcode & 0xfff0) { + case 0xf100: + // AAR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + // A shift by 16 positions is equivalent to a shift by 15 + tmp = tmp > 15 ? 15 : tmp; + m_reg_A = ((m_reg_A ^ 0x8000) >> tmp) - (0x8000 >> tmp); + break; + + case 0xf900: + // ABR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + tmp = tmp > 15 ? 15 : tmp; + m_reg_B = ((m_reg_B ^ 0x8000) >> tmp) - (0x8000 >> tmp); + break; + + case 0xf140: + // SAR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_A >>= tmp; + break; + + case 0xf940: + // SBR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_B >>= tmp; + break; + + case 0xf180: + // SAL + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_A <<= tmp; + break; + + case 0xf980: + // SBL + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_B <<= tmp; + break; + + case 0xf1c0: + // RAR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_A = (m_reg_A >> tmp) | (m_reg_A << (16 - tmp)); + break; + + case 0xf9c0: + // RBR + tmp = (opcode & 0xf) + 1; + m_icount -= (9 + tmp); + m_reg_B = (m_reg_B >> tmp) | (m_reg_B << (16 - tmp)); + break; + + default: + if ((opcode & 0xf760) == 0x7160) { + // Place/withdraw instructions + m_icount -= 23; + do_pw(opcode); + } else if ((opcode & 0xff80) == 0xf080) { + // RET + m_icount -= 16; + if (BIT(opcode , 6)) { + // Pop PA stack + if (BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) { + BIT_CLR(m_flags , HPHYBRID_IRH_SVC_BIT); + memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); + } else if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { + BIT_CLR(m_flags , HPHYBRID_IRL_SVC_BIT); + memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); + } + } + tmp = RM(m_reg_R--) + (opcode & 0x1f); + return BIT(opcode , 5) ? tmp - 0x20 : tmp; + } else { + switch (opcode) { + case 0x7100: + // SDO + m_icount -= 12; + BIT_SET(m_flags , HPHYBRID_DMADIR_BIT); + break; + + case 0x7108: + // SDI + m_icount -= 12; + BIT_CLR(m_flags , HPHYBRID_DMADIR_BIT); + break; + + case 0x7110: + // EIR + m_icount -= 12; + BIT_SET(m_flags , HPHYBRID_INTEN_BIT); + break; + + case 0x7118: + // DIR + m_icount -= 12; + BIT_CLR(m_flags , HPHYBRID_INTEN_BIT); + break; + + case 0x7120: + // DMA + m_icount -= 12; + BIT_SET(m_flags , HPHYBRID_DMAEN_BIT); + break; + + case 0x7138: + // DDR + m_icount -= 12; + BIT_CLR(m_flags , HPHYBRID_DMAEN_BIT); + break; + + case 0x7140: + // DBL + m_icount -= 12; + BIT_CLR(m_flags , HPHYBRID_DB_BIT); + break; + + case 0x7148: + // CBL + m_icount -= 12; + BIT_CLR(m_flags , HPHYBRID_CB_BIT); + break; + + case 0x7150: + // DBU + m_icount -= 12; + BIT_SET(m_flags , HPHYBRID_DB_BIT); + break; + + case 0x7158: + // CBU + m_icount -= 12; + BIT_SET(m_flags , HPHYBRID_CB_BIT); + break; + + case 0xf020: + // TCA + m_icount -= 9; + m_reg_A = ~m_reg_A; + do_add(m_reg_A , 1); + break; + + case 0xf060: + // CMA + m_icount -= 9; + m_reg_A = ~m_reg_A; + break; + + case 0xf820: + // TCB + m_icount -= 9; + m_reg_B = ~m_reg_B; + do_add(m_reg_B , 1); + break; + + case 0xf860: + // CMB + m_icount -= 9; + m_reg_B = ~m_reg_B; + break; + + default: + // Unrecognized instructions: NOP + // Execution time is fictional + m_icount -= 6; + } + } + } + } + } + } + + return m_reg_P + 1; +} + +void hp_hybrid_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) +{ + if (entry.index() == STATE_GENFLAGS) { + strprintf(str, "%s %s %c %c", + BIT(m_flags , HPHYBRID_DB_BIT) ? "Db":"..", + BIT(m_flags , HPHYBRID_CB_BIT) ? "Cb":"..", + BIT(m_flags , HPHYBRID_O_BIT) ? 'O':'.', + BIT(m_flags , HPHYBRID_C_BIT) ? 'E':'.'); + } +} + +offs_t hp_hybrid_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE(hp_hybrid); + return CPU_DISASSEMBLE_NAME(hp_hybrid)(this, buffer, pc, oprom, opram, options); +} + +UINT16 hp_hybrid_cpu_device::get_ea(UINT16 opcode) +{ + UINT16 base; + UINT16 off; + + if (BIT(opcode , 10)) { + // Current page + base = m_reg_P; + } else { + // Base page + base = 0; + } + + off = opcode & 0x3ff; + if (off & 0x200) { + off -= 0x400; + } + + base += off; + + if (BIT(opcode , 15)) { + // Indirect addressing + m_icount -= 6; + return RM(base); + } else { + // Direct addressing + return base; + } +} + +void hp_hybrid_cpu_device::do_add(UINT16& addend1 , UINT16 addend2) +{ + UINT32 tmp = addend1 + addend2; + + if (BIT(tmp , 16)) { + // Carry + BIT_SET(m_flags , HPHYBRID_C_BIT); + } + + if (BIT((tmp ^ addend1) & (tmp ^ addend2) , 15)) { + // Overflow + BIT_SET(m_flags , HPHYBRID_O_BIT); + } + + addend1 = (UINT16)tmp; +} + +UINT16 hp_hybrid_cpu_device::get_skip_addr(UINT16 opcode , bool condition) const +{ + bool skip_val = BIT(opcode , 8) != 0; + + if (condition == skip_val) { + UINT16 off = opcode & 0x1f; + + if (BIT(opcode , 5)) { + off -= 0x20; + } + return m_reg_P + off; + } else { + return m_reg_P + 1; + } +} + +UINT16 hp_hybrid_cpu_device::get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n) +{ + bool val = BIT(v , n); + + if (BIT(opcode , 7)) { + if (BIT(opcode , 6)) { + BIT_SET(v , n); + } else { + BIT_CLR(v , n); + } + } + + return get_skip_addr(opcode , val); +} + +void hp_hybrid_cpu_device::do_pw(UINT16 opcode) +{ + UINT16 tmp; + UINT16 reg_addr = opcode & 7; + UINT16 *ptr_reg; + UINT16 b_mask; + + if (BIT(opcode , 3)) { + ptr_reg = &m_reg_D; + b_mask = BIT_MASK(HPHYBRID_DB_BIT); + } else { + ptr_reg = &m_reg_C; + b_mask = BIT_MASK(HPHYBRID_CB_BIT); + } + + if (BIT(opcode , 4)) { + // Withdraw + if (BIT(opcode , 11)) { + // Byte + UINT32 tmp_addr = (UINT32)(*ptr_reg); + if (m_flags & b_mask) { + tmp_addr |= 0x10000; + } + tmp = RM((UINT16)(tmp_addr >> 1)); + if (BIT(tmp_addr , 0)) { + tmp &= 0xff; + } else { + tmp >>= 8; + } + } else { + // Word + tmp = RM(*ptr_reg); + } + WM(reg_addr , tmp); + + if (BIT(opcode , 7)) { + // Post-decrement + if ((*ptr_reg)-- == 0) { + m_flags ^= b_mask; + } + } else { + // Post-increment + if (++(*ptr_reg) == 0) { + m_flags ^= b_mask; + } + } + } else { + // Place + if (BIT(opcode , 7)) { + // Pre-decrement + if ((*ptr_reg)-- == 0) { + m_flags ^= b_mask; + } + } else { + // Pre-increment + if (++(*ptr_reg) == 0) { + m_flags ^= b_mask; + } + } + tmp = RM(reg_addr); + if (BIT(opcode , 11)) { + // Byte + UINT32 tmp_addr = (UINT32)(*ptr_reg); + if (m_flags & b_mask) { + tmp_addr |= 0x10000; + } + WMB(tmp_addr , (UINT8)tmp); + } else { + // Word + WM(*ptr_reg , tmp); + } + } +} + +UINT16 hp_hybrid_cpu_device::RM(UINT16 addr) +{ + UINT16 tmp; + + if (addr <= HP_REG_LAST_ADDR) { + // Memory mapped registers + switch (addr) { + case HP_REG_A_ADDR: + return m_reg_A; + + case HP_REG_B_ADDR: + return m_reg_B; + + case HP_REG_P_ADDR: + return m_reg_P; + + case HP_REG_R_ADDR: + return m_reg_R; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + return RIO(CURRENT_PA , addr - HP_REG_R4_ADDR); + + case HP_REG_IV_ADDR: + return m_reg_IV; + + case HP_REG_PA_ADDR: + return CURRENT_PA; + + case HP_REG_DMAPA_ADDR: + tmp = m_dmapa & HP_REG_PA_MASK; + if (BIT(m_flags , HPHYBRID_CB_BIT)) { + BIT_SET(tmp , 15); + } + if (BIT(m_flags , HPHYBRID_DB_BIT)) { + BIT_SET(tmp , 14); + } + return tmp; + + case HP_REG_DMAMA_ADDR: + return m_dmama; + + case HP_REG_DMAC_ADDR: + return m_dmac; + + case HP_REG_C_ADDR: + return m_reg_C; + + case HP_REG_D_ADDR: + return m_reg_D; + + default: + // Unknown registers are returned as 0 + return 0; + } + } else { + return m_direct->read_decrypted_word((offs_t)addr << 1); + } +} + +void hp_hybrid_cpu_device::WM(UINT16 addr , UINT16 v) +{ + if (addr <= HP_REG_LAST_ADDR) { + // Memory mapped registers + switch (addr) { + case HP_REG_A_ADDR: + m_reg_A = v; + break; + + case HP_REG_B_ADDR: + m_reg_B = v; + break; + + case HP_REG_P_ADDR: + m_reg_P = v; + break; + + case HP_REG_R_ADDR: + m_reg_R = v; + break; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + WIO(CURRENT_PA , addr - HP_REG_R4_ADDR , v); + break; + + case HP_REG_IV_ADDR: + m_reg_IV = v & HP_REG_IV_MASK; + break; + + case HP_REG_PA_ADDR: + CURRENT_PA = v & HP_REG_PA_MASK; + break; + + case HP_REG_DMAPA_ADDR: + m_dmapa = v & HP_REG_PA_MASK; + break; + + case HP_REG_DMAMA_ADDR: + m_dmama = v; + break; + + case HP_REG_DMAC_ADDR: + m_dmac = v; + break; + + case HP_REG_C_ADDR: + m_reg_C = v; + break; + + case HP_REG_D_ADDR: + m_reg_D = v; + break; + + default: + // Unknown registers are silently discarded + break; + } + } else { + m_program->write_word((offs_t)addr << 1 , v); + } +} + +void hp_hybrid_cpu_device::WMB(UINT32 addr , UINT8 v) +{ + if (addr <= (HP_REG_LAST_ADDR * 2 + 1)) { + // Cannot write bytes to registers + } else { + m_program->write_byte(addr , v); + } +} + +UINT16 hp_hybrid_cpu_device::RIO(UINT8 pa , UINT8 ic) +{ + return m_io->read_word(MAKE_IOADDR(pa, ic) << 1); +} + +void hp_hybrid_cpu_device::WIO(UINT8 pa , UINT8 ic , UINT16 v) +{ + m_io->write_word(MAKE_IOADDR(pa, ic) << 1 , v); +} + +hp_5061_3011_cpu_device::hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : hp_hybrid_cpu_device(mconfig, HP_5061_3011, "HP_5061_3011", tag, owner, clock, "5061-3011") +{ +} + diff --git a/src/emu/cpu/hphybrid/hphybrid.h b/src/emu/cpu/hphybrid/hphybrid.h new file mode 100644 index 00000000000..a9153580bee --- /dev/null +++ b/src/emu/cpu/hphybrid/hphybrid.h @@ -0,0 +1,141 @@ +// license:BSD-3-Clause +// copyright-holders:F. Ulivi +// +// ***************************************** +// Emulator for HP "hybrid" processor series +// ***************************************** +// +// The HP hybrid processor series is composed of a few different models with different +// capabilities. The series was derived from HP's own 2116 processor by translating a +// discrete implementation of the 1960s into a multi-chip module (hence the "hybrid" name). +// This emulator currently supports the 5061-3011 version only. +// +// There is very little information around on this processor. +// For this emulator I mainly relied on these sources: +// - http://www.hp9845.net/ website +// - HP manual "Assembly development ROM manual for the HP9845": this is the most precious +// and "enabling" resource of all +// - US Patent 4,180,854 describing the HP9845 system +// - Some manual for the 2116 processor +// - Study of disassembly of firmware of HP64000 system +// - A lot of "educated" guessing + +#ifndef _HPHYBRID_H_ +#define _HPHYBRID_H_ + +// Input lines +#define HPHYBRID_IRH 0 // High-level interrupt +#define HPHYBRID_IRL 1 // Low-level interrupt +#define HPHYBRID_INT_LVLS 2 // Levels of interrupt + +#define HPHYBRID_DMAR 2 // DMA request +#define HPHYBRID_HALT 3 // "Halt" input +#define HPHYBRID_STS 4 // "Status" input +#define HPHYBRID_FLG 5 // "Flag" input + +// I/O addressing space (16-bit wide) +// Addresses into this space are composed as follows: +// b[5..2] = Peripheral address 0..15 +// b[1..0] = Register address (IC) 0..3 +#define HP_IOADDR_PA_SHIFT 2 +#define HP_IOADDR_IC_SHIFT 0 + +// Addresses of memory mapped registers +#define HP_REG_A_ADDR 0x0000 +#define HP_REG_B_ADDR 0x0001 +#define HP_REG_P_ADDR 0x0002 +#define HP_REG_R_ADDR 0x0003 +#define HP_REG_R4_ADDR 0x0004 +#define HP_REG_R5_ADDR 0x0005 +#define HP_REG_R6_ADDR 0x0006 +#define HP_REG_R7_ADDR 0x0007 +#define HP_REG_IV_ADDR 0x0008 +#define HP_REG_PA_ADDR 0x0009 +#define HP_REG_DMAPA_ADDR 0x000B +#define HP_REG_DMAMA_ADDR 0x000C +#define HP_REG_DMAC_ADDR 0x000D +#define HP_REG_C_ADDR 0x000e +#define HP_REG_D_ADDR 0x000f +#define HP_REG_LAST_ADDR 0x001f + +#define HP_REG_IV_MASK 0xfff0 +#define HP_REG_PA_MASK 0x000f + +class hp_hybrid_cpu_device : public cpu_device +{ +public: +protected: + hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname); + + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 6; } + virtual UINT32 execute_max_cycles() const { return 25; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual UINT32 execute_default_irq_vector() const { return 0xffff; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + UINT16 execute_one(UINT16 opcode); + UINT16 execute_one_sub(UINT16 opcode); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, std::string &str); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + private: + address_space_config m_program_config; + address_space_config m_io_config; + + address_space *m_program; + direct_read_data *m_direct; + address_space *m_io; + int m_icount; + + // State of processor + UINT16 m_reg_A; // Register A + UINT16 m_reg_B; // Register B + UINT16 m_reg_P; // Register P + UINT16 m_reg_R; // Register R + UINT16 m_reg_C; // Register C + UINT16 m_reg_D; // Register D + UINT16 m_reg_IV; // Register IV + UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long) + UINT16 m_flags; // Flags (carry, overflow, cb, db, int en, dma en, dma dir) + UINT8 m_dmapa; // DMA peripheral address (4 bits) + UINT16 m_dmama; // DMA address + UINT16 m_dmac; // DMA counter + UINT16 m_reg_I; // Instruction register + + UINT16 get_ea(UINT16 opcode); + void do_add(UINT16& addend1 , UINT16 addend2); + UINT16 get_skip_addr(UINT16 opcode , bool condition) const; + UINT16 get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n); + void do_pw(UINT16 opcode); + + UINT16 RM(UINT16 addr); + void WM(UINT16 addr , UINT16 v); + void WMB(UINT32 addr , UINT8 v); + UINT16 RIO(UINT8 pa , UINT8 ic); + void WIO(UINT8 pa , UINT8 ic , UINT16 v); +}; + +class hp_5061_3011_cpu_device : public hp_hybrid_cpu_device +{ +public: + hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +extern const device_type HP_5061_3011; + +#endif /* _HPHYBRID_H_ */ diff --git a/src/emu/cpu/hphybrid/hphybrid_dasm.c b/src/emu/cpu/hphybrid/hphybrid_dasm.c new file mode 100644 index 00000000000..15897498292 --- /dev/null +++ b/src/emu/cpu/hphybrid/hphybrid_dasm.c @@ -0,0 +1,281 @@ +// license:BSD-3-Clause +// copyright-holders:F. Ulivi +// ******************************************************************************** +// * HP "hybrid" processor disassembler +// ******************************************************************************** + +#include "emu.h" +#include "debugger.h" +#include "hphybrid.h" + +typedef void (*fn_dis_param)(char *buffer , offs_t pc , UINT16 opcode); + +typedef struct { + UINT16 m_op_mask; + UINT16 m_opcode; + const char *m_mnemonic; + fn_dis_param m_param_fn; + UINT32 m_dasm_flags; +} dis_entry_t; + +static void addr_2_str(char *buffer , UINT16 addr , bool indirect) +{ + char *s = buffer + strlen(buffer); + + s += sprintf(s , "$%04x" , addr); + + switch (addr) { + case HP_REG_A_ADDR: + strcpy(s , "(A)"); + break; + + case HP_REG_B_ADDR: + strcpy(s , "(B)"); + break; + + case HP_REG_P_ADDR: + strcpy(s , "(P)"); + break; + + case HP_REG_R_ADDR: + strcpy(s , "(R)"); + break; + + case HP_REG_R4_ADDR: + strcpy(s , "(R4)"); + break; + + case HP_REG_R5_ADDR: + strcpy(s , "(R5)"); + break; + + case HP_REG_R6_ADDR: + strcpy(s , "(R6)"); + break; + + case HP_REG_R7_ADDR: + strcpy(s , "(R7)"); + break; + + case HP_REG_IV_ADDR: + strcpy(s , "(IV)"); + break; + + case HP_REG_PA_ADDR: + strcpy(s , "(PA)"); + break; + + case HP_REG_DMAPA_ADDR: + strcpy(s , "(DMAPA)"); + break; + + case HP_REG_DMAMA_ADDR: + strcpy(s , "(DMAMA)"); + break; + + case HP_REG_DMAC_ADDR: + strcpy(s , "(DMAC)"); + break; + + case HP_REG_C_ADDR: + strcpy(s , "(C)"); + break; + + case HP_REG_D_ADDR: + strcpy(s , "(D)"); + break; + } + + if (indirect) { + strcat(s , ",I"); + } +} + +static void param_none(char *buffer , offs_t pc , UINT16 opcode) +{ +} + +static void param_loc(char *buffer , offs_t pc , UINT16 opcode) +{ + UINT16 base; + UINT16 off; + + if (opcode & 0x0400) { + // Current page + base = pc; + } else { + // Base page + base = 0; + } + + off = opcode & 0x3ff; + if (off & 0x200) { + off -= 0x400; + } + + addr_2_str(buffer , base + off , (opcode & 0x8000) != 0); +} + +static void param_addr32(char *buffer , offs_t pc , UINT16 opcode) +{ + addr_2_str(buffer , opcode & 0x1f , (opcode & 0x8000) != 0); +} + +static void param_skip(char *buffer , offs_t pc , UINT16 opcode) +{ + UINT16 off = opcode & 0x3f; + if (off & 0x20) { + off -= 0x40; + } + addr_2_str(buffer , pc + off , false); +} + +static void param_skip_sc(char *buffer , offs_t pc , UINT16 opcode) +{ + param_skip(buffer, pc, opcode); + + if (opcode & 0x80) { + if (opcode & 0x40) { + strcat(buffer , ",S"); + } else { + strcat(buffer , ",C"); + } + } +} + +static void param_ret(char *buffer , offs_t pc , UINT16 opcode) +{ + char *s = buffer + strlen(buffer); + + int off = opcode & 0x3f; + + if (off & 0x20) { + off -= 0x40; + } + + s += sprintf(s , "%d" , off); + if (opcode & 0x40) { + strcpy(s , ",P"); + } +} + +static void param_n16(char *buffer , offs_t pc , UINT16 opcode) +{ + char *s = buffer + strlen(buffer); + + sprintf(s , "%u" , (opcode & 0xf) + 1); +} + +static void param_reg_id(char *buffer , offs_t pc , UINT16 opcode) +{ + addr_2_str(buffer, opcode & 7, false); + + if (opcode & 0x80) { + strcat(buffer , ",D"); + } else { + strcat(buffer , ",I"); + } +} + +static const dis_entry_t dis_table[] = { + // *** BPC Instructions *** + {0xffff , 0x0000 , "NOP" , param_none , 0 }, + {0x7800 , 0x0000 , "LDA" , param_loc , 0 }, + {0x7800 , 0x0800 , "LDB" , param_loc , 0 }, + {0x7800 , 0x1000 , "CPA" , param_loc , 0 }, + {0x7800 , 0x1800 , "CPB" , param_loc , 0 }, + {0x7800 , 0x2000 , "ADA" , param_loc , 0 }, + {0x7800 , 0x2800 , "ADB" , param_loc , 0 }, + {0x7800 , 0x3000 , "STA" , param_loc , 0 }, + {0x7800 , 0x3800 , "STB" , param_loc , 0 }, + {0x7800 , 0x4000 , "JSM" , param_loc , DASMFLAG_STEP_OVER }, + {0x7800 , 0x4800 , "ISZ" , param_loc , 0 }, + {0x7800 , 0x5000 , "AND" , param_loc , 0 }, + {0x7800 , 0x5800 , "DSZ" , param_loc , 0 }, + {0x7800 , 0x6000 , "IOR" , param_loc , 0 }, + {0x7800 , 0x6800 , "JMP" , param_loc , 0 }, + {0x7fe0 , 0x7000 , "EXE" , param_addr32 , 0 }, + {0xffc0 , 0x7400 , "RZA" , param_skip , 0 }, + {0xffc0 , 0x7C00 , "RZB" , param_skip , 0 }, + {0xffc0 , 0x7440 , "RIA" , param_skip , 0 }, + {0xffc0 , 0x7C40 , "RIB" , param_skip , 0 }, + {0xffc0 , 0x7500 , "SZA" , param_skip , 0 }, + {0xffc0 , 0x7D00 , "SZB" , param_skip , 0 }, + {0xffc0 , 0x7540 , "SIA" , param_skip , 0 }, + {0xffc0 , 0x7D40 , "SIB" , param_skip , 0 }, + {0xffc0 , 0x7480 , "SFS" , param_skip , 0 }, + {0xffc0 , 0x7580 , "SFC" , param_skip , 0 }, + {0xffc0 , 0x7c80 , "SSS" , param_skip , 0 }, + {0xffc0 , 0x7d80 , "SSC" , param_skip , 0 }, + {0xffc0 , 0x7cc0 , "SHS" , param_skip , 0 }, + {0xffc0 , 0x7dc0 , "SHC" , param_skip , 0 }, + {0xff00 , 0x7600 , "SLA" , param_skip_sc , 0 }, + {0xff00 , 0x7e00 , "SLB" , param_skip_sc , 0 }, + {0xff00 , 0x7700 , "RLA" , param_skip_sc , 0 }, + {0xff00 , 0x7f00 , "RLB" , param_skip_sc , 0 }, + {0xff00 , 0xf400 , "SAP" , param_skip_sc , 0 }, + {0xff00 , 0xfc00 , "SBP" , param_skip_sc , 0 }, + {0xff00 , 0xf500 , "SAM" , param_skip_sc , 0 }, + {0xff00 , 0xfd00 , "SBM" , param_skip_sc , 0 }, + {0xff00 , 0xf600 , "SOC" , param_skip_sc , 0 }, + {0xff00 , 0xf700 , "SOS" , param_skip_sc , 0 }, + {0xff00 , 0xfe00 , "SEC" , param_skip_sc , 0 }, + {0xff00 , 0xff00 , "SES" , param_skip_sc , 0 }, + {0xffff , 0xf020 , "TCA" , param_none , 0 }, + {0xffff , 0xf820 , "TCB" , param_none , 0 }, + {0xffff , 0xf060 , "CMA" , param_none , 0 }, + {0xffff , 0xf860 , "CMB" , param_none , 0 }, + {0xff80 , 0xf080 , "RET" , param_ret , DASMFLAG_STEP_OUT }, + {0xfff0 , 0xf100 , "AAR" , param_n16 , 0 }, + {0xfff0 , 0xf900 , "ABR" , param_n16 , 0 }, + {0xffff , 0xf14f , "CLA" , param_none , 0 }, + {0xfff0 , 0xf140 , "SAR" , param_n16 , 0 }, + {0xffff , 0xf94f , "CLB" , param_none , 0 }, + {0xfff0 , 0xf940 , "SBR" , param_n16 , 0 }, + {0xfff0 , 0xf180 , "SAL" , param_n16 , 0 }, + {0xfff0 , 0xf980 , "SBL" , param_n16 , 0 }, + {0xfff0 , 0xf1c0 , "RAR" , param_n16 , 0 }, + {0xfff0 , 0xf9c0 , "RBR" , param_n16 , 0 }, + // *** IOC Instructions *** + {0xffff , 0x7100 , "SDO" , param_none , 0 }, + {0xffff , 0x7108 , "SDI" , param_none , 0 }, + {0xffff , 0x7110 , "EIR" , param_none , 0 }, + {0xffff , 0x7118 , "DIR" , param_none , 0 }, + {0xffff , 0x7120 , "DMA" , param_none , 0 }, + {0xffff , 0x7128 , "PCM" , param_none , 0 }, + {0xffff , 0x7138 , "DDR" , param_none , 0 }, + {0xffff , 0x7140 , "DBL" , param_none , 0 }, + {0xffff , 0x7148 , "CBL" , param_none , 0 }, + {0xffff , 0x7150 , "DBU" , param_none , 0 }, + {0xffff , 0x7158 , "CBU" , param_none , 0 }, + {0xff78 , 0x7160 , "PWC" , param_reg_id , 0 }, + {0xff78 , 0x7168 , "PWD" , param_reg_id , 0 }, + {0xff78 , 0x7960 , "PBC" , param_reg_id , 0 }, + {0xff78 , 0x7968 , "PBD" , param_reg_id , 0 }, + {0xff78 , 0x7170 , "WWC" , param_reg_id , 0 }, + {0xff78 , 0x7178 , "WWD" , param_reg_id , 0 }, + {0xff78 , 0x7970 , "WBC" , param_reg_id , 0 }, + {0xff78 , 0x7978 , "WBD" , param_reg_id , 0 }, + // *** END *** + {0 , 0 , NULL , NULL , 0 } +}; + +CPU_DISASSEMBLE(hp_hybrid) +{ + UINT16 opcode = ((UINT16)oprom[ 0 ] << 8) | oprom[ 1 ]; + const dis_entry_t *p; + + for (p = dis_table; p->m_op_mask; p++) { + if ((opcode & p->m_op_mask) == p->m_opcode) { + strcpy(buffer , p->m_mnemonic); + strcat(buffer , " "); + p->m_param_fn(buffer , pc , opcode); + return 1 | p->m_dasm_flags | DASMFLAG_SUPPORTED; + } + } + + // Unknown opcode + strcpy(buffer , "???"); + + return 1 | DASMFLAG_SUPPORTED; +} -- cgit v1.2.3-70-g09d2