From 64e16ca8cf6f8f3f63a9a7604153a8c4725a7cf4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 27 May 2015 09:03:32 +0200 Subject: Cleanups and version bump --- src/emu/cpu/avr8/avr8.c | 4 +- src/emu/cpu/e0c6200/e0c6200.c | 20 ++++---- src/emu/cpu/e0c6200/e0c6200.h | 4 +- src/emu/cpu/e0c6200/e0c6200d.c | 18 +++---- src/emu/cpu/e0c6200/e0c6200op.inc | 4 +- src/emu/cpu/e0c6200/e0c6s46.c | 102 +++++++++++++++++++------------------- src/emu/cpu/e0c6200/e0c6s46.h | 6 +-- src/emu/cpu/melps4/m58846.c | 4 +- src/emu/cpu/melps4/melps4.c | 10 ++-- src/emu/cpu/melps4/melps4.h | 8 +-- src/emu/cpu/melps4/melps4d.c | 6 +-- src/emu/cpu/melps4/melps4op.inc | 4 +- src/emu/cpu/mips/mips3drc.c | 2 +- src/emu/cpu/tlcs90/tlcs90.c | 4 +- src/emu/cpu/tms34010/tms34010.c | 2 +- 15 files changed, 97 insertions(+), 101 deletions(-) (limited to 'src/emu/cpu') diff --git a/src/emu/cpu/avr8/avr8.c b/src/emu/cpu/avr8/avr8.c index a0aacacc3d5..976b2ff8856 100644 --- a/src/emu/cpu/avr8/avr8.c +++ b/src/emu/cpu/avr8/avr8.c @@ -1906,9 +1906,9 @@ void avr8_device::timer5_tick() case WGM5_FAST_PWM_ICR: case WGM5_FAST_PWM_OCR: #if LOG_TIMER_5 - printf("Unimplemented timer#5 waveform generation mode: AVR8_WGM5 = 0x%02X\n", AVR8_WGM5); + printf("Unimplemented timer#5 waveform generation mode: AVR8_WGM5 = 0x%02X\n", AVR8_WGM5); #endif - break; + break; case WGM5_CTC_OCR: //TODO: verify this! Can be very wrong!!! diff --git a/src/emu/cpu/e0c6200/e0c6200.c b/src/emu/cpu/e0c6200/e0c6200.c index d9b1ab65864..e0b6a2eb8d2 100644 --- a/src/emu/cpu/e0c6200/e0c6200.c +++ b/src/emu/cpu/e0c6200/e0c6200.c @@ -78,7 +78,7 @@ void e0c6200_cpu_device::device_start() m_prev_pc = 0; m_npc = 0; m_jpc = 0; - + m_a = 0; m_b = 0; m_xp = m_xh = m_xl = 0; @@ -158,7 +158,7 @@ void e0c6200_cpu_device::do_interrupt() m_halt = m_sleep = false; push_pc(); m_f &= ~I_FLAG; - + // page 1 of the current bank m_pc = (m_pc & 0x1000) | 0x100 | m_irq_vector; @@ -180,27 +180,27 @@ void e0c6200_cpu_device::execute_run() break; } } - + // core cpu not running (peripherals still work) if (m_halt || m_sleep) { m_icount = 0; break; } - + // remember previous state, prepare pset-longjump m_prev_op = m_op; m_prev_pc = m_pc; m_jpc = ((m_prev_op & 0xfe0) == 0xe40) ? m_npc : (m_prev_pc & 0x1f00); - + // fetch next opcode debugger_instruction_hook(this, m_pc); m_op = m_program->read_word(m_pc << 1) & 0xfff; m_pc = (m_pc & 0x1000) | ((m_pc + 1) & 0x0fff); - + // minimal opcode time is 5 clock cycles, opcodes take 5, 7, or 12 clock cycles m_icount -= 5; - + // handle opcode execute_one(); } @@ -226,7 +226,7 @@ void e0c6200_cpu_device::execute_one() // i = 4-bit immediate param // e = 8-bit immediate param // s = 8-bit immediate branch destination - + switch (m_op & 0xf00) { // JP s: jump unconditional @@ -296,7 +296,6 @@ void e0c6200_cpu_device::execute_one() default: switch (m_op) { - // LD r,q: load register with register case 0xec0: /* m_a = m_a; */ break; case 0xec1: m_a = m_b; break; @@ -698,7 +697,6 @@ void e0c6200_cpu_device::execute_one() default: switch (m_op & 0xff0) { - // LD r,i: load register with 4-bit immediate data case 0xe00: m_a = m_op & 0xf; break; case 0xe10: m_b = m_op & 0xf; break; @@ -726,7 +724,7 @@ void e0c6200_cpu_device::execute_one() break; // LD Mn,A: load memory with A - case 0xf80: + case 0xf80: write_mn(m_a); break; diff --git a/src/emu/cpu/e0c6200/e0c6200.h b/src/emu/cpu/e0c6200/e0c6200.h index 27ffa1da817..430cc36f6f8 100644 --- a/src/emu/cpu/e0c6200/e0c6200.h +++ b/src/emu/cpu/e0c6200/e0c6200.h @@ -63,7 +63,7 @@ protected: UINT16 m_prev_pc; UINT16 m_npc; // new bank/page prepared by pset UINT16 m_jpc; // actual bank/page destination for jumps - + // all work registers are 4-bit UINT8 m_a; // accumulator UINT8 m_b; // generic @@ -92,7 +92,7 @@ protected: inline void inc_x(); inline void inc_y(); void do_branch(int condition = 1); - + // opcode handlers UINT8 op_inc(UINT8 x); UINT8 op_dec(UINT8 x); diff --git a/src/emu/cpu/e0c6200/e0c6200d.c b/src/emu/cpu/e0c6200/e0c6200d.c index b1f65071545..4fc0599ac24 100644 --- a/src/emu/cpu/e0c6200/e0c6200d.c +++ b/src/emu/cpu/e0c6200/e0c6200d.c @@ -82,30 +82,30 @@ static char* decode_param(UINT16 opcode, int param, char* buffer) int bits = ep_bits[param] & 0xf; int shift = ep_bits[param] >> 4 & 0xf; UINT16 opmask = opcode >> shift & ((1 << bits) - 1); - + // redirect r/q to A/B/MX/MY if (ep_bits[param] & 0x100) param = ep_redirect_r[opmask]; - + // literal param if (ep_bits[param] == 0) { strcpy(buffer, ep_name[param]); return buffer; } - + // print value like how it's documented in the manual char val[10]; if (bits > 4 || opmask > 9) sprintf(val, "%02XH", opmask); else sprintf(val, "%d", opmask); - + if (param == ep_MN) sprintf(buffer, "M%s", val); else strcpy(buffer, val); - + return buffer; } @@ -113,7 +113,7 @@ static char* decode_param(UINT16 opcode, int param, char* buffer) CPU_DISASSEMBLE(e0c6200) { UINT16 op = (oprom[1] | oprom[0] << 8) & 0xfff; - + int m = -1; int p1 = -1; int p2 = -1; @@ -180,7 +180,6 @@ CPU_DISASSEMBLE(e0c6200) default: switch (op) { - // RLC r case 0xaf0: case 0xaf5: case 0xafa: case 0xaff: m = em_RLC; p1 = ep_R0; @@ -475,7 +474,6 @@ CPU_DISASSEMBLE(e0c6200) default: switch (op & 0xff0) { - // ADC XH,i case 0xa00: m = em_ADC; p1 = ep_XH; p2 = ep_I; @@ -694,7 +692,7 @@ CPU_DISASSEMBLE(e0c6200) // fetch mnemonic char *dst = buffer; dst += sprintf(dst, "%-6s", em_name[m]); - + // fetch param(s) char pbuffer[10]; if (p1 != -1) @@ -705,6 +703,6 @@ CPU_DISASSEMBLE(e0c6200) dst += sprintf(dst, ",%s", decode_param(op, p2, pbuffer)); } } - + return 1 | em_flags[m] | DASMFLAG_SUPPORTED; } diff --git a/src/emu/cpu/e0c6200/e0c6200op.inc b/src/emu/cpu/e0c6200/e0c6200op.inc index 6eef5a7975e..09fc07b3c70 100644 --- a/src/emu/cpu/e0c6200/e0c6200op.inc +++ b/src/emu/cpu/e0c6200/e0c6200op.inc @@ -151,14 +151,14 @@ UINT8 e0c6200_cpu_device::op_add(UINT8 x, UINT8 y, int decimal) m_icount -= 2; x += y; set_cf(x); - + // decimal correction if (m_f & decimal && x >= 10) { x -= 10; m_f |= C_FLAG; } - + set_zf(x); return x & 0xf; } diff --git a/src/emu/cpu/e0c6200/e0c6s46.c b/src/emu/cpu/e0c6200/e0c6s46.c index 55a0127db7b..be131a1e5dc 100644 --- a/src/emu/cpu/e0c6200/e0c6s46.c +++ b/src/emu/cpu/e0c6200/e0c6s46.c @@ -4,7 +4,7 @@ Seiko Epson E0C6S46 MCU QFP5-128pin, see manual for pinout - + TODO: - OSC3 - K input interrupts @@ -64,7 +64,7 @@ e0c6s46_device::e0c6s46_device(const machine_config &mconfig, const char *tag, d void e0c6s46_device::device_start() { e0c6200_cpu_device::device_start(); - + // find ports m_write_r0.resolve_safe(); m_write_r1.resolve_safe(); @@ -88,7 +88,7 @@ void e0c6s46_device::device_start() m_prgtimer_handle->adjust(attotime::never); m_buzzer_handle = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(e0c6s46_device::buzzer_cb), this)); m_buzzer_handle->adjust(attotime::never); - + // zerofill memset(m_port_r, 0x0, sizeof(m_port_r)); m_r_dir = 0; @@ -97,7 +97,7 @@ void e0c6s46_device::device_start() m_p_pullup = 0; memset(m_port_k, 0xf, sizeof(m_port_k)); m_dfk0 = 0xf; - + memset(m_irqflag, 0, sizeof(m_irqflag)); memset(m_irqmask, 0, sizeof(m_irqmask)); m_osc = 0; @@ -114,7 +114,7 @@ void e0c6s46_device::device_start() m_swl_slice = 0; m_swl_count = 0; m_swh_count = 0; - + m_prgtimer_select = 0; m_prgtimer_on = 0; m_prgtimer_src_pulse = 0; @@ -130,7 +130,7 @@ void e0c6s46_device::device_start() m_bz_1shot_running = false; m_bz_1shot_count = 0; m_bz_pulse = 0; - + // register for savestates save_item(NAME(m_port_r)); save_item(NAME(m_r_dir)); @@ -139,7 +139,7 @@ void e0c6s46_device::device_start() save_item(NAME(m_p_pullup)); save_item(NAME(m_port_k)); save_item(NAME(m_dfk0)); - + save_item(NAME(m_irqflag)); save_item(NAME(m_irqmask)); save_item(NAME(m_osc)); @@ -187,7 +187,7 @@ void e0c6s46_device::device_reset() // reset interrupts memset(m_irqflag, 0, sizeof(m_irqflag)); memset(m_irqmask, 0, sizeof(m_irqmask)); - + // reset other i/o m_data->write_byte(0xf41, 0xf); m_data->write_byte(0xf54, 0xf); @@ -205,7 +205,7 @@ void e0c6s46_device::device_reset() m_data->write_byte(0xf7b, 0x0); m_data->write_byte(0xf7d, 0x0); m_data->write_byte(0xf7e, 0x0); - + // reset ports for (int i = 0; i < 5; i++) write_r(i, m_port_r[i]); @@ -224,7 +224,7 @@ void e0c6s46_device::execute_one() // E0C6S46 has no support for SLP opcode if (m_op == 0xff9) return; - + e0c6200_cpu_device::execute_one(); } @@ -255,7 +255,7 @@ bool e0c6s46_device::check_interrupt() m_irq_vector = 2*pri + 2; int reg = priorder[pri]; m_irq_id = reg; - + switch (reg) { // other: mask vs flag @@ -265,7 +265,7 @@ bool e0c6s46_device::check_interrupt() break; } } - + return false; } @@ -278,7 +278,7 @@ void e0c6s46_device::execute_set_input(int line, int state) state = (state) ? 1 : 0; int port = line >> 2 & 1; UINT8 bit = 1 << (line & 3); - + m_port_k[port] = (m_port_k[port] & ~bit) | (state ? bit : 0); } @@ -299,14 +299,14 @@ void e0c6s46_device::write_r(UINT8 port, UINT8 data) UINT8 out = data; if (port < 4 && !(m_r_dir >> port & 1)) out = 0xf; - + switch (port) { case 0: m_write_r0(port, out, 0xff); break; case 1: m_write_r1(port, out, 0xff); break; case 2: m_write_r2(port, out, 0xff); break; case 3: m_write_r3(port, out, 0xff); break; // TODO: R33 PTCLK/_SRDY - + // R4x: special output case 4: // d3: buzzer on: direct output or 1-shot output @@ -336,7 +336,7 @@ void e0c6s46_device::write_p(UINT8 port, UINT8 data) { data &= 0xf; m_port_p[port] = data; - + // don't output if port direction is set to input if (!(m_p_dir >> port & 1)) return; @@ -355,7 +355,7 @@ UINT8 e0c6s46_device::read_p(UINT8 port) // return written value if port direction is set to output if (m_p_dir >> port & 1) return m_port_p[port]; - + switch (port) { case 0: return m_read_p0(port, 0xff); @@ -363,7 +363,7 @@ UINT8 e0c6s46_device::read_p(UINT8 port) case 2: return m_read_p2(port, 0xff); case 3: return m_read_p3(port, 0xff); } - + return 0; } @@ -412,7 +412,7 @@ void e0c6s46_device::clock_watchdog() void e0c6s46_device::clock_clktimer() { m_clktimer_count++; - + // irq on falling edge of 32, 8, 2, 1hz UINT8 flag = 0; if ((m_clktimer_count & 0x07) == 0) @@ -427,7 +427,7 @@ void e0c6s46_device::clock_clktimer() m_irqflag[IRQREG_CLKTIMER] |= flag; if (m_irqflag[IRQREG_CLKTIMER] & m_irqmask[IRQREG_CLKTIMER]) m_possible_irq = true; - + // 1hz falling edge also clocks the watchdog timer if (m_clktimer_count == 0) clock_watchdog(); @@ -439,14 +439,14 @@ void e0c6s46_device::clock_clktimer() void e0c6s46_device::clock_stopwatch() { m_swl_slice++; - + // 1 slice is 3 ticks(256hz) on even and 2 ticks on uneven counts, // but from count 1 to 2 it's 3 ticks, 6 out of 100 times, to make // exactly 26/256hz * 6 + 25/256hz * 4 = 1 second int swl_next = 3 - (m_swl_count & 1); if (m_swl_count == 1 && !(m_swh_count >> 1 & 1)) swl_next = 3; - + if (m_swl_slice == swl_next) { m_swl_slice = 0; @@ -477,7 +477,7 @@ void e0c6s46_device::clock_prgtimer() m_irqflag[IRQREG_PRGTIMER] |= 1; if (m_irqflag[IRQREG_PRGTIMER] & m_irqmask[IRQREG_PRGTIMER]) m_possible_irq = true; - + // note: a reload of 0 indicates a 256-counter m_prgtimer_count = m_prgtimer_reload; } @@ -489,7 +489,7 @@ bool e0c6s46_device::prgtimer_reset_prescaler() UINT8 sel = m_prgtimer_select & 7; if (sel >= 2) m_prgtimer_handle->adjust(attotime::from_ticks(2 << (sel ^ 7), unscaled_clock())); - + return (sel >= 2); } @@ -501,7 +501,7 @@ TIMER_CALLBACK_MEMBER(e0c6s46_device::prgtimer_cb) m_prgtimer_src_pulse ^= 1; m_prgtimer_cur_pulse = m_prgtimer_src_pulse | (m_prgtimer_on ^ 1); - + // clock prgtimer on falling edge of pulse+on if (m_prgtimer_cur_pulse == 0) clock_prgtimer(); @@ -515,17 +515,17 @@ void e0c6s46_device::schedule_buzzer() // only schedule next buzzer timeout if it's on if (m_bz_43_on != 0 && !m_bz_1shot_running) return; - + // pulse width differs per frequency selection int mul = (m_bz_freq & 4) ? 1 : 2; int high = (m_bz_freq & 2) ? 12 : 8; int low = 16 + (m_bz_freq << 2 & 0xc); - + // pulse width envelope if it's on if (m_bz_envelope & 1) high -= m_bz_duty_ratio; low -= high; - + m_buzzer_handle->adjust(attotime::from_ticks(m_bz_pulse ? high : low, mul * unscaled_clock())); } @@ -548,14 +548,14 @@ void e0c6s46_device::reset_buzzer() void e0c6s46_device::clock_bz_1shot() { m_bz_1shot_running = true; - + // reload counter the 1st time if (m_bz_1shot_count == 0) { reset_buzzer(); m_bz_1shot_count = (m_bz_freq & 8) ? 16 : 8; } - + // stop ringing when counter reaches 0 else if (--m_bz_1shot_count == 0) { @@ -586,7 +586,7 @@ UINT32 e0c6s46_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap pixel = 1; else lcd_on = true; - + // draw pixels for (int offset = 0; offset < 0x50; offset++) { @@ -594,11 +594,11 @@ UINT32 e0c6s46_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap { if (lcd_on) pixel = vram[offset] >> c & 1; - + // 16 COM(common) pins, 40 SEG(segment) pins int seg = offset / 2; int com = bank * 8 + (offset & 1) * 4 + c; - + if (m_pixel_update_handler != NULL) m_pixel_update_handler(*this, bitmap, cliprect, m_lcd_contrast, seg, com, pixel); else if (cliprect.contains(seg, com)) @@ -631,7 +631,7 @@ READ8_MEMBER(e0c6s46_device::io_r) } case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: return m_irqmask[offset-0x10]; - + // K input ports case 0x40: case 0x42: return m_port_k[offset >> 1 & 1]; @@ -643,7 +643,7 @@ READ8_MEMBER(e0c6s46_device::io_r) return m_port_r[offset & 7]; case 0x7b: return m_r_dir; - + // P I/O ports case 0x60: case 0x61: case 0x62: case 0x63: return read_p(offset & 3); @@ -651,11 +651,11 @@ READ8_MEMBER(e0c6s46_device::io_r) return m_p_dir; case 0x7e: return m_p_pullup; - + // clock-timer (lo, hi) case 0x20: case 0x21: return m_clktimer_count >> (4 * (offset & 1)) & 0xf; - + // stopwatch timer case 0x22: return m_swl_count; @@ -663,7 +663,7 @@ READ8_MEMBER(e0c6s46_device::io_r) return m_swh_count; case 0x77: return m_stopwatch_on; - + // programmable timer case 0x24: case 0x25: return m_prgtimer_count >> (4 * (offset & 1)) & 0xf; @@ -673,34 +673,34 @@ READ8_MEMBER(e0c6s46_device::io_r) return m_prgtimer_on; case 0x79: return m_prgtimer_select; - + // buzzer case 0x74: return m_bz_freq; case 0x75: // d3: 1-shot buzzer is on return m_bz_1shot_on | m_bz_envelope; - + // OSC circuit case 0x70: return m_osc; - + // LCD driver case 0x71: return m_lcd_control; case 0x72: return m_lcd_contrast; - + // SVD circuit (supply voltage detection) case 0x73: // d3: criteria voltage* is 0: <=, 1: > source voltage (Vdd-Vss) // *0,1,2,3: -2.2V, -2.5V, -3.1V, -4.2V, 1 when off return m_svd | ((m_svd & 4 && m_svd != 7) ? 0 : 8); - + // write-only registers case 0x76: break; - + default: if (!space.debugger_access()) logerror("%s unknown io_r from $0F%02X at $%04X\n", tag(), offset, m_prev_pc); @@ -722,13 +722,13 @@ WRITE8_MEMBER(e0c6s46_device::io_w) m_possible_irq = true; break; } - + // K input ports case 0x41: // d0-d3: K0x irq on 0: rising edge, 1: falling edge m_dfk0 = data; break; - + // R output ports case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: write_r(offset & 7, data); @@ -744,7 +744,7 @@ WRITE8_MEMBER(e0c6s46_device::io_w) write_r(i, m_port_r[i]); } break; - + // P I/O ports case 0x60: case 0x61: case 0x62: case 0x63: write_p(offset & 3, data); @@ -764,7 +764,7 @@ WRITE8_MEMBER(e0c6s46_device::io_w) // d0-d3: Px* pull up resistor on/off m_p_pullup = data; break; - + // OSC circuit case 0x70: // d0,d1: CPU operating voltage @@ -793,7 +793,7 @@ WRITE8_MEMBER(e0c6s46_device::io_w) // d2: on m_svd = data & 7; break; - + // clock-timer case 0x76: // d0: reset watchdog @@ -804,7 +804,7 @@ WRITE8_MEMBER(e0c6s46_device::io_w) if (data & 2) m_clktimer_count = 0; break; - + // stopwatch timer case 0x77: // d0: run/stop counter @@ -878,7 +878,7 @@ WRITE8_MEMBER(e0c6s46_device::io_w) m_bz_envelope = data & 3; m_bz_1shot_on |= data & 8; break; - + // read-only registers case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: diff --git a/src/emu/cpu/e0c6200/e0c6s46.h b/src/emu/cpu/e0c6200/e0c6s46.h index acf5b62b41c..0b5f1e8bee3 100644 --- a/src/emu/cpu/e0c6200/e0c6s46.h +++ b/src/emu/cpu/e0c6200/e0c6s46.h @@ -110,7 +110,7 @@ private: UINT8 m_irqmask[6]; UINT8 m_osc; UINT8 m_svd; - + UINT8 m_lcd_control; UINT8 m_lcd_contrast; e0c6s46_pixel_update_func m_pixel_update_handler; @@ -123,7 +123,7 @@ private: void write_r4_out(); void write_p(UINT8 port, UINT8 data); UINT8 read_p(UINT8 port); - + UINT8 m_port_r[5]; UINT8 m_r_dir; UINT8 m_port_p[4]; @@ -148,7 +148,7 @@ private: int m_swl_count; int m_swh_count; void clock_stopwatch(); - + UINT8 m_prgtimer_select; UINT8 m_prgtimer_on; int m_prgtimer_src_pulse; diff --git a/src/emu/cpu/melps4/m58846.c b/src/emu/cpu/melps4/m58846.c index 5d6829c971f..e4842d28a6a 100644 --- a/src/emu/cpu/melps4/m58846.c +++ b/src/emu/cpu/melps4/m58846.c @@ -50,7 +50,7 @@ offs_t m58846_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *o void m58846_device::device_start() { melps4_cpu_device::device_start(); - + // set fixed state m_bm_page = 2; m_int_page = 1; @@ -158,7 +158,7 @@ void m58846_device::execute_one() } break; // 0xff - + } break; // 0xfc diff --git a/src/emu/cpu/melps4/melps4.c b/src/emu/cpu/melps4/melps4.c index ef593876d00..b9172f7745d 100644 --- a/src/emu/cpu/melps4/melps4.c +++ b/src/emu/cpu/melps4/melps4.c @@ -3,7 +3,7 @@ /* Mitsubishi MELPS 4 MCU family cores - + Known types and their features: (* means not emulated yet) @@ -16,7 +16,7 @@ M58846: 42-pin DIL, 2Kx9 ROM, 128x4 RAM, 2 timers(not same as M58845), extra I/O ports *M58847: 40-pin DIL, 2Kx9 ROM, 128x4 RAM, extra I/O ports(not same as M58846) *M58848: ? (couldn't find info, just that it exists) - + MELPS 41/42 subfamily: *M58494: 72-pin QFP CMOS, 4Kx10 ROM, 32x4 internal + 4Kx4 external RAM, 2 timers @@ -74,7 +74,7 @@ void melps4_cpu_device::device_start() m_data = &space(AS_DATA); m_prgmask = (1 << m_prgwidth) - 1; m_datamask = (1 << m_datawidth) - 1; - + // zerofill m_pc = 0; m_prev_pc = 0; @@ -87,7 +87,7 @@ void melps4_cpu_device::device_start() m_skip = false; m_inte = 0; m_intp = 1; - + m_a = 0; m_b = 0; m_e = 0; @@ -163,7 +163,7 @@ void melps4_cpu_device::device_reset() m_inte = 0; m_intp = 1; op_lcps(); // CPS=0 - + m_v = 0; m_w = 0; } diff --git a/src/emu/cpu/melps4/melps4.h b/src/emu/cpu/melps4/melps4.h index 3bcbedd3bd0..d8b9380f7d7 100644 --- a/src/emu/cpu/melps4/melps4.h +++ b/src/emu/cpu/melps4/melps4.h @@ -96,7 +96,7 @@ protected: UINT8 m_bm_page; // short BM default page: 14 on '40 to '44, 2 on '45,'46, 0 on '47 UINT8 m_int_page; // interrupt routine page: 12 on '40 to '44, 1 on '45,'46, 2 on '47 UINT8 m_xami_mask; // mask option for XAMI opcode on '40,'41,'45 (0xf for others) - + // internal state, misc regs UINT16 m_pc; // program counter (11 or 10-bit) UINT16 m_prev_pc; @@ -104,7 +104,7 @@ protected: UINT16 m_op; UINT16 m_prev_op; UINT8 m_bitmask; // opcode bit argument - + UINT8 m_cps; // DP,CY or DP',CY' selected bool m_skip; // skip next opcode UINT8 m_inte; // interrupt enable flag @@ -118,13 +118,13 @@ protected: UINT8 m_x, m_x2; // RAM index X, X', 2-bit UINT8 m_z, m_z2; // RAM index Z, Z', 1-bit, optional UINT8 m_cy, m_cy2; // carry flag(s) - + UINT8 m_h; // A/D converter H or generic UINT8 m_l; // A/D converter L or generic UINT8 m_c; // A/D converter counter UINT8 m_v; // timer control V UINT8 m_w; // timer control W - + // misc internal helpers UINT8 ram_r(); void ram_w(UINT8 data); diff --git a/src/emu/cpu/melps4/melps4d.c b/src/emu/cpu/melps4/melps4d.c index c38b4b54004..01d9b51f5ce 100644 --- a/src/emu/cpu/melps4/melps4d.c +++ b/src/emu/cpu/melps4/melps4d.c @@ -3,7 +3,7 @@ /* Mitsubishi MELPS 4 MCU family disassembler - + Not counting the extra opcodes for peripherals (eg. timers, A/D), each MCU in the series has small differences in the opcode map. @@ -117,10 +117,10 @@ CPU_DISASSEMBLE(m58846) instr = m58846_opmap[op]; dst += sprintf(dst, "%-6s", em_name[instr]); - + // get immediate param UINT8 bits = em_bits[instr]; - + // special case for LXY x,y if (instr == em_LXY) { diff --git a/src/emu/cpu/melps4/melps4op.inc b/src/emu/cpu/melps4/melps4op.inc index a63d55bbb50..296a5b1a39a 100644 --- a/src/emu/cpu/melps4/melps4op.inc +++ b/src/emu/cpu/melps4/melps4op.inc @@ -115,14 +115,14 @@ void melps4_cpu_device::op_lcps() if ((m_op & 1) != m_cps) { m_cps = m_op & 1; - + // swap registers UINT8 x, y, z, cy; x = m_x; y = m_y; z = m_z; cy = m_cy; - + m_x = m_x2; m_y = m_y2; m_z = m_z2; diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index c448e7b84fe..3e73d96f206 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -166,7 +166,7 @@ void mips3_device::clear_fastram(UINT32 select_start) m_fastram[i].readonly = false; m_fastram[i].base = NULL; } - m_fastram_select=select_start; + m_fastram_select=select_start; } /*------------------------------------------------- diff --git a/src/emu/cpu/tlcs90/tlcs90.c b/src/emu/cpu/tlcs90/tlcs90.c index 3ec7ab5bfaa..a5c866c7f54 100644 --- a/src/emu/cpu/tlcs90/tlcs90.c +++ b/src/emu/cpu/tlcs90/tlcs90.c @@ -6,9 +6,9 @@ emulation by Luca Elia, based on the Z80 core by Juergen Buchmueller - ChangeLog: + ChangeLog: - 20150517 Fixed TRUN bit masking (timers start/stop handling) [Rainer Keuchel] + 20150517 Fixed TRUN bit masking (timers start/stop handling) [Rainer Keuchel] *************************************************************************************************************/ diff --git a/src/emu/cpu/tms34010/tms34010.c b/src/emu/cpu/tms34010/tms34010.c index d1c520b473b..524fa8bd917 100644 --- a/src/emu/cpu/tms34010/tms34010.c +++ b/src/emu/cpu/tms34010/tms34010.c @@ -651,7 +651,7 @@ void tms340x0_device::device_reset() /* HALT the CPU if requested, and remember to re-read the starting PC */ /* the first time we are run */ m_reset_deferred = m_halt_on_reset; - + if (m_reset_deferred) { io_register_w(*m_program, REG_HSTCTLH, 0x8000, 0xffff); -- cgit v1.2.3-70-g09d2