From fc20d899ab83925a1169eeac2c61c70561b59ffb Mon Sep 17 00:00:00 2001 From: AJR Date: Sat, 10 Nov 2018 14:40:45 -0500 Subject: z80ctc: Allow a fixed-rate clock input to be configured for each channel. This improves performance by alleviating the need to drive the CLK/TRG inputs with high-frequency timers. --- src/devices/machine/z80ctc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/devices/machine/z80ctc.h') diff --git a/src/devices/machine/z80ctc.h b/src/devices/machine/z80ctc.h index 3a3234cf698..0b388eb3933 100644 --- a/src/devices/machine/z80ctc.h +++ b/src/devices/machine/z80ctc.h @@ -47,7 +47,7 @@ class z80ctc_channel_device : public device_t public: // construction/destruction - z80ctc_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + z80ctc_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); protected: // device-level overrides @@ -84,6 +84,8 @@ public: auto intr_callback() { return m_intr_cb.bind(); } template auto zc_callback() { return m_zc_cb[Channel].bind(); } // m_zc_cb[3] not supported on a standard ctc, only used for the tmpz84c015 + template void set_clk(u32 clock) { channel_config(Channel).set_clock(clock); } + template void set_clk(const XTAL &xtal) { channel_config(Channel).set_clock(xtal); } // read/write handlers DECLARE_READ8_MEMBER( read ); @@ -93,7 +95,7 @@ public: DECLARE_WRITE_LINE_MEMBER( trg2 ); DECLARE_WRITE_LINE_MEMBER( trg3 ); - u16 get_channel_constant(u8 channel) const { return m_channel[channel]->m_tconst; } + u16 get_channel_constant(int ch) const { return m_channel[ch]->m_tconst; } protected: // device-level overrides @@ -111,6 +113,8 @@ private: // internal helpers void interrupt_check(); + z80ctc_channel_device &channel_config(int ch) { return *subdevice(m_channel[ch].finder_tag()); } + // internal state devcb_write_line m_intr_cb; // interrupt callback devcb_write_line m_zc_cb[4]; // zero crossing/timer output callbacks -- cgit v1.2.3-70-g09d2