From 1b80b02eb0dcbe7b10a6ee95540a00069e3dba34 Mon Sep 17 00:00:00 2001 From: hap Date: Mon, 27 Nov 2017 19:44:34 +0100 Subject: tms1000: added preliminary tms1000c (nw) --- src/devices/cpu/tms1000/tms1k_base.cpp | 56 ++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'src/devices/cpu/tms1000/tms1k_base.cpp') diff --git a/src/devices/cpu/tms1000/tms1k_base.cpp b/src/devices/cpu/tms1000/tms1k_base.cpp index b7ce7aa3b87..eb389fc6bc9 100644 --- a/src/devices/cpu/tms1000/tms1k_base.cpp +++ b/src/devices/cpu/tms1000/tms1k_base.cpp @@ -404,6 +404,62 @@ void tms1k_base_device::op_retn() } +// TMS1400/TMS1000C 3-level stack version + +void tms1k_base_device::op_br3() +{ + // BR/BL: conditional branch + if (m_status) + { + m_pa = m_pb; // don't care about clatch + m_ca = m_cb; + m_pc = m_opcode & m_pc_mask; + } +} + +void tms1k_base_device::op_call3() +{ + // CALL/CALLL: conditional call + if (m_status) + { + // mask clatch 3 bits (no need to mask others) + m_clatch = (m_clatch << 1 | 1) & 7; + + m_sr = m_sr << m_pc_bits | m_pc; + m_pc = m_opcode & m_pc_mask; + + m_ps = m_ps << 4 | m_pa; + m_pa = m_pb; + + m_cs = m_cs << 2 | m_ca; + m_ca = m_cb; + } + else + { + m_pb = m_pa; + m_cb = m_ca; + } +} + +void tms1k_base_device::op_retn3() +{ + // RETN: return from subroutine + if (m_clatch & 1) + { + m_clatch >>= 1; + + m_pc = m_sr & m_pc_mask; + m_sr >>= m_pc_bits; + + m_pa = m_pb = m_ps & 0xf; + m_ps >>= 4; + + m_ca = m_cb = m_cs & 3; + m_cs >>= 2; + } +} + + // handle other: // TMS1000/common -- cgit v1.2.3-70-g09d2