From fe898720e91bc4c178f13a9880cba961f1f4ae66 Mon Sep 17 00:00:00 2001 From: angelosa Date: Sun, 25 Jun 2023 03:46:01 +0200 Subject: pc/pcipc.cpp: add base PCI for Cirrus Logic CL-GD5465 Laguna 3D --- scripts/src/video.lua | 15 +++ src/devices/video/clgd546x_laguna.cpp | 219 ++++++++++++++++++++++++++++++++++ src/devices/video/clgd546x_laguna.h | 56 +++++++++ src/mame/pc/pcipc.cpp | 5 +- 4 files changed, 293 insertions(+), 2 deletions(-) create mode 100644 src/devices/video/clgd546x_laguna.cpp create mode 100644 src/devices/video/clgd546x_laguna.h diff --git a/scripts/src/video.lua b/scripts/src/video.lua index ded980289aa..eed692d1b99 100644 --- a/scripts/src/video.lua +++ b/scripts/src/video.lua @@ -953,6 +953,20 @@ if (VIDEOS["PC_XGA"]~=null) then } end + +-------------------------------------------------- +-- +--@src/devices/video/clgd546x_laguna.h,VIDEOS["CLGD546X_LAGUNA"] = true +-------------------------------------------------- + +if (VIDEOS["CLGD546X_LAGUNA"]~=null) then + files { + MAME_DIR .. "src/devices/video/clgd546x_laguna.cpp", + MAME_DIR .. "src/devices/video/clgd546x_laguna.h", + } +end + + -------------------------------------------------- -- --@src/devices/video/virge_pci.h,VIDEOS["VIRGE_PCI"] = true @@ -965,6 +979,7 @@ if (VIDEOS["VIRGE_PCI"]~=null) then } end + -------------------------------------------------- -- --@src/devices/video/pcd8544.h,VIDEOS["PCD8544"] = true diff --git a/src/devices/video/clgd546x_laguna.cpp b/src/devices/video/clgd546x_laguna.cpp new file mode 100644 index 00000000000..12d684bb7e8 --- /dev/null +++ b/src/devices/video/clgd546x_laguna.cpp @@ -0,0 +1,219 @@ +// license:BSD-3-Clause +// copyright-holders:Angelo Salese + +#include "emu.h" +#include "clgd546x_laguna.h" + +#include "screen.h" + +#define LOG_WARN (1U << 1) +#define LOG_TODO (1U << 2) // log unimplemented registers + +#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_TODO) +//#define LOG_OUTPUT_FUNC osd_printf_info +#include "logmacro.h" + +#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__) +#define LOGTODO(...) LOGMASKED(LOG_TODO, __VA_ARGS__) + +DEFINE_DEVICE_TYPE(CIRRUS_GD5465_LAGUNA3D, cirrus_gd5465_laguna3d_device, "clgd5465_laguna", "Cirrus Logic GD-5465 \"Laguna 3D\"") + +cirrus_gd5465_laguna3d_device::cirrus_gd5465_laguna3d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : pci_device(mconfig, CIRRUS_GD5465_LAGUNA3D, tag, owner, clock) + , m_svga(*this, "svga") + , m_vga_rom(*this, "vga_rom") +{ + // device ID 0x1013 Cirrus Logic + // 0x00dx for Laguna revs + // subvendor ID: Returns values from ROM 0x7ff8-0x7ffb + set_ids_agp(0x101300d6, 0x00, 0x10130000); + // TODO: class can be 0x80 (other display controller) with P18 pin. +} + +ROM_START( gd5465 ) + ROM_REGION32_LE( 0x8000, "vga_rom", ROMREGION_ERASEFF ) + ROM_SYSTEM_BIOS( 0, "chaintech", "Chaintech GA-5465AS 1.62c" ) + ROMX_LOAD( "chaintech.vbi", 0x0000, 0x8000, CRC(8afa1afb) SHA1(251a953d442dc34738f80371cfbd0fd9f1097635), ROM_BIOS(0) ) +ROM_END + +const tiny_rom_entry *cirrus_gd5465_laguna3d_device::device_rom_region() const +{ + return ROM_NAME(gd5465); +} + +void cirrus_gd5465_laguna3d_device::device_add_mconfig(machine_config &config) +{ + screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); + screen.set_raw(XTAL(25'174'800), 900, 0, 640, 526, 0, 480); + screen.set_screen_update(m_svga, FUNC(cirrus_gd5446_device::screen_update)); + + // TODO: bump to GD5465 + CIRRUS_GD5446(config, m_svga, 0); + m_svga->set_screen("screen"); + // FIXME: shared RAM + // in 4 and 8 MB versions + m_svga->set_vram_size(8*1024*1024); +} + +void cirrus_gd5465_laguna3d_device::device_start() +{ + pci_device::device_start(); + + add_map( 32*1024, M_MEM, FUNC(cirrus_gd5465_laguna3d_device::mmio_map)); + add_map( 32*1024*1024, M_MEM, FUNC(cirrus_gd5465_laguna3d_device::vram_aperture_map)); + + add_rom((u8 *)m_vga_rom->base(), 0x8000); + expansion_rom_base = 0xc0000; + + // INTA# + intr_pin = 1; + save_item(NAME(m_vga_legacy_enable)); + + // TODO: fast back-to-back +} + +void cirrus_gd5465_laguna3d_device::device_reset() +{ + pci_device::device_reset(); + + // TODO: to be checked + command = 0x0000; + status = 0x0000; + + m_vga_legacy_enable = true; + remap_cb(); +} + +void cirrus_gd5465_laguna3d_device::config_map(address_map &map) +{ + pci_device::config_map(map); + // TODO: AGP CAPPTR +// map(0xf8, 0xf8) PCI VGA Shadow Register +// map(0xfc, 0xfc) PCI Vendor Specific Control Register +} + +void cirrus_gd5465_laguna3d_device::mmio_map(address_map &map) +{ + +} + +void cirrus_gd5465_laguna3d_device::vram_aperture_map(address_map &map) +{ + +} + +// TODO: this should really be a subclass of VGA +void cirrus_gd5465_laguna3d_device::legacy_memory_map(address_map &map) +{ + map(0xa0000, 0xbffff).rw(FUNC(cirrus_gd5465_laguna3d_device::vram_r), FUNC(cirrus_gd5465_laguna3d_device::vram_w)); +} + +void cirrus_gd5465_laguna3d_device::legacy_io_map(address_map &map) +{ + map(0x03b0, 0x03bf).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_w)); + map(0x03c0, 0x03cf).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_w)); + map(0x03d0, 0x03df).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_w)); +} + +uint8_t cirrus_gd5465_laguna3d_device::vram_r(offs_t offset) +{ + return downcast(m_svga.target())->mem_r(offset); +} + +void cirrus_gd5465_laguna3d_device::vram_w(offs_t offset, uint8_t data) +{ + downcast(m_svga.target())->mem_w(offset, data); +} + +u32 cirrus_gd5465_laguna3d_device::vga_3b0_r(offs_t offset, uint32_t mem_mask) +{ + uint32_t result = 0; + if (ACCESSING_BITS_0_7) + result |= downcast(m_svga.target())->port_03b0_r(offset * 4 + 0) << 0; + if (ACCESSING_BITS_8_15) + result |= downcast(m_svga.target())->port_03b0_r(offset * 4 + 1) << 8; + if (ACCESSING_BITS_16_23) + result |= downcast(m_svga.target())->port_03b0_r(offset * 4 + 2) << 16; + if (ACCESSING_BITS_24_31) + result |= downcast(m_svga.target())->port_03b0_r(offset * 4 + 3) << 24; + return result; +} + +void cirrus_gd5465_laguna3d_device::vga_3b0_w(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + if (ACCESSING_BITS_0_7) + downcast(m_svga.target())->port_03b0_w(offset * 4 + 0, data >> 0); + if (ACCESSING_BITS_8_15) + downcast(m_svga.target())->port_03b0_w(offset * 4 + 1, data >> 8); + if (ACCESSING_BITS_16_23) + downcast(m_svga.target())->port_03b0_w(offset * 4 + 2, data >> 16); + if (ACCESSING_BITS_24_31) + downcast(m_svga.target())->port_03b0_w(offset * 4 + 3, data >> 24); +} + + +u32 cirrus_gd5465_laguna3d_device::vga_3c0_r(offs_t offset, uint32_t mem_mask) +{ + uint32_t result = 0; + if (ACCESSING_BITS_0_7) + result |= downcast(m_svga.target())->port_03c0_r(offset * 4 + 0) << 0; + if (ACCESSING_BITS_8_15) + result |= downcast(m_svga.target())->port_03c0_r(offset * 4 + 1) << 8; + if (ACCESSING_BITS_16_23) + result |= downcast(m_svga.target())->port_03c0_r(offset * 4 + 2) << 16; + if (ACCESSING_BITS_24_31) + result |= downcast(m_svga.target())->port_03c0_r(offset * 4 + 3) << 24; + return result; +} + +void cirrus_gd5465_laguna3d_device::vga_3c0_w(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + if (ACCESSING_BITS_0_7) + downcast(m_svga.target())->port_03c0_w(offset * 4 + 0, data >> 0); + if (ACCESSING_BITS_8_15) + downcast(m_svga.target())->port_03c0_w(offset * 4 + 1, data >> 8); + if (ACCESSING_BITS_16_23) + downcast(m_svga.target())->port_03c0_w(offset * 4 + 2, data >> 16); + if (ACCESSING_BITS_24_31) + downcast(m_svga.target())->port_03c0_w(offset * 4 + 3, data >> 24); +} + +u32 cirrus_gd5465_laguna3d_device::vga_3d0_r(offs_t offset, uint32_t mem_mask) +{ + uint32_t result = 0; + if (ACCESSING_BITS_0_7) + result |= downcast(m_svga.target())->port_03d0_r(offset * 4 + 0) << 0; + if (ACCESSING_BITS_8_15) + result |= downcast(m_svga.target())->port_03d0_r(offset * 4 + 1) << 8; + if (ACCESSING_BITS_16_23) + result |= downcast(m_svga.target())->port_03d0_r(offset * 4 + 2) << 16; + if (ACCESSING_BITS_24_31) + result |= downcast(m_svga.target())->port_03d0_r(offset * 4 + 3) << 24; + return result; +} + +void cirrus_gd5465_laguna3d_device::vga_3d0_w(offs_t offset, uint32_t data, uint32_t mem_mask) +{ + if (ACCESSING_BITS_0_7) + downcast(m_svga.target())->port_03d0_w(offset * 4 + 0, data >> 0); + if (ACCESSING_BITS_8_15) + downcast(m_svga.target())->port_03d0_w(offset * 4 + 1, data >> 8); + if (ACCESSING_BITS_16_23) + downcast(m_svga.target())->port_03d0_w(offset * 4 + 2, data >> 16); + if (ACCESSING_BITS_24_31) + downcast(m_svga.target())->port_03d0_w(offset * 4 + 3, data >> 24); +} + +void cirrus_gd5465_laguna3d_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space, + uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) +{ + if (m_vga_legacy_enable) + { + memory_space->install_readwrite_handler(0xa0000, 0xbffff, read8sm_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vram_r)), write8sm_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vram_w))); + + io_space->install_readwrite_handler(0x3b0, 0x3bf, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_w))); + io_space->install_readwrite_handler(0x3c0, 0x3cf, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_w))); + io_space->install_readwrite_handler(0x3d0, 0x3df, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_w))); + //memory_space->install_rom(0xc0000, 0xcffff, (void *)expansion_rom); + } +} diff --git a/src/devices/video/clgd546x_laguna.h b/src/devices/video/clgd546x_laguna.h new file mode 100644 index 00000000000..010061d0a5e --- /dev/null +++ b/src/devices/video/clgd546x_laguna.h @@ -0,0 +1,56 @@ +// license:BSD-3-Clause +// copyright-holders:Angelo Salese +#ifndef MAME_VIDEO_CLGD546X_LAGUNA_H +#define MAME_VIDEO_CLGD546X_LAGUNA_H + +#pragma once + +#include "machine/pci.h" +//#include "video/pc_vga.h" +#include "video/clgd542x.h" + +class cirrus_gd5465_laguna3d_device : public pci_device +{ +public: + cirrus_gd5465_laguna3d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + void legacy_memory_map(address_map &map); + void legacy_io_map(address_map &map); + +protected: + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + + virtual const tiny_rom_entry *device_rom_region() const override; + + virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space, + uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override; + + virtual void config_map(address_map &map) override; + + virtual void mmio_map(address_map &map); + virtual void vram_aperture_map(address_map &map); +private: + required_device m_svga; + required_memory_region m_vga_rom; + + u8 vram_r(offs_t offset); + void vram_w(offs_t offset, uint8_t data); + u32 vga_3b0_r(offs_t offset, uint32_t mem_mask = ~0); + void vga_3b0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + u32 vga_3c0_r(offs_t offset, uint32_t mem_mask = ~0); + void vga_3c0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + u32 vga_3d0_r(offs_t offset, uint32_t mem_mask = ~0); + void vga_3d0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); + +// u32 unmap_log_r(offs_t offset, u32 mem_mask = ~0); +// void unmap_log_w(offs_t offset, u32 data, u32 mem_mask = ~0); + + bool m_vga_legacy_enable = false; + u32 m_main_scratchpad_id = 0; +}; + +DECLARE_DEVICE_TYPE(CIRRUS_GD5465_LAGUNA3D, cirrus_gd5465_laguna3d_device) + +#endif // MAME_VIDEO_CLGD546X_LAGUNA_H diff --git a/src/mame/pc/pcipc.cpp b/src/mame/pc/pcipc.cpp index e2c6f7b9279..800c9078a07 100644 --- a/src/mame/pc/pcipc.cpp +++ b/src/mame/pc/pcipc.cpp @@ -41,6 +41,7 @@ #include "video/mga2064w.h" #include "video/virge_pci.h" #include "video/riva128.h" +#include "video/clgd546x_laguna.h" namespace { @@ -661,8 +662,8 @@ void pcipc_state::pciagp(machine_config &config) serport1.cts_handler().set("board4:w83977tf", FUNC(fdc37c93x_device::ncts2_w)); #endif - // TODO: temp, to be converted to a proper AGP card once we make this to boot - VIRGE_PCI(config, "pci:0e.0", 0); // J4C1 + // TODO: temp link, to be moved to quakeat.cpp + CIRRUS_GD5465_LAGUNA3D(config, "pci:01.0:00.0", 0); } ROM_START(pcipc) -- cgit v1.2.3