From f7a8b2ba0a717ce49c010589bd5f3f2df6b259d7 Mon Sep 17 00:00:00 2001 From: Patrick Mackinlay Date: Wed, 24 May 2023 15:48:42 +0700 Subject: New working systems ------------------- Omron Luna 88K [Jeffrey McMahill] --- src/mame/mame.lst | 1 + src/mame/omron/luna_88k.cpp | 453 +++++++++++++++++++++++++++++--------------- 2 files changed, 306 insertions(+), 148 deletions(-) diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 1765b7176dd..ecbfb248d44 100755 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -34520,6 +34520,7 @@ spaceg // (c) 19?? luna // Omron Luna @source:omron/luna_88k.cpp +luna88k // Omron Luna 88K luna88k2 // Omron Luna 88K² @source:openuni/hektor.cpp diff --git a/src/mame/omron/luna_88k.cpp b/src/mame/omron/luna_88k.cpp index 9b6507a7092..017d09086f0 100644 --- a/src/mame/omron/luna_88k.cpp +++ b/src/mame/omron/luna_88k.cpp @@ -21,55 +21,6 @@ * - scsi issues with OpenBSD */ -/* - * Omron 3W4SX-9100/DT9581 UNIX WORKSTATION - * - * PWB7187 (MAIN) - * -- - * MB89352A SCSI - * D7201AC serial (keyboard/mouse + port A) - * HD647180X0FS6 I/O processor (serial port -00 and -01, printer) - * TF116NF - * TF175NF - * HM62256ALFP-10T * 5 32,768x8 static RAM - * MB89352FP SCSI - * MDS74ACE36X646 - * TF177HF - * MC88915FN70 clock driver - * DS1000M-25 delay line - * HN27C1024HCC-85 * 2 PROM - * DS1397 RTC/NVRAM MC146818 RTC + 4Kx8 NVRAM - * M5M82C55A * 2 PPI - * OSC1 12.288MHz IOP clock - * OSC2 33.333MHz CPU clock - * OSC3 50MHz - * OSC4 200Hz - * OSC5 8MHz - * KSS EXO3 3C 19.660M PC-98 bus? - * Ports: keyboard, SCSI, RS232C-A, -01, -00, printer - * - * PWB7188 (CPU+MMU) - * -- - * MC88100RC33 - * MC88200RC33 * 2 - * - * PWB87132 (W-LAN) - * -- - * AM7990JC/80 - * DS1220Y-200 NVRAM - * AM7992BDC - * OSC1 40MHz - * Another AM7990 and AM7992B are unpopulated - * - * PWB7131 BM08HR (video) - * -- - * Bt458LPJ124 RAMDAC - * HD6445CP4 - * Bt438KPJ - * OSC1 108.9920MHz - * HM53462ZP-10 * 8*8 - */ - #include "emu.h" #include "luna_kbd.h" @@ -86,6 +37,7 @@ #include "machine/mc88200.h" #include "machine/nscsi_bus.h" #include "machine/ram.h" +#include "machine/timekpr.h" #include "machine/z80sio.h" #include "video/bt45x.h" #include "video/hd44780.h" @@ -104,26 +56,21 @@ namespace { -class luna_88k_state : public driver_device +class luna_88k_state_base : public driver_device { public: - luna_88k_state(machine_config const &mconfig, device_type type, char const *tag) + luna_88k_state_base(machine_config const &mconfig, device_type type, char const *tag) : driver_device(mconfig, type, tag) , m_cpu(*this, "cpu") , m_cmmu(*this, "cmmu%u", 0U) , m_ram(*this, "ram") , m_iop(*this, "iop") - , m_rtc(*this, "rtc") , m_sio(*this, "sio") , m_pio(*this, "pio%u", 0U) , m_serial(*this, "serial%u", 0U) - , m_spc(*this, "scsi%u:7:spc", 0U) - , m_net(*this, "net%u", 0U) - , m_fzrom(*this, "fzrom") , m_ramdac(*this, "ramdac") , m_vram(*this, "vram", 0x20'0000, ENDIANNESS_BIG) , m_lcdc(*this, "lcdc") - , m_eprom(*this, "eprom") , m_3port_ram(*this, "3port_ram") , m_boot(*this, "boot") , m_sw(*this, "SW%u", 1U) @@ -133,8 +80,7 @@ public: { } - void luna88k2(machine_config &config); - void init(); + void common_config(machine_config &config, XTAL clock); DECLARE_INPUT_CHANGED_MEMBER(abort) { irq(0, 7, newval); } @@ -142,8 +88,8 @@ protected: virtual void machine_start() override; virtual void machine_reset() override; -private: - void cpu_map(address_map &map); + virtual void cpu_map(address_map &map); + void iop_map_mem(address_map &map); void iop_map_pio(address_map &map); @@ -167,23 +113,19 @@ private: u16 net_r(offs_t offset) { return m_nram[u16(offset >> 1)]; } void net_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(&m_nram[u16(offset >> 1)]); } +private: required_device m_cpu; required_device_array m_cmmu; required_device m_ram; required_device m_iop; - required_device m_rtc; required_device m_sio; required_device_array m_pio; required_device_array m_serial; - required_device_array m_spc; - required_device_array m_net; - required_region_ptr m_fzrom; required_device m_ramdac; memory_share_creator m_vram; required_device m_lcdc; - required_region_ptr m_eprom; required_shared_ptr m_3port_ram; memory_view m_boot; @@ -200,10 +142,74 @@ private: u8 m_irq_mask[4]; util::endian_cast m_nram; +}; + +class luna88k_state : public luna_88k_state_base +{ +public: + luna88k_state(machine_config const &mconfig, device_type type, char const *tag) + : luna_88k_state_base(mconfig, type, tag) + , m_rtc(*this, "rtc") + , m_spc(*this, "scsi:7:spc") + , m_net(*this, "net") + , m_eprom(*this, "eprom") + { + } + + void luna88k(machine_config &config); + void init(); + +protected: + virtual void cpu_map(address_map &map) override; + + required_device m_rtc; + required_device m_spc; + required_device m_net; + required_region_ptr m_eprom; +}; + +class luna88k2_state : public luna_88k_state_base +{ +public: + luna88k2_state(machine_config const &mconfig, device_type type, char const *tag) + : luna_88k_state_base(mconfig, type, tag) + , m_rtc(*this, "rtc") + , m_spc(*this, "scsi%u:7:spc", 0U) + , m_net(*this, "net%u", 0U) + , m_eprom(*this, "eprom") + , m_fzrom(*this, "fzrom") + { + } + + void luna88k2(machine_config &config); + void init(); + +protected: + virtual void machine_start() override; + virtual void cpu_map(address_map &map) override; + + required_device m_rtc; + required_device_array m_spc; + required_device_array m_net; + required_region_ptr m_eprom; + required_region_ptr m_fzrom; + +private: u8 m_fzrom_addr; }; -void luna_88k_state::init() +void luna88k_state::init() +{ + /* + * HACK: avoid firmware data access exception handler returning to SXIP + * causing infinite loop. Does hardware only recognize the bus error in + * the second stage of the pipeline? + */ + m_eprom[0x16bc >> 2] = 0x80204080; // ldcr r1,sxip + m_eprom[0x16c0 >> 2] = 0x60210004; // addu r1,r1,0x4 +} + +void luna88k2_state::init() { // HACK: bypass abort switch test failure m_eprom[0x1fa58 >> 2] = 0xf4406000; @@ -218,7 +224,7 @@ void luna_88k_state::init() m_eprom[0x1e4c0 >> 2] = 0xf7206000; } -void luna_88k_state::machine_start() +void luna_88k_state_base::machine_start() { save_item(NAME(m_plane_active)); save_item(NAME(m_plane_func)); @@ -228,12 +234,17 @@ void luna_88k_state::machine_start() save_item(NAME(m_irq_active)); save_item(NAME(m_irq_mask)); - save_item(NAME(m_fzrom_addr)); - m_nram = util::big_endian_cast(m_3port_ram.target()); } -void luna_88k_state::machine_reset() +void luna88k2_state::machine_start() +{ + luna_88k_state_base::machine_start(); + + save_item(NAME(m_fzrom_addr)); +} + +void luna_88k_state_base::machine_reset() { m_boot.select(0); @@ -252,7 +263,7 @@ void luna_88k_state::machine_reset() irq_check(); } -void luna_88k_state::cpu_map(address_map &map) +void luna_88k_state_base::cpu_map(address_map &map) { map(0x0000'0000, 0x03ff'ffff).view(m_boot); m_boot[0](0x0000'0000, 0x0003'ffff).rom().region("eprom", 0); @@ -266,15 +277,14 @@ void luna_88k_state::cpu_map(address_map &map) map(0x4100'0000, 0x4103'ffff).lw32([this](offs_t offset, u32 data) { m_boot.select(1); }, "boot"); map(0x4300'0000, 0x4300'03ff).rom().region("fuserom", 0); - map(0x4500'0000, 0x4500'0001).rw(m_rtc, FUNC(ds1397_device::read), FUNC(ds1397_device::write)); - map(0x4700'0000, 0x4700'003f).rw(m_rtc, FUNC(ds1397_device::xram_r), FUNC(ds1397_device::xram_w)); + map(0x4900'0000, 0x4900'000f).rw(m_pio[0], FUNC(i8255_device::read), FUNC(i8255_device::write)).umask32(0xff000000); map(0x4d00'0000, 0x4d00'000f).rw(m_pio[1], FUNC(i8255_device::read), FUNC(i8255_device::write)).umask32(0xff000000); map(0x5100'0000, 0x5100'000f).rw(m_sio, FUNC(upd7201_device::ba_cd_r), FUNC(upd7201_device::ba_cd_w)).umask32(0xff000000); //map(0x6100'0000, 0x6100'0003); // tas register map(0x6300'0000, 0x6300'0003).nopr(); // power switch? map(0x6300'0000, 0x6300'000f).lw32([this](offs_t offset, u32 data) { irq(offset, 6, 0); }, "sysclk_clr"); - map(0x6500'0000, 0x6500'000f).rw(FUNC(luna_88k_state::irq_ctl_r), FUNC(luna_88k_state::irq_ctl_w)); + map(0x6500'0000, 0x6500'000f).rw(FUNC(luna_88k_state_base::irq_ctl_r), FUNC(luna_88k_state_base::irq_ctl_w)); map(0x6900'0000, 0x6900'000f).lrw32( [this](offs_t offset) { irq(offset, 1, 0); return 0xffffffff; }, "softint_clr", [this](offs_t offset, u32 data) { irq(offset, 1, 1); }, "softint_set"); @@ -284,45 +294,62 @@ void luna_88k_state::cpu_map(address_map &map) map(0x7100'0000, 0x7101'ffff).ram().share("3port_ram"); - // 0x8100'0000 ext board A - // 0x8300'0000 ext board B - // 0x9000'0000 pc-98 ext board - // 0x9100'0000 pc-9801 irq 4 map(0x8000'0000, 0x9fff'ffff).lr32([this]() { m_cmmu[1]->bus_error_w(1); return 0; }, "bus_error"); //map(0xb100'0000, 0xb100'ffff); // rfcnt (pad,vert_loc,pad,horiz_loc) map(0xb104'0000, 0xb104'ffff).lw8([this](u8 data) { LOG("plane_active 0x%02x\n", data); m_plane_active = data; }, "plane_active"); - map(0xb108'0000, 0xb10b'ffff).w(FUNC(luna_88k_state::plane_common_w)); - map(0xb10c'0000, 0xb10f'ffff).rw(FUNC(luna_88k_state::plane_r<0>), FUNC(luna_88k_state::plane_w<0>)); - map(0xb110'0000, 0xb113'ffff).rw(FUNC(luna_88k_state::plane_r<1>), FUNC(luna_88k_state::plane_w<1>)); - map(0xb114'0000, 0xb117'ffff).rw(FUNC(luna_88k_state::plane_r<2>), FUNC(luna_88k_state::plane_w<2>)); - map(0xb118'0000, 0xb11b'ffff).rw(FUNC(luna_88k_state::plane_r<3>), FUNC(luna_88k_state::plane_w<3>)); - map(0xb11c'0000, 0xb11f'ffff).rw(FUNC(luna_88k_state::plane_r<4>), FUNC(luna_88k_state::plane_w<4>)); - map(0xb120'0000, 0xb123'ffff).rw(FUNC(luna_88k_state::plane_r<5>), FUNC(luna_88k_state::plane_w<5>)); - map(0xb124'0000, 0xb127'ffff).rw(FUNC(luna_88k_state::plane_r<6>), FUNC(luna_88k_state::plane_w<6>)); - map(0xb128'0000, 0xb12b'ffff).rw(FUNC(luna_88k_state::plane_r<7>), FUNC(luna_88k_state::plane_w<7>)); - map(0xb12c'0000, 0xb12c'ffff).w(FUNC(luna_88k_state::logic_common_w)); - - map(0xb130'0000, 0xb130'ffff).w(FUNC(luna_88k_state::logic_w<0>)); - map(0xb134'0000, 0xb134'ffff).w(FUNC(luna_88k_state::logic_w<1>)); - map(0xb138'0000, 0xb138'ffff).w(FUNC(luna_88k_state::logic_w<2>)); - map(0xb13c'0000, 0xb13c'ffff).w(FUNC(luna_88k_state::logic_w<3>)); - map(0xb140'0000, 0xb140'ffff).w(FUNC(luna_88k_state::logic_w<4>)); - map(0xb144'0000, 0xb144'ffff).w(FUNC(luna_88k_state::logic_w<5>)); - map(0xb148'0000, 0xb148'ffff).w(FUNC(luna_88k_state::logic_w<6>)); - map(0xb14c'0000, 0xb14c'ffff).w(FUNC(luna_88k_state::logic_w<7>)); + map(0xb108'0000, 0xb10b'ffff).w(FUNC(luna_88k_state_base::plane_common_w)); + map(0xb10c'0000, 0xb10f'ffff).rw(FUNC(luna_88k_state_base::plane_r<0>), FUNC(luna_88k_state_base::plane_w<0>)); + map(0xb110'0000, 0xb113'ffff).rw(FUNC(luna_88k_state_base::plane_r<1>), FUNC(luna_88k_state_base::plane_w<1>)); + map(0xb114'0000, 0xb117'ffff).rw(FUNC(luna_88k_state_base::plane_r<2>), FUNC(luna_88k_state_base::plane_w<2>)); + map(0xb118'0000, 0xb11b'ffff).rw(FUNC(luna_88k_state_base::plane_r<3>), FUNC(luna_88k_state_base::plane_w<3>)); + map(0xb11c'0000, 0xb11f'ffff).rw(FUNC(luna_88k_state_base::plane_r<4>), FUNC(luna_88k_state_base::plane_w<4>)); + map(0xb120'0000, 0xb123'ffff).rw(FUNC(luna_88k_state_base::plane_r<5>), FUNC(luna_88k_state_base::plane_w<5>)); + map(0xb124'0000, 0xb127'ffff).rw(FUNC(luna_88k_state_base::plane_r<6>), FUNC(luna_88k_state_base::plane_w<6>)); + map(0xb128'0000, 0xb12b'ffff).rw(FUNC(luna_88k_state_base::plane_r<7>), FUNC(luna_88k_state_base::plane_w<7>)); + map(0xb12c'0000, 0xb12c'ffff).w(FUNC(luna_88k_state_base::logic_common_w)); + + map(0xb130'0000, 0xb130'ffff).w(FUNC(luna_88k_state_base::logic_w<0>)); + map(0xb134'0000, 0xb134'ffff).w(FUNC(luna_88k_state_base::logic_w<1>)); + map(0xb138'0000, 0xb138'ffff).w(FUNC(luna_88k_state_base::logic_w<2>)); + map(0xb13c'0000, 0xb13c'ffff).w(FUNC(luna_88k_state_base::logic_w<3>)); + map(0xb140'0000, 0xb140'ffff).w(FUNC(luna_88k_state_base::logic_w<4>)); + map(0xb144'0000, 0xb144'ffff).w(FUNC(luna_88k_state_base::logic_w<5>)); + map(0xb148'0000, 0xb148'ffff).w(FUNC(luna_88k_state_base::logic_w<6>)); + map(0xb14c'0000, 0xb14c'ffff).w(FUNC(luna_88k_state_base::logic_w<7>)); map(0xc100'0000, 0xc100'000f).m(m_ramdac, FUNC(bt458_device::map)).umask32(0xff000000).mirror(0x0010'0000); // 0xd000'0000 board check register? // 0xd100'0000 crtc-ii // 0xd180'0000 bitmap board identify rom +} + +void luna88k_state::cpu_map(address_map &map) +{ + luna_88k_state_base::cpu_map(map); + + map(0x4500'0000, 0x4500'1fff).rw(m_rtc, FUNC(m48t02_device::read), FUNC(m48t02_device::write)).umask32(0xff000000); + map(0xe100'0000, 0xe100'003f).m(m_spc, FUNC(mb89352_device::map)).umask32(0xff000000); + map(0xf100'0000, 0xf100'0007).rw(m_net, FUNC(am7990_device::regs_r), FUNC(am7990_device::regs_w)).umask32(0xffff0000); +} + +void luna88k2_state::cpu_map(address_map &map) +{ + luna_88k_state_base::cpu_map(map); + + map(0x4500'0000, 0x4500'0001).rw(m_rtc, FUNC(ds1397_device::read), FUNC(ds1397_device::write)); + map(0x4700'0000, 0x4700'003f).rw(m_rtc, FUNC(ds1397_device::xram_r), FUNC(ds1397_device::xram_w)); + + // 0x8100'0000 ext board A + // 0x8300'0000 ext board B + // 0x9000'0000 pc-98 ext board + // 0x9100'0000 pc-9801 irq 4 map(0xe100'0000, 0xe100'003f).m(m_spc[0], FUNC(mb89352_device::map)).umask32(0xff000000); map(0xe100'0040, 0xe100'007f).m(m_spc[1], FUNC(mb89352_device::map)).umask32(0xff000000); map(0xf100'0000, 0xf100'0007).rw(m_net[0], FUNC(am7990_device::regs_r), FUNC(am7990_device::regs_w)).umask32(0xffff0000); - map(0xf100'0008, 0xf100'0009).lrw16( [this]() { @@ -334,12 +361,12 @@ void luna_88k_state::cpu_map(address_map &map) map(0xf100'0010, 0xf100'0017).rw(m_net[1], FUNC(am7990_device::regs_r), FUNC(am7990_device::regs_w)).umask32(0xffff0000); } -void luna_88k_state::iop_map_mem(address_map &map) +void luna_88k_state_base::iop_map_mem(address_map &map) { //map(0x0'0000, 0x0'ffff).ram().share("iop_ram"); } -void luna_88k_state::iop_map_pio(address_map &map) +void luna_88k_state_base::iop_map_pio(address_map &map) { map(0x0049, 0x0049).nopr(); } @@ -354,15 +381,15 @@ void keyboard_devices(device_slot_interface &device) device.option_add("keyboard", LUNA_KEYBOARD); } -void luna_88k_state::luna88k2(machine_config &config) +void luna_88k_state_base::common_config(machine_config &config, XTAL clock) { - MC88100(config, m_cpu, 33.333_MHz_XTAL); - m_cpu->set_addrmap(AS_PROGRAM, &luna_88k_state::cpu_map); + MC88100(config, m_cpu, clock.value()); + m_cpu->set_addrmap(AS_PROGRAM, &luna_88k_state_base::cpu_map); - MC88200(config, m_cmmu[0], 33.333_MHz_XTAL, 0x07); // cpu0 cmmu i0 + MC88200(config, m_cmmu[0], clock.value(), 0x07); // cpu0 cmmu i0 m_cmmu[0]->set_mbus(m_cpu, AS_PROGRAM); m_cpu->set_cmmu_i(m_cmmu[0]); - MC88200(config, m_cmmu[1], 33.333_MHz_XTAL, 0x06); // cpu0 cmmu d0 + MC88200(config, m_cmmu[1], clock.value(), 0x06); // cpu0 cmmu d0 m_cmmu[1]->set_mbus(m_cpu, AS_PROGRAM); m_cpu->set_cmmu_d(m_cmmu[1]); @@ -373,15 +400,12 @@ void luna_88k_state::luna88k2(machine_config &config) clock_device &sys_clk(CLOCK(config, "sys_clk", 200 / 2)); sys_clk.signal_handler().set([this](int state) { if (state) irq(0, 6, 1); }); - DS1397(config, m_rtc, 32'768); - m_rtc->set_epoch(1990); - HD647180X(config, m_iop, 12'288'000); - m_iop->set_addrmap(AS_PROGRAM, &luna_88k_state::iop_map_mem); - m_iop->set_addrmap(AS_IO, &luna_88k_state::iop_map_pio); + m_iop->set_addrmap(AS_PROGRAM, &luna_88k_state_base::iop_map_mem); + m_iop->set_addrmap(AS_IO, &luna_88k_state_base::iop_map_pio); UPD7201(config, m_sio, 19'660'800); // ? - m_sio->out_int_callback().set(&luna_88k_state::irq<0, 5>, "irq0,5"); + m_sio->out_int_callback().set(&luna_88k_state_base::irq<0, 5>, "irq0,5"); // RS-232C-A RS232_PORT(config, m_serial[0], default_rs232_devices, nullptr); @@ -459,8 +483,64 @@ void luna_88k_state::luna88k2(machine_config &config) m_pio[1]->out_pc_callback().append(m_lcdc, FUNC(ks0066_f00_device::rs_w)).bit(6); m_pio[1]->out_pc_callback().append(m_lcdc, FUNC(ks0066_f00_device::e_w)).bit(7); + + // TODO: crt timing control by HD6445CP4 + screen_device &crt(SCREEN(config, "crt", SCREEN_TYPE_RASTER)); + crt.set_raw(108'992'000, 2048, 0, 1280, 1024, 0, 1024); + crt.set_screen_update(FUNC(luna_88k_state_base::screen_update)); + + BT458(config, m_ramdac, 108'992'000); + + KS0066_F00(config, m_lcdc, 250'000); + m_lcdc->set_function_set_at_any_time(true); + m_lcdc->set_lcd_size(2, 16); + + palette_device &palette(PALETTE(config, "palette", palette_device::MONOCHROME)); + + screen_device &lcd(SCREEN(config, "lcd", SCREEN_TYPE_LCD)); + lcd.set_raw(192'000, 40 * 6, 0, 16 * 6, 2 * 8, 0, 2 * 8); + lcd.set_screen_update(m_lcdc, FUNC(ks0066_f00_device::screen_update)); + lcd.set_palette(palette); +} + +void luna88k_state::luna88k(machine_config &config) +{ + luna_88k_state_base::common_config(config, 50_MHz_XTAL / 2); + + M48T02(config, m_rtc); + + NSCSI_BUS(config, "scsi"); + NSCSI_CONNECTOR(config, "scsi:0", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:1", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:2", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:3", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:4", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:5", scsi_devices, nullptr); + NSCSI_CONNECTOR(config, "scsi:6", scsi_devices, "harddisk"); + NSCSI_CONNECTOR(config, "scsi:7").option_set("spc", MB89352).machine_config( + [this](device_t *device) + { + mb89352_device &spc = downcast(*device); + + spc.set_clock(8_MHz_XTAL); + spc.out_irq_callback().set(*this, &luna88k_state::irq<0, 3>, "irq0,3"); + }); + + AM7990(config, m_net, 40_MHz_XTAL / 4); + m_net->intr_out().set(&luna88k_state::irq<0, 4>, "irq0,4").invert(); + m_net->dma_in().set(FUNC(luna88k_state::net_r)); + m_net->dma_out().set(FUNC(luna88k_state::net_w)); +} + +void luna88k2_state::luna88k2(machine_config &config) +{ + luna_88k_state_base::common_config(config, 33.333_MHz_XTAL); + + DS1397(config, m_rtc, 32'768); + m_rtc->set_epoch(1990); + input_merger_any_high_device &spc_irq(INPUT_MERGER_ANY_HIGH(config, "spc_irq")); - spc_irq.output_handler().set(&luna_88k_state::irq<0, 3>, "irq0,3"); + spc_irq.output_handler().set(&luna88k2_state::irq<0, 3>, "irq0,3"); NSCSI_BUS(config, "scsi0"); NSCSI_CONNECTOR(config, "scsi0:0", scsi_devices, nullptr); @@ -497,38 +577,20 @@ void luna_88k_state::luna88k2(machine_config &config) }); input_merger_any_low_device &net_irq(INPUT_MERGER_ANY_LOW(config, "net_irq")); - net_irq.output_handler().set(&luna_88k_state::irq<0, 4>, "irq0,4"); + net_irq.output_handler().set(&luna88k2_state::irq<0, 4>, "irq0,4"); AM7990(config, m_net[0], 40_MHz_XTAL / 4); m_net[0]->intr_out().set(net_irq, FUNC(input_merger_any_low_device::in_w<0>)); - m_net[0]->dma_in().set(FUNC(luna_88k_state::net_r)); - m_net[0]->dma_out().set(FUNC(luna_88k_state::net_w)); + m_net[0]->dma_in().set(FUNC(luna88k2_state::net_r)); + m_net[0]->dma_out().set(FUNC(luna88k2_state::net_w)); AM7990(config, m_net[1], 40_MHz_XTAL / 4); m_net[1]->intr_out().set(net_irq, FUNC(input_merger_any_low_device::in_w<1>)); - m_net[1]->dma_in().set(FUNC(luna_88k_state::net_r)); - m_net[1]->dma_out().set(FUNC(luna_88k_state::net_w)); - - // TODO: crt timing control by HD6445CP4 - screen_device &crt(SCREEN(config, "crt", SCREEN_TYPE_RASTER)); - crt.set_raw(108'992'000, 2048, 0, 1280, 1024, 0, 1024); - crt.set_screen_update(FUNC(luna_88k_state::screen_update)); - - BT458(config, m_ramdac, 108'992'000); - - KS0066_F00(config, m_lcdc, 250'000); - m_lcdc->set_function_set_at_any_time(true); - m_lcdc->set_lcd_size(2, 16); - - palette_device &palette(PALETTE(config, "palette", palette_device::MONOCHROME)); - - screen_device &lcd(SCREEN(config, "lcd", SCREEN_TYPE_LCD)); - lcd.set_raw(192'000, 40 * 6, 0, 16 * 6, 2 * 8, 0, 2 * 8); - lcd.set_screen_update(m_lcdc, FUNC(ks0066_f00_device::screen_update)); - lcd.set_palette(palette); + m_net[1]->dma_in().set(FUNC(luna88k2_state::net_r)); + m_net[1]->dma_out().set(FUNC(luna88k2_state::net_w)); } -u32 luna_88k_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, rectangle const &cliprect) +u32 luna_88k_state_base::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, rectangle const &cliprect) { for (int y = screen.visible_area().min_y; y <= screen.visible_area().max_y; y++) { @@ -565,7 +627,7 @@ u32 luna_88k_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, r return 0; } -void luna_88k_state::plane_common_w(offs_t offset, u32 data, u32 mem_mask) +void luna_88k_state_base::plane_common_w(offs_t offset, u32 data, u32 mem_mask) { if (BIT(m_plane_active, 0)) plane_w<0>(offset, data, mem_mask); if (BIT(m_plane_active, 1)) plane_w<1>(offset, data, mem_mask); @@ -577,7 +639,7 @@ void luna_88k_state::plane_common_w(offs_t offset, u32 data, u32 mem_mask) if (BIT(m_plane_active, 7)) plane_w<7>(offset, data, mem_mask); } -void luna_88k_state::logic_common_w(offs_t offset, u32 data) +void luna_88k_state_base::logic_common_w(offs_t offset, u32 data) { LOG("logic_common func 0x%x mask 0x%08x\n", offset & 0xf, data); @@ -591,12 +653,12 @@ void luna_88k_state::logic_common_w(offs_t offset, u32 data) if (BIT(m_plane_active, 7)) logic_w<7>(offset, data); } -template u32 luna_88k_state::plane_r(offs_t offset, u32 data) +template u32 luna_88k_state_base::plane_r(offs_t offset, u32 data) { return m_vram[Plane * 0x1'0000 + offset]; } -template void luna_88k_state::plane_w(offs_t offset, u32 data, u32 mem_mask) +template void luna_88k_state_base::plane_w(offs_t offset, u32 data, u32 mem_mask) { u32 const memory = m_vram[Plane * 0x1'0000 + offset]; @@ -626,7 +688,7 @@ template void luna_88k_state::plane_w(offs_t offset, u32 data, COMBINE_DATA(&m_vram[Plane * 0x1'0000 + offset]); } -template void luna_88k_state::logic_w(offs_t offset, u32 data) +template void luna_88k_state_base::logic_w(offs_t offset, u32 data) { if (VERBOSE & LOG_GENERAL) { @@ -643,7 +705,7 @@ template void luna_88k_state::logic_w(offs_t offset, u32 data) m_plane_mask[Plane] = data; } -u32 luna_88k_state::irq_ctl_r(offs_t offset) +u32 luna_88k_state_base::irq_ctl_r(offs_t offset) { u32 data = u32(m_irq_mask[offset]) << 18; @@ -658,14 +720,14 @@ u32 luna_88k_state::irq_ctl_r(offs_t offset) return data; } -void luna_88k_state::irq_ctl_w(offs_t offset, u32 data) +void luna_88k_state_base::irq_ctl_w(offs_t offset, u32 data) { m_irq_mask[offset] = BIT(data, 26, 6); irq_check(); } -void luna_88k_state::irq(unsigned cpu, unsigned interrupt, int state) +void luna_88k_state_base::irq(unsigned cpu, unsigned interrupt, int state) { if (state) m_irq_active[cpu] |= (1U << interrupt); @@ -675,7 +737,7 @@ void luna_88k_state::irq(unsigned cpu, unsigned interrupt, int state) irq_check(); } -void luna_88k_state::irq_check() +void luna_88k_state_base::irq_check() { bool irq_state = m_irq_active[0] & (0x80 | m_irq_mask[0] << 1); @@ -687,6 +749,64 @@ void luna_88k_state::irq_check() } static INPUT_PORTS_START(luna88k) + PORT_START("SW1") + PORT_DIPNAME(0x80, 0x80, "Start") PORT_DIPLOCATION("SW1:1") + PORT_DIPSETTING(0x00, "Monitor") // single-user + PORT_DIPSETTING(0x80, "Autoboot") // multi-user + PORT_DIPNAME(0x40, 0x40, "Console") PORT_DIPLOCATION("SW1:2") + PORT_DIPSETTING(0x00, "Serial") + PORT_DIPSETTING(0x40, "Graphics") + PORT_DIPNAME(0x20, 0x00, "SW1#3") PORT_DIPLOCATION("SW1:3") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x20, DEF_STR(On)) + PORT_DIPNAME(0x10, 0x00, "SW1#4") PORT_DIPLOCATION("SW1:4") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x10, DEF_STR(On)) + PORT_DIPNAME(0x08, 0x00, "SW1#5") PORT_DIPLOCATION("SW1:5") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x08, DEF_STR(On)) + PORT_DIPNAME(0x04, 0x00, "SW1#6") PORT_DIPLOCATION("SW1:6") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x04, DEF_STR(On)) + PORT_DIPNAME(0x02, 0x00, "SW1#7") PORT_DIPLOCATION("SW1:7") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x02, DEF_STR(On)) + PORT_DIPNAME(0x01, 0x01, "Mode") PORT_DIPLOCATION("SW1:8") + PORT_DIPSETTING(0x00, "Diagnostic") + PORT_DIPSETTING(0x01, "Normal") + + // user-defined switches + PORT_START("SW2") + PORT_DIPNAME(0x80, 0x00, "SW2#1") PORT_DIPLOCATION("SW2:1") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x80, DEF_STR(On)) + PORT_DIPNAME(0x40, 0x00, "SW2#2") PORT_DIPLOCATION("SW2:2") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x40, DEF_STR(On)) + PORT_DIPNAME(0x20, 0x00, "SW2#3") PORT_DIPLOCATION("SW2:3") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x20, DEF_STR(On)) + PORT_DIPNAME(0x10, 0x00, "SW2#4") PORT_DIPLOCATION("SW2:4") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x10, DEF_STR(On)) + PORT_DIPNAME(0x08, 0x00, "SW2#5") PORT_DIPLOCATION("SW2:5") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x08, DEF_STR(On)) + PORT_DIPNAME(0x04, 0x00, "SW2#6") PORT_DIPLOCATION("SW2:6") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x04, DEF_STR(On)) + PORT_DIPNAME(0x02, 0x00, "SW2#7") PORT_DIPLOCATION("SW2:7") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x02, DEF_STR(On)) + PORT_DIPNAME(0x01, 0x00, "SW2#8") PORT_DIPLOCATION("SW2:8") + PORT_DIPSETTING(0x00, DEF_STR(Off)) + PORT_DIPSETTING(0x01, DEF_STR(On)) + + PORT_START("ABORT") + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_NAME("Abort") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, luna_88k_state_base, abort, 0) +INPUT_PORTS_END + +static INPUT_PORTS_START(luna88k2) PORT_START("SW1") PORT_DIPNAME(0x80, 0x80, "Start") PORT_DIPLOCATION("SW1:!1") PORT_DIPSETTING(0x00, "Monitor") // single-user @@ -741,9 +861,45 @@ static INPUT_PORTS_START(luna88k) PORT_DIPSETTING(0x01, DEF_STR(On)) PORT_START("ABORT") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_NAME("Abort") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, luna_88k_state, abort, 0) + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_NAME("Abort") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHANGED_MEMBER(DEVICE_SELF, luna_88k_state_base, abort, 0) INPUT_PORTS_END +ROM_START(luna88k) + // 2 x 27C1024 + ROM_REGION32_BE(0x40000, "eprom", 0) + ROM_SYSTEM_BIOS(0, "l122", "ROM Version 1.22") + ROMX_LOAD("l122hi.ic92", 0x00000, 0x20000, CRC(4cdccd8f) SHA1(e2503fa2cfd4a17a881562315b5bd8f46f028186), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(0)) + ROMX_LOAD("l122lo.ic102", 0x00002, 0x20000, CRC(992b3f32) SHA1(57a7150eabf46e6aa324f9d0b55b792154b6f61f), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(0)) + + ROM_SYSTEM_BIOS(1, "l110", "ROM Version 1.10") + ROMX_LOAD("l110hi.ic92", 0x00000, 0x20000, CRC(9f0c2d37) SHA1(c7ac5d8b5995958bf91ecd2ea0b669c43a224fec), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(1)) + ROMX_LOAD("l110lo.ic102", 0x00002, 0x20000, CRC(61f5604e) SHA1(6a835c562a18a4d527c2f8ea85a7f94d56362f8a), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(1)) + + ROM_SYSTEM_BIOS(2, "l103", "ROM Version 1.03") + ROMX_LOAD("l103hi.ic92", 0x00000, 0x20000, CRC(cb862bc9) SHA1(a581b96f52eebf81e911f61694e487d46cc0b8ed), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(2)) + ROMX_LOAD("l103lo.ic102", 0x00002, 0x20000, CRC(1a004082) SHA1(c09218ba8b60f44ef9e7e59b7ffacef5fccb0667), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(2)) + + ROM_SYSTEM_BIOS(3, "l006", "L006") + ROMX_LOAD("l006hi.ic92", 0x00000, 0x20000, CRC(50d0bedb) SHA1(9dc8501a724347f068684c4bc0cf8a5f2505db59), ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(3)) + ROMX_LOAD("l006lo.ic102", 0x00002, 0x20000, CRC(f9d3647c) SHA1(9b5c105c5bd57bb4018b679634d051d6052e6428) BAD_DUMP, ROM_GROUPWORD | ROM_REVERSE | ROM_SKIP(2) | ROM_BIOS(3)) + + /* + * This PROM contains the Ethernet MAC address stored in the upper 4 bits + * of each byte. The content decodes to nul-terminated ASCII string and a + * checkum: + * + * ENADDR=00000Axxxxxx + * + * This hash matches content hand-crafted to assign ficticious station + * address 00:00:0a:12:34:56. + */ + ROM_REGION32_BE(0x400, "fuserom", ROMREGION_ERASEFF) + ROM_LOAD32_BYTE("fuserom.ic132", 0x000, 0x100, CRC(29704768) SHA1(09f8e5dc13fa9e42a268f6d3c036e8f485e41d60)) + + ROM_REGION(0x4000, "iop", 0) + ROM_LOAD("hd647180x.ic13", 0x0000, 0x4000, NO_DUMP) // HD647180X0FS6 +ROM_END + ROM_START(luna88k2) ROM_REGION32_BE(0x40000, "eprom", 0) ROM_LOAD32_WORD_SWAP("7187__high__1.37.bin", 0x00000, 0x20000, CRC(a7515231) SHA1(86b3e42a8df6fa33cf68f372f4053b240c8cc4e2)) // HN27C1024HCC-85 @@ -785,5 +941,6 @@ ROM_END } // anonymous namespace -/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ -COMP(1992?, luna88k2, 0, 0, luna88k2, luna88k, luna_88k_state, init, "Omron", u8"Luna 88K²", 0) +/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ +COMP(1991?, luna88k, 0, 0, luna88k, luna88k, luna88k_state, init, "Omron", "Luna 88K", 0) +COMP(1992?, luna88k2, 0, 0, luna88k2, luna88k2, luna88k2_state, init, "Omron", u8"Luna 88K²", 0) -- cgit v1.2.3