From ec6b3d2b5542b5b02339d066b35f7818bd5dbb57 Mon Sep 17 00:00:00 2001 From: 987123879113 <63495610+987123879113@users.noreply.github.com> Date: Sat, 1 Apr 2023 03:39:02 +0900 Subject: namcos10: Refactored driver, and implemented MEM(M) and MEM(N) boards. (#11053) * machine/smartmed.cpp, machine/nandflash.cpp: Separated NAND Flash from smartmed. * sound/spu.cpp: Calculate tables based on clock speed. * machine/intelfsh.cpp: Added Intel 28F640J5 device. * namco/namcos10.cpp: Refactored driver, and implemented MEM(M) and MEM(N) boards. * namco/namcos10.cpp: Fixed parenting of Mr. Driller 2, and renamed Kono e Tako. --- scripts/src/machine.lua | 12 + src/devices/machine/intelfsh.cpp | 81 +- src/devices/machine/intelfsh.h | 11 + src/devices/machine/nandflash.cpp | 606 ++++++++++++ src/devices/machine/nandflash.h | 150 +++ src/devices/machine/smartmed.cpp | 488 +--------- src/devices/machine/smartmed.h | 185 +--- src/devices/sound/spu.cpp | 15 +- src/devices/sound/spu.h | 49 +- src/devices/sound/spu_tables.cpp | 838 ++++++++--------- src/mame/eolith/ghosteo.cpp | 7 +- src/mame/mame.lst | 10 +- src/mame/misc/crospuzl.cpp | 3 +- src/mame/misc/hapyfish.cpp | 12 +- src/mame/namco/namcos10.cpp | 1841 ++++++++++++++++++++++++++----------- src/mame/palm/palmz22.cpp | 9 +- src/mame/skeleton/mini2440.cpp | 8 +- 17 files changed, 2640 insertions(+), 1685 deletions(-) create mode 100644 src/devices/machine/nandflash.cpp create mode 100644 src/devices/machine/nandflash.h diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua index d77e3f27042..35b191e8303 100644 --- a/scripts/src/machine.lua +++ b/scripts/src/machine.lua @@ -2653,6 +2653,18 @@ if (MACHINES["MYB3K_KEYBOARD"]~=null) then } end +--------------------------------------------------- +-- +--@src/devices/machine/nandflash.h,MACHINES["NANDFLASH"] = true +--------------------------------------------------- + +if (MACHINES["NANDFLASH"]~=null) then + files { + MAME_DIR .. "src/devices/machine/nandflash.cpp", + MAME_DIR .. "src/devices/machine/nandflash.h", + } +end + --------------------------------------------------- -- --@src/devices/machine/nmc9306.h,MACHINES["NMC9306"] = true diff --git a/src/devices/machine/intelfsh.cpp b/src/devices/machine/intelfsh.cpp index 1bd9308bba8..5ae298c83fc 100644 --- a/src/devices/machine/intelfsh.cpp +++ b/src/devices/machine/intelfsh.cpp @@ -38,7 +38,9 @@ enum FM_ERASEAMD4, // part 4 of AMD erase sequence FM_BYTEPROGRAM, FM_BANKSELECT, - FM_WRITEPAGEATMEL + FM_WRITEPAGEATMEL, + FM_WRITEBUFFER1, // part 1 of write to buffer sequence + FM_WRITEBUFFER2, // part 2 of write to buffer sequence }; @@ -117,6 +119,7 @@ DEFINE_DEVICE_TYPE(SHARP_LH28F320BF, sharp_lh28f320bf_device, "sharp_l DEFINE_DEVICE_TYPE(INTEL_28F320J3D, intel_28f320j3d_device, "intel_28f320j3d", "Intel 28F320J3D Flash") DEFINE_DEVICE_TYPE(SPANSION_S29GL064S, spansion_s29gl064s_device, "spansion_s29gl064s", "Spansion / Cypress S29GL064S Flash") DEFINE_DEVICE_TYPE(INTEL_28F320J5, intel_28f320j5_device, "intel_28f320j5", "Intel 28F320J5 Flash") +DEFINE_DEVICE_TYPE(INTEL_28F640J5, intel_28f640j5_device, "intel_28f640j5", "Intel 28F640J5 Flash") DEFINE_DEVICE_TYPE(SST_39VF400A, sst_39vf400a_device, "sst_39vf400a", "SST 39VF400A Flash") @@ -286,6 +289,8 @@ intel_28f320j5_device::intel_28f320j5_device(const machine_config &mconfig, cons // m_sector_is_4k = true; 128kb? } +intel_28f640j5_device::intel_28f640j5_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : intelfsh16_device(mconfig, INTEL_28F640J5, tag, owner, clock, 0x800000, MFG_INTEL, 0x15) { } sst_39vf400a_device::sst_39vf400a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : intelfsh16_device(mconfig, SST_39VF400A, tag, owner, clock, 0x80000, MFG_SST, 0xd6) { m_sector_is_4k = true; } @@ -415,8 +420,12 @@ uint32_t intelfsh_device::read_full(uint32_t address) } break; case FM_READSTATUS: + case FM_WRITEBUFFER2: data = m_status; break; + case FM_WRITEBUFFER1: + data = 0x80; // extended status register for write buffer flag + break; case FM_READAMDID3: if ((m_maker_id == MFG_FUJITSU && m_device_id == 0x35) || (m_maker_id == MFG_AMD && m_device_id == 0x3b)) { @@ -567,6 +576,13 @@ void intelfsh_device::write_full(uint32_t address, uint32_t data) m_flash_mode = FM_READAMDID1; } break; + case 0xe8: + // Write to buffer (Intel StrataFlash series) + if ( m_maker_id == MFG_INTEL && m_device_id >= 0x14 && m_device_id <= 0x16 ) + m_flash_mode = FM_WRITEBUFFER1; + else + logerror( "Unknown flash mode byte %x\n", data & 0xff ); + break; default: logerror( "Unknown flash mode byte %x\n", data & 0xff ); break; @@ -982,7 +998,68 @@ void intelfsh_device::write_full(uint32_t address, uint32_t data) logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff ); break; } - m_flash_mode = FM_NORMAL; + m_flash_mode = FM_READSTATUS; + break; + case FM_WRITEBUFFER1: + // Datasheets don't specify what happens when the word count is outside of + // the valid range so clamp and pray + if ( m_bits == 16 ) + m_write_buffer_count = std::min(data, 0xf) + 1; + else + m_write_buffer_count = std::min(data, 0x1f) + 1; + + m_status = 0x80; + m_flash_mode = FM_WRITEBUFFER2; + m_byte_count = 0; + break; + case FM_WRITEBUFFER2: + { + if ( m_byte_count < m_write_buffer_count ) + { + if ( m_byte_count == 0 ) + m_write_buffer_start_address = address; + + if ( address >= m_write_buffer_start_address + m_write_buffer_count ) + { + // All subsequent addresses must lie within the start address plus the count + // Set error bits and abort + m_status = (1 << 4) | (1 << 5); + m_flash_mode = FM_READSTATUS; + } + else + { + if ( m_bits == 8 ) + { + m_write_buffer[m_byte_count] = data; + } + else + { + m_write_buffer[m_byte_count * 2] = data >> 8; + m_write_buffer[m_byte_count * 2 + 1] = data; + } + + m_byte_count++; + } + } + else + { + if ( ( data & 0xff ) == 0xd0 ) + { + // Confirmation byte received, commit buffered data + uint32_t base = m_write_buffer_start_address * ((m_bits == 16) ? 2 : 1); + uint32_t len = m_write_buffer_count * ((m_bits == 16) ? 2 : 1); + memcpy(&m_data[base], m_write_buffer, len); + m_status = 0x80; + } + else + { + // Invalid Command/Sequence, set error bits and abort + m_status = (1 << 4) | (1 << 5); + } + + m_flash_mode = FM_READSTATUS; + } + } break; case FM_BANKSELECT: m_bank = data & 0xff; diff --git a/src/devices/machine/intelfsh.h b/src/devices/machine/intelfsh.h index ee6a54fb829..e3fc991324b 100644 --- a/src/devices/machine/intelfsh.h +++ b/src/devices/machine/intelfsh.h @@ -56,6 +56,10 @@ protected: emu_timer * m_timer; int32_t m_bank; uint8_t m_byte_count; + + uint8_t m_write_buffer[32]; + uint32_t m_write_buffer_start_address; + uint32_t m_write_buffer_count; }; @@ -315,6 +319,12 @@ public: intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); }; +class intel_28f640j5_device : public intelfsh16_device +{ +public: + intel_28f640j5_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + class sst_39vf400a_device : public intelfsh16_device { public: @@ -379,6 +389,7 @@ DECLARE_DEVICE_TYPE(SPANSION_S29GL064S, spansion_s29gl064s_device) DECLARE_DEVICE_TYPE(SHARP_LH28F320BF, sharp_lh28f320bf_device) DECLARE_DEVICE_TYPE(INTEL_28F320J3D, intel_28f320j3d_device) DECLARE_DEVICE_TYPE(INTEL_28F320J5, intel_28f320j5_device) +DECLARE_DEVICE_TYPE(INTEL_28F640J5, intel_28f640j5_device) DECLARE_DEVICE_TYPE(SST_39VF400A, sst_39vf400a_device) DECLARE_DEVICE_TYPE(ATMEL_49F4096, atmel_49f4096_device) DECLARE_DEVICE_TYPE(CAT28F020, cat28f020_device) diff --git a/src/devices/machine/nandflash.cpp b/src/devices/machine/nandflash.cpp new file mode 100644 index 00000000000..559816e9101 --- /dev/null +++ b/src/devices/machine/nandflash.cpp @@ -0,0 +1,606 @@ +// license:BSD-3-Clause +// copyright-holders:Raphael Nabet +/* + NAND flash emulation + + References: + Datasheets for various SmartMedia chips were found on Samsung and Toshiba's + sites (http://www.toshiba.com/taec and + http://www.samsung.com/Products/Semiconductor/Flash/FlashCard/SmartMedia) + + Raphael Nabet 2004 +*/ + +#include "emu.h" +#include "nandflash.h" + +#include "formats/imageutl.h" + +ALLOW_SAVE_TYPE(nand_device::sm_mode_t) +ALLOW_SAVE_TYPE(nand_device::pointer_sm_mode_t) + +DEFINE_DEVICE_TYPE(NAND, nand_device, "nand", "NAND Flash Memory") +DEFINE_DEVICE_TYPE(SAMSUNG_K9F5608U0D, samsung_k9f5608u0d_device, "samsung_k9f5608u0d", "Samsung K9F5608U0D") +DEFINE_DEVICE_TYPE(SAMSUNG_K9F5608U0DJ, samsung_k9f5608u0dj_device, "samsung_k9f5608u0dj", "Samsung K9F5608U0D-J") +DEFINE_DEVICE_TYPE(SAMSUNG_K9F5608U0B, samsung_k9f5608u0b_device, "samsung_k9f5608u0b", "Samsung K9F5608U0B") +DEFINE_DEVICE_TYPE(SAMSUNG_K9F2808U0B, samsung_k9f2808u0b_device, "samsung_k9f2808u0b", "Samsung K9F2808U0B") +DEFINE_DEVICE_TYPE(SAMSUNG_K9F1G08U0B, samsung_k9f1g08u0b_device, "samsung_k9f1g08u0b", "Samsung K9F1G08U0B") +DEFINE_DEVICE_TYPE(SAMSUNG_K9LAG08U0M, samsung_k9lag08u0m_device, "samsung_k9lag08u0m", "Samsung K9LAG08U0M") + +nand_device::nand_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, NAND, tag, owner, clock) +{ +} + +nand_device::nand_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock), + device_nvram_interface(mconfig, *this), + m_region(*this, DEVICE_SELF), + m_page_data_size(0), + m_page_total_size(0), + m_num_pages(0), + m_log2_pages_per_block(0), + m_pagereg(nullptr), + m_id_len(0), + m_col_address_cycles(0), + m_row_address_cycles(0), + m_sequential_row_read(0), + m_write_rnb(*this) +{ + memset(m_id, 0, sizeof(m_id)); +} + +samsung_k9f5608u0d_device::samsung_k9f5608u0d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9F5608U0D, tag, owner, clock) +{ + m_id_len = 2; + m_id[0] = 0xec; + m_id[1] = 0x75; + m_page_data_size = 512; + m_page_total_size = 512 + 16; + m_log2_pages_per_block = compute_log2(32); + m_num_pages = 32 * 2048; + m_col_address_cycles = 1; + m_row_address_cycles = 2; + m_sequential_row_read = 1; +} + +samsung_k9f5608u0dj_device::samsung_k9f5608u0dj_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9F5608U0DJ, tag, owner, clock) +{ + m_id_len = 2; + m_id[0] = 0xec; + m_id[1] = 0x75; + m_page_data_size = 512; + m_page_total_size = 512 + 16; + m_log2_pages_per_block = compute_log2(32); + m_num_pages = 32 * 2048; + m_col_address_cycles = 1; + m_row_address_cycles = 2; + m_sequential_row_read = 0; +} + +samsung_k9f5608u0b_device::samsung_k9f5608u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9F5608U0B, tag, owner, clock) +{ + m_id_len = 2; + m_id[0] = 0xec; + m_id[1] = 0x75; + m_page_data_size = 512; + m_page_total_size = 512 + 16; + m_log2_pages_per_block = compute_log2(32); + m_num_pages = 32 * 2048; + m_col_address_cycles = 1; + m_row_address_cycles = 2; + m_sequential_row_read = 0; +} + +samsung_k9f2808u0b_device::samsung_k9f2808u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9F2808U0B, tag, owner, clock) +{ + m_id_len = 2; + m_id[0] = 0xec; + m_id[1] = 0x73; + m_page_data_size = 512; + m_page_total_size = 512 + 16; + m_log2_pages_per_block = compute_log2(32); + m_num_pages = 32 * 1024; + m_col_address_cycles = 1; + m_row_address_cycles = 2; + m_sequential_row_read = 0; +} + +samsung_k9f1g08u0b_device::samsung_k9f1g08u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9F1G08U0B, tag, owner, clock) +{ + m_id_len = 5; + m_id[0] = 0xec; + m_id[1] = 0xf1; + m_id[2] = 0x00; + m_id[3] = 0x95; + m_id[4] = 0x40; + m_page_data_size = 2048; + m_page_total_size = 2048 + 64; + m_log2_pages_per_block = compute_log2(64); + m_num_pages = 64 * 1024; + m_col_address_cycles = 2; + m_row_address_cycles = 2; + m_sequential_row_read = 0; +} + +samsung_k9lag08u0m_device::samsung_k9lag08u0m_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : nand_device(mconfig, SAMSUNG_K9LAG08U0M, tag, owner, clock) +{ + m_id_len = 5; + m_id[0] = 0xec; + m_id[1] = 0xd5; + m_id[2] = 0x55; + m_id[3] = 0x25; + m_id[4] = 0x68; + m_page_data_size = 2048; + m_page_total_size = 2048 + 64; + m_log2_pages_per_block = compute_log2(128); + m_num_pages = 128 * 8192; + m_col_address_cycles = 2; + m_row_address_cycles = 3; + m_sequential_row_read = 0; +} + +void nand_device::device_start() +{ + m_data_uid_ptr = nullptr; // smartmed cruft + m_feeprom_data = std::make_unique(m_page_total_size * m_num_pages); + m_pagereg = std::make_unique(m_page_total_size); + + save_item(NAME(m_mode)); + save_item(NAME(m_pointer_mode)); + save_item(NAME(m_page_addr)); + save_item(NAME(m_byte_addr)); + save_item(NAME(m_status)); + save_item(NAME(m_accumulated_status)); + save_item(NAME(m_mode_3065)); +} + +void nand_device::device_reset() +{ + m_mode = SM_M_INIT; + m_pointer_mode = SM_PM_A; + m_page_addr = 0; + m_byte_addr = 0; + m_accumulated_status = 0; + m_mode_3065 = false; + m_status = 0xc0; + + std::fill_n(m_pagereg.get(), m_page_total_size, 0); +} + +void nand_device::device_resolve_objects() +{ + m_write_rnb.resolve_safe(); +} + +void nand_device::nvram_default() +{ + if (m_region.found()) + { + // Copy from region if it exists + uint32_t bytes = m_region->bytes(); + + if (bytes > m_page_total_size * m_num_pages) + bytes = m_page_total_size * m_num_pages; + + for (offs_t offs = 0; offs < bytes; offs++) + m_feeprom_data[offs] = m_region->as_u8(offs); + + return; + } + + memset(&m_feeprom_data[0], 0xff, m_page_total_size * m_num_pages); +} + +bool nand_device::nvram_read(util::read_stream &file) +{ + size_t actual; + uint32_t size = m_page_total_size * m_num_pages; + return !file.read(&m_feeprom_data[0], size, actual) && actual == size; +} + +bool nand_device::nvram_write(util::write_stream &file) +{ + size_t actual; + uint32_t size = m_page_total_size * m_num_pages; + return !file.write(&m_feeprom_data[0], size, actual) && actual == size; +} + +int nand_device::is_present() +{ + return m_num_pages != 0; +} + +int nand_device::is_protected() +{ + return (m_status & 0x80) == 0; +} + +int nand_device::is_busy() +{ + return (m_status & 0x40) == 0; +} + +void nand_device::command_w(uint8_t data) +{ + if (!is_present()) + return; + + switch (data) + { + case 0xff: // Reset + m_mode = SM_M_INIT; + m_pointer_mode = SM_PM_A; + m_status = (m_status & 0x80) | 0x40; + m_accumulated_status = 0; + m_mode_3065 = false; + + m_write_rnb(0); + m_write_rnb(1); + break; + case 0x00: // Read (1st cycle) + m_mode = SM_M_READ; + m_pointer_mode = SM_PM_A; + m_page_addr = 0; + m_addr_load_ptr = 0; + break; + case 0x01: + if (m_page_data_size != 512) + { + logerror("nandflash: unsupported upper data field select (256-byte pages)\n"); + m_mode = SM_M_INIT; + } + else + { + m_mode = SM_M_READ; + m_pointer_mode = SM_PM_B; + m_page_addr = 0; + m_addr_load_ptr = 0; + } + break; + case 0x50: + if (m_page_data_size > 512) + { + logerror("nandflash: unsupported spare area select\n"); + m_mode = SM_M_INIT; + } + else + { + m_mode = SM_M_READ; + m_pointer_mode = SM_PM_C; + m_page_addr = 0; + m_addr_load_ptr = 0; + } + break; + case 0x80: // Page Program (1st cycle) + m_mode = SM_M_PROGRAM; + m_page_addr = 0; + m_addr_load_ptr = 0; + m_program_byte_count = 0; + memset(m_pagereg.get(), 0xff, m_page_total_size); + break; + case 0x10: // Page Program (2nd cycle) + case 0x15: + if ((m_mode != SM_M_PROGRAM) && (m_mode != SM_M_RANDOM_DATA_INPUT)) + { + logerror("nandflash: illegal page program confirm command\n"); + m_mode = SM_M_INIT; + } + else + { + m_status = (m_status & 0x80) | m_accumulated_status; + // logerror( "nandflash: program, page_addr %08X\n", m_page_addr); + for (int i = 0; i < m_page_total_size; i++) + m_feeprom_data[m_page_addr * m_page_total_size + i] &= m_pagereg[i]; + m_status |= 0x40; + if (data == 0x15) + m_accumulated_status = m_status & 0x1f; + else + m_accumulated_status = 0; + m_mode = SM_M_INIT; + + m_write_rnb(0); + m_write_rnb(1); + } + break; + // case 0x11: + // break; + case 0x60: // Block Erase (1st cycle) + m_mode = SM_M_ERASE; + m_page_addr = 0; + m_addr_load_ptr = 0; + break; + case 0xd0: // Block Erase (2nd cycle) + if (m_mode != SM_M_ERASE) + { + logerror("nandflash: illegal block erase confirm command\n"); + m_mode = SM_M_INIT; + } + else + { + m_status &= 0x80; + memset(m_feeprom_data.get() + ((m_page_addr & (-1 << m_log2_pages_per_block)) * m_page_total_size), 0xFF, (size_t)(1 << m_log2_pages_per_block) * m_page_total_size); + // logerror( "nandflash: erase, page_addr %08X, offset %08X, length %08X\n", m_page_addr, (m_page_addr & (-1 << m_log2_pages_per_block)) * m_page_total_size, (1 << m_log2_pages_per_block) * m_page_total_size); + m_status |= 0x40; + m_mode = SM_M_INIT; + if (m_pointer_mode == SM_PM_B) + m_pointer_mode = SM_PM_A; + + m_write_rnb(0); + m_write_rnb(1); + } + break; + case 0x70: // Read Status + m_mode = SM_M_READSTATUS; + break; + // case 0x71: + // break; + case 0x90: // Read ID + m_mode = SM_M_READID; + m_addr_load_ptr = 0; + break; + // case 0x91: + // break; + case 0x30: // Read (2nd cycle) + if (m_col_address_cycles == 1) + { + m_mode = SM_M_30; + } + else + { + if (m_mode != SM_M_READ) + { + logerror("nandflash: illegal read 2nd cycle command\n"); + m_mode = SM_M_INIT; + } + else if (m_addr_load_ptr < (m_col_address_cycles + m_row_address_cycles)) + { + logerror("nandflash: read 2nd cycle, not enough address cycles (actual: %d, expected: %d)\n", m_addr_load_ptr, m_col_address_cycles + m_row_address_cycles); + m_mode = SM_M_INIT; + } + else + { + m_write_rnb(0); + m_write_rnb(1); + } + } + break; + case 0x65: + if (m_mode != SM_M_30) + { + logerror("nandflash: unexpected address port write\n"); + m_mode = SM_M_INIT; + } + else + { + m_mode_3065 = true; + } + break; + case 0x05: // Random Data Output (1st cycle) + if ((m_mode != SM_M_READ) && (m_mode != SM_M_RANDOM_DATA_OUTPUT)) + { + logerror("nandflash: illegal random data output command\n"); + m_mode = SM_M_INIT; + } + else + { + m_mode = SM_M_RANDOM_DATA_OUTPUT; + m_addr_load_ptr = 0; + } + break; + case 0xE0: // Random Data Output (2nd cycle) + if (m_mode != SM_M_RANDOM_DATA_OUTPUT) + { + logerror("nandflash: illegal random data output confirm command\n"); + m_mode = SM_M_INIT; + } + else + { + // do nothing + } + break; + case 0x85: // Random Data Input + if ((m_mode != SM_M_PROGRAM) && (m_mode != SM_M_RANDOM_DATA_INPUT)) + { + logerror("nandflash: illegal random data input command\n"); + m_mode = SM_M_INIT; + } + else + { + m_mode = SM_M_RANDOM_DATA_INPUT; + m_addr_load_ptr = 0; + m_program_byte_count = 0; + } + break; + default: + logerror("nandflash: unsupported command 0x%02x\n", data); + m_mode = SM_M_INIT; + break; + } +} + +void nand_device::address_w(uint8_t data) +{ + if (!is_present()) + return; + + switch (m_mode) + { + case SM_M_INIT: + logerror("nandflash: unexpected address port write\n"); + break; + case SM_M_READ: + case SM_M_PROGRAM: + if ((m_addr_load_ptr == 0) && (m_col_address_cycles == 1)) + { + switch (m_pointer_mode) + { + case SM_PM_A: + m_byte_addr = data; + break; + case SM_PM_B: + m_byte_addr = data + 256; + m_pointer_mode = SM_PM_A; + break; + case SM_PM_C: + if (!m_mode_3065) + m_byte_addr = (data & 0x0f) + m_page_data_size; + else + m_byte_addr = (data & 0x0f) + 256; + break; + } + } + else + { + if (m_addr_load_ptr < m_col_address_cycles) + { + m_byte_addr &= ~(0xFF << (m_addr_load_ptr * 8)); + m_byte_addr |= (data << (m_addr_load_ptr * 8)); + } + else if (m_addr_load_ptr < m_col_address_cycles + m_row_address_cycles) + { + m_page_addr &= ~(0xFF << ((m_addr_load_ptr - m_col_address_cycles) * 8)); + m_page_addr |= (data << ((m_addr_load_ptr - m_col_address_cycles) * 8)); + } + } + m_addr_load_ptr++; + break; + case SM_M_ERASE: + if (m_addr_load_ptr < m_row_address_cycles) + { + m_page_addr &= ~(0xFF << (m_addr_load_ptr * 8)); + m_page_addr |= (data << (m_addr_load_ptr * 8)); + } + m_addr_load_ptr++; + break; + case SM_M_RANDOM_DATA_INPUT: + case SM_M_RANDOM_DATA_OUTPUT: + if (m_addr_load_ptr < m_col_address_cycles) + { + m_byte_addr &= ~(0xFF << (m_addr_load_ptr * 8)); + m_byte_addr |= (data << (m_addr_load_ptr * 8)); + } + m_addr_load_ptr++; + break; + case SM_M_READSTATUS: + case SM_M_30: + logerror("nandflash: unexpected address port write\n"); + break; + case SM_M_READID: + if (m_addr_load_ptr == 0) + m_byte_addr = data; + m_addr_load_ptr++; + break; + } +} + +uint8_t nand_device::data_r() +{ + uint8_t reply = 0; + if (!is_present()) + return 0; + + switch (m_mode) + { + case SM_M_INIT: + case SM_M_30: + logerror("nandflash: unexpected data port read\n"); + break; + case SM_M_READ: + case SM_M_RANDOM_DATA_OUTPUT: + if (!m_mode_3065) + { + if (m_byte_addr < m_page_total_size) + { + if (m_page_addr < m_num_pages) + reply = m_feeprom_data[m_page_addr * m_page_total_size + m_byte_addr]; + else + reply = 0xff; + } + else + { + reply = 0xFF; + } + } + else + { + if (m_data_uid_ptr != nullptr) + { + // FIXME: this appears to be incorrect, m_data_uid_ptr is a smaller structure of 256*16 + // this code would always result in reading past the buffer + uint32_t addr = m_page_addr * m_page_total_size + m_byte_addr; + if (addr < 256 + 16) + reply = m_data_uid_ptr[addr]; + } + else + { + reply = 0xff; + } + } + m_byte_addr++; + + // "Sequential Row Read is available only on K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P" + if ((m_byte_addr == m_page_total_size) && (m_sequential_row_read != 0)) + { + m_byte_addr = (m_pointer_mode != SM_PM_C) ? 0 : m_page_data_size; + m_page_addr++; + if (m_page_addr == m_num_pages) + m_page_addr = 0; + } + break; + case SM_M_PROGRAM: + case SM_M_RANDOM_DATA_INPUT: + case SM_M_ERASE: + logerror("nandflash: unexpected data port read\n"); + break; + case SM_M_READSTATUS: + reply = m_status & 0xc1; + break; + case SM_M_READID: + if (m_byte_addr < m_id_len) + reply = m_id[m_byte_addr]; + else + reply = 0; + m_byte_addr++; + break; + } + + return reply; +} + +void nand_device::data_w(uint8_t data) +{ + if (!is_present()) + return; + + switch (m_mode) + { + case SM_M_INIT: + case SM_M_READ: + case SM_M_30: + case SM_M_RANDOM_DATA_OUTPUT: + logerror("nandflash: unexpected data port write\n"); + break; + case SM_M_PROGRAM: + case SM_M_RANDOM_DATA_INPUT: + if (m_program_byte_count++ < m_page_total_size) + { + m_pagereg[m_byte_addr] = data; + } + m_byte_addr++; + if (m_byte_addr == m_page_total_size) + m_byte_addr = (m_pointer_mode != SM_PM_C) ? 0 : m_page_data_size; + break; + case SM_M_ERASE: + case SM_M_READSTATUS: + case SM_M_READID: + logerror("nandflash: unexpected data port write\n"); + break; + } +} diff --git a/src/devices/machine/nandflash.h b/src/devices/machine/nandflash.h new file mode 100644 index 00000000000..221216ff3a1 --- /dev/null +++ b/src/devices/machine/nandflash.h @@ -0,0 +1,150 @@ +// license:BSD-3-Clause +// copyright-holders:Raphael Nabet + +#ifndef MAME_MACHINE_NANDFLASH_H +#define MAME_MACHINE_NANDFLASH_H + +#pragma once + +/*************************************************************************** + TYPE DEFINITIONS +***************************************************************************/ + +// ======================> nand_device +class nand_device : public device_t, public device_nvram_interface +{ +public: + // construction/destruction + nand_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + + virtual void device_resolve_objects() override; + + // device_nvram_interface overrides + virtual void nvram_default() override; + virtual bool nvram_read(util::read_stream &file) override; + virtual bool nvram_write(util::write_stream &file) override; + + auto rnb_wr_callback() { return m_write_rnb.bind(); } + + int is_present(); + int is_protected(); + int is_busy(); + + uint8_t data_r(); + void command_w(uint8_t data); + void address_w(uint8_t data); + void data_w(uint8_t data); + +protected: + enum sm_mode_t : uint8_t + { + SM_M_INIT, // initial state + SM_M_READ, // read page data + SM_M_PROGRAM, // program page data + SM_M_ERASE, // erase block data + SM_M_READSTATUS, // read status + SM_M_READID, // read ID + SM_M_30, + SM_M_RANDOM_DATA_INPUT, + SM_M_RANDOM_DATA_OUTPUT + }; + + enum pointer_sm_mode_t : uint8_t + { + SM_PM_A, // accessing first 256-byte half of 512-byte data field + SM_PM_B, // accessing second 256-byte half of 512-byte data field + SM_PM_C // accessing spare field + }; + + nand_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + optional_memory_region m_region; + + uint32_t m_page_data_size; // 256 for a 2MB card, 512 otherwise + uint32_t m_page_total_size; // 264 for a 2MB card, 528 otherwise + uint32_t m_num_pages; // 8192 for a 4MB card, 16184 for 8MB, 32768 for 16MB, + // 65536 for 32MB, 131072 for 64MB, 262144 for 128MB... + // 0 means no card loaded + int32_t m_log2_pages_per_block; // log2 of number of pages per erase block (usually 4 or 5) + + std::unique_ptr m_feeprom_data; // FEEPROM data area + std::unique_ptr m_data_uid_ptr; // TODO: this probably should be contained to smartmed + + sm_mode_t m_mode; // current operation mode + pointer_sm_mode_t m_pointer_mode; // pointer mode + + uint32_t m_page_addr; // page address pointer + uint32_t m_byte_addr; // byte address pointer + uint32_t m_addr_load_ptr; // address load pointer + + uint8_t m_status; // current status + uint8_t m_accumulated_status; // accumulated status + + std::unique_ptr m_pagereg; // page register used by program command + uint8_t m_id[5]; // chip ID + + bool m_mode_3065; + + // Palm Z22 NAND has 512 + 16 byte pages but, for some reason, Palm OS writes 512 + 64 bytes when + // programming a page, so we need to keep track of the number of bytes written so we can ignore the + // last 48 (64 - 16) bytes or else the first 48 bytes get overwritten + uint32_t m_program_byte_count; + + uint32_t m_id_len; + uint32_t m_col_address_cycles; + uint32_t m_row_address_cycles; + uint32_t m_sequential_row_read; + + devcb_write_line m_write_rnb; +}; + +class samsung_k9f5608u0d_device : public nand_device +{ +public: + samsung_k9f5608u0d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +class samsung_k9f5608u0dj_device : public nand_device +{ +public: + samsung_k9f5608u0dj_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +class samsung_k9f5608u0b_device : public nand_device +{ +public: + samsung_k9f5608u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +class samsung_k9f2808u0b_device : public nand_device +{ +public: + samsung_k9f2808u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +class samsung_k9f1g08u0b_device : public nand_device +{ +public: + samsung_k9f1g08u0b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +class samsung_k9lag08u0m_device : public nand_device +{ +public: + samsung_k9lag08u0m_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); +}; + +// device type definition +DECLARE_DEVICE_TYPE(NAND, nand_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F5608U0D, samsung_k9f5608u0d_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F5608U0DJ, samsung_k9f5608u0dj_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F5608U0B, samsung_k9f5608u0b_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F2808U0B, samsung_k9f2808u0b_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F1G08U0B, samsung_k9f1g08u0b_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9LAG08U0M, samsung_k9lag08u0m_device) + +#endif // MAME_MACHINE_NANDFLASH_H diff --git a/src/devices/machine/smartmed.cpp b/src/devices/machine/smartmed.cpp index 27492fd8b31..4ba30d5d442 100644 --- a/src/devices/machine/smartmed.cpp +++ b/src/devices/machine/smartmed.cpp @@ -14,6 +14,7 @@ TODO: * support multi-plane mode? * use HD-format images instead of our experimental custom format? + * better separation of SmartMedia image and NAND flash device Raphael Nabet 2004 */ @@ -37,14 +38,6 @@ inline uint32_t get_UINT32BE(UINT32BE word) return (word.bytes[0] << 24) | (word.bytes[1] << 16) | (word.bytes[2] << 8) | word.bytes[3]; } -[[maybe_unused]] inline void set_UINT32BE(UINT32BE *word, uint32_t data) -{ - word->bytes[0] = (data >> 24) & 0xff; - word->bytes[1] = (data >> 16) & 0xff; - word->bytes[2] = (data >> 8) & 0xff; - word->bytes[3] = data & 0xff; -} - /* SmartMedia image header */ struct SM_disk_image_header { @@ -71,53 +64,6 @@ enum } // anonymous namespace - -DEFINE_DEVICE_TYPE(NAND, nand_device, "nand", "NAND Flash Memory") - -nand_device::nand_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : nand_device(mconfig, NAND, tag, owner, clock) -{ -} - -nand_device::nand_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) - : device_t(mconfig, type, tag, owner, clock) - , m_page_data_size(0) - , m_page_total_size(0) - , m_num_pages(0) - , m_log2_pages_per_block(0) - , m_pagereg(nullptr) - , m_id_len(0) - , m_col_address_cycles(0) - , m_row_address_cycles(0) - , m_sequential_row_read(0) - , m_write_rnb(*this) -{ - memset(m_id, 0, sizeof(m_id)); -} - -/* - Init a SmartMedia image -*/ -void nand_device::device_start() -{ - m_feeprom_data = nullptr; - m_data_uid_ptr = nullptr; - m_mode = SM_M_INIT; - m_pointer_mode = SM_PM_A; - m_page_addr = 0; - m_byte_addr = 0; - m_status = 0xC0; - m_accumulated_status = 0; - m_mp_opcode = 0; - m_mode_3065 = 0; - m_pagereg = std::make_unique(m_page_total_size); - -#ifdef SMARTMEDIA_IMAGE_SAVE - m_image_format = 0; -#endif - m_write_rnb.resolve_safe(); -} - /* Load a SmartMedia image */ @@ -140,8 +86,7 @@ std::error_condition smartmedia_image_device::smartmedia_format_1() m_page_total_size = get_UINT32BE(custom_header.page_total_size); m_num_pages = get_UINT32BE(custom_header.num_pages); m_log2_pages_per_block = get_UINT32BE(custom_header.log2_pages_per_block); - m_feeprom_data_alloc = std::make_unique(m_page_total_size*m_num_pages); - m_feeprom_data = &m_feeprom_data_alloc[0]; + m_feeprom_data = std::make_unique(m_page_total_size*m_num_pages); m_data_uid_ptr = std::make_unique(256 + 16); m_mode = SM_M_INIT; m_pointer_mode = SM_PM_A; @@ -236,8 +181,7 @@ std::error_condition smartmedia_image_device::smartmedia_format_2() return image_error::INVALIDIMAGE; } - m_feeprom_data_alloc = std::make_unique(m_page_total_size*m_num_pages); - m_feeprom_data = &m_feeprom_data_alloc[0]; + m_feeprom_data = std::make_unique(m_page_total_size*m_num_pages); m_data_uid_ptr = std::make_unique(256 + 16); m_mode = SM_M_INIT; m_pointer_mode = SM_PM_A; @@ -351,436 +295,14 @@ void smartmedia_image_device::call_unload() return; } -int nand_device::is_present() -{ - return m_num_pages != 0; -} - -int nand_device::is_protected() -{ - return (m_status & 0x80) == 0; -} - -int nand_device::is_busy() -{ - return (m_status & 0x40) == 0; -} - -void nand_device::set_data_ptr(void *ptr) -{ - m_feeprom_data = (uint8_t *)ptr; -} - -/* - write a byte to SmartMedia command port -*/ -void nand_device::command_w(uint8_t data) -{ - if (!is_present()) - return; - - switch (data) - { - case 0xff: // Reset - m_mode = SM_M_INIT; - m_pointer_mode = SM_PM_A; - m_status = (m_status & 0x80) | 0x40; - m_accumulated_status = 0; - m_mode_3065 = 0; - if (!m_write_rnb.isnull()) - { - m_write_rnb(0); - m_write_rnb(1); - } - break; - case 0x00: // Read (1st cycle) - m_mode = SM_M_READ; - m_pointer_mode = SM_PM_A; - m_page_addr = 0; - m_addr_load_ptr = 0; - break; - case 0x01: - if (m_page_data_size != 512) - { - logerror("smartmedia: unsupported upper data field select (256-byte pages)\n"); - m_mode = SM_M_INIT; - } - else - { - m_mode = SM_M_READ; - m_pointer_mode = SM_PM_B; - m_page_addr = 0; - m_addr_load_ptr = 0; - } - break; - case 0x50: - if (m_page_data_size > 512) - { - logerror("smartmedia: unsupported spare area select\n"); - m_mode = SM_M_INIT; - } - else - { - m_mode = SM_M_READ; - m_pointer_mode = SM_PM_C; - m_page_addr = 0; - m_addr_load_ptr = 0; - } - break; - case 0x80: // Page Program (1st cycle) - m_mode = SM_M_PROGRAM; - m_page_addr = 0; - m_addr_load_ptr = 0; - m_program_byte_count = 0; - memset(m_pagereg.get(), 0xff, m_page_total_size); - break; - case 0x10: // Page Program (2nd cycle) - case 0x15: - if ((m_mode != SM_M_PROGRAM) && (m_mode != SM_M_RANDOM_DATA_INPUT)) - { - logerror("smartmedia: illegal page program confirm command\n"); - m_mode = SM_M_INIT; - } - else - { - m_status = (m_status & 0x80) | m_accumulated_status; - //logerror( "smartmedia: program, page_addr %08X\n", m_page_addr); - for (int i = 0; i < m_page_total_size; i++) - m_feeprom_data[m_page_addr * m_page_total_size + i] &= m_pagereg[i]; - m_status |= 0x40; - if (data == 0x15) - m_accumulated_status = m_status & 0x1f; - else - m_accumulated_status = 0; - m_mode = SM_M_INIT; - if (!m_write_rnb.isnull()) - { - m_write_rnb(0); - m_write_rnb(1); - } - } - break; - //case 0x11: - // break; - case 0x60: // Block Erase (1st cycle) - m_mode = SM_M_ERASE; - m_page_addr = 0; - m_addr_load_ptr = 0; - break; - case 0xd0: // Block Erase (2nd cycle) - if (m_mode != SM_M_ERASE) - { - logerror("smartmedia: illegal block erase confirm command\n"); - m_mode = SM_M_INIT; - } - else - { - m_status &= 0x80; - memset(m_feeprom_data + ((m_page_addr & (-1 << m_log2_pages_per_block)) * m_page_total_size), 0xFF, (size_t)(1 << m_log2_pages_per_block) * m_page_total_size); - //logerror( "smartmedia: erase, page_addr %08X, offset %08X, length %08X\n", m_page_addr, (m_page_addr & (-1 << m_log2_pages_per_block)) * m_page_total_size, (1 << m_log2_pages_per_block) * m_page_total_size); - m_status |= 0x40; - m_mode = SM_M_INIT; - if (m_pointer_mode == SM_PM_B) - m_pointer_mode = SM_PM_A; - if (!m_write_rnb.isnull()) - { - m_write_rnb(0); - m_write_rnb(1); - } - } - break; - case 0x70: // Read Status - m_mode = SM_M_READSTATUS; - break; - //case 0x71: - // break; - case 0x90: // Read ID - m_mode = SM_M_READID; - m_addr_load_ptr = 0; - break; - //case 0x91: - // break; - case 0x30: // Read (2nd cycle) - if (m_col_address_cycles == 1) - { - m_mode = SM_M_30; - } - else - { - if (m_mode != SM_M_READ) - { - logerror("smartmedia: illegal read 2nd cycle command\n"); - m_mode = SM_M_INIT; - } - else if (m_addr_load_ptr < (m_col_address_cycles + m_row_address_cycles)) - { - logerror("smartmedia: read 2nd cycle, not enough address cycles (actual: %d, expected: %d)\n", m_addr_load_ptr, m_col_address_cycles + m_row_address_cycles); - m_mode = SM_M_INIT; - } - else - { - if (!m_write_rnb.isnull()) - { - m_write_rnb(0); - m_write_rnb(1); - } - } - } - break; - case 0x65: - if (m_mode != SM_M_30) - { - logerror("smartmedia: unexpected address port write\n"); - m_mode = SM_M_INIT; - } - else - { - m_mode_3065 = 1; - } - break; - case 0x05: // Random Data Output (1st cycle) - if ((m_mode != SM_M_READ) && (m_mode != SM_M_RANDOM_DATA_OUTPUT)) - { - logerror("smartmedia: illegal random data output command\n"); - m_mode = SM_M_INIT; - } - else - { - m_mode = SM_M_RANDOM_DATA_OUTPUT; - m_addr_load_ptr = 0; - } - break; - case 0xE0: // Random Data Output (2nd cycle) - if (m_mode != SM_M_RANDOM_DATA_OUTPUT) - { - logerror("smartmedia: illegal random data output confirm command\n"); - m_mode = SM_M_INIT; - } - else - { - // do nothing - } - break; - case 0x85: // Random Data Input - if ((m_mode != SM_M_PROGRAM) && (m_mode != SM_M_RANDOM_DATA_INPUT)) - { - logerror("smartmedia: illegal random data input command\n"); - m_mode = SM_M_INIT; - } - else - { - m_mode = SM_M_RANDOM_DATA_INPUT; - m_addr_load_ptr = 0; - m_program_byte_count = 0; - } - break; - default: - logerror("smartmedia: unsupported command 0x%02x\n", data); - m_mode = SM_M_INIT; - break; - } -} - -/* - write a byte to SmartMedia address port -*/ -void nand_device::address_w(uint8_t data) -{ - if (!is_present()) - return; - - switch (m_mode) - { - case SM_M_INIT: - logerror("smartmedia: unexpected address port write\n"); - break; - case SM_M_READ: - case SM_M_PROGRAM: - if ((m_addr_load_ptr == 0) && (m_col_address_cycles == 1)) - { - switch (m_pointer_mode) - { - case SM_PM_A: - m_byte_addr = data; - break; - case SM_PM_B: - m_byte_addr = data + 256; - m_pointer_mode = SM_PM_A; - break; - case SM_PM_C: - if (!m_mode_3065) - m_byte_addr = (data & 0x0f) + m_page_data_size; - else - m_byte_addr = (data & 0x0f) + 256; - break; - } - } - else - { - if (m_addr_load_ptr < m_col_address_cycles) - { - m_byte_addr &= ~(0xFF << (m_addr_load_ptr * 8)); - m_byte_addr |= (data << (m_addr_load_ptr * 8)); - } - else if (m_addr_load_ptr < m_col_address_cycles + m_row_address_cycles) - { - m_page_addr &= ~(0xFF << ((m_addr_load_ptr - m_col_address_cycles) * 8)); - m_page_addr |= (data << ((m_addr_load_ptr - m_col_address_cycles) * 8)); - } - } - m_addr_load_ptr++; - break; - case SM_M_ERASE: - if (m_addr_load_ptr < m_row_address_cycles) - { - m_page_addr &= ~(0xFF << (m_addr_load_ptr * 8)); - m_page_addr |= (data << (m_addr_load_ptr * 8)); - } - m_addr_load_ptr++; - break; - case SM_M_RANDOM_DATA_INPUT: - case SM_M_RANDOM_DATA_OUTPUT: - if (m_addr_load_ptr < m_col_address_cycles) - { - m_byte_addr &= ~(0xFF << (m_addr_load_ptr * 8)); - m_byte_addr |= (data << (m_addr_load_ptr * 8)); - } - m_addr_load_ptr++; - break; - case SM_M_READSTATUS: - case SM_M_30: - logerror("smartmedia: unexpected address port write\n"); - break; - case SM_M_READID: - if (m_addr_load_ptr == 0) - m_byte_addr = data; - m_addr_load_ptr++; - break; - } -} - -/* - read a byte from SmartMedia data port -*/ -uint8_t nand_device::data_r() -{ - uint8_t reply = 0; - if (!is_present()) - return 0; - - switch (m_mode) - { - case SM_M_INIT: - case SM_M_30: - logerror("smartmedia: unexpected data port read\n"); - break; - case SM_M_READ: - case SM_M_RANDOM_DATA_OUTPUT: - if (!m_mode_3065) - { - if (m_byte_addr < m_page_total_size) - { - if (m_page_addr < m_num_pages) - reply = m_feeprom_data[m_page_addr * m_page_total_size + m_byte_addr]; - else - reply = 0xff; - } - else - { - reply = 0xFF; - } - } - else - { - // FIXME: this appears to be incorrect, m_data_uid_ptr is a smaller structure of 256*16 - // this code would always result in reading past the buffer - uint32_t addr = m_page_addr * m_page_total_size + m_byte_addr; - if (addr < 256 + 16) - reply = m_data_uid_ptr[addr]; - } - m_byte_addr++; - if ((m_byte_addr == m_page_total_size) && (m_sequential_row_read != 0)) - { - m_byte_addr = (m_pointer_mode != SM_PM_C) ? 0 : m_page_data_size; - m_page_addr++; - if (m_page_addr == m_num_pages) - m_page_addr = 0; - } - break; - case SM_M_PROGRAM: - case SM_M_RANDOM_DATA_INPUT: - case SM_M_ERASE: - logerror("smartmedia: unexpected data port read\n"); - break; - case SM_M_READSTATUS: - reply = m_status & 0xc1; - break; - case SM_M_READID: - if (m_byte_addr < m_id_len) - reply = m_id[m_byte_addr]; - else - reply = 0; - m_byte_addr++; - break; - } - - return reply; -} - -/* - write a byte to SmartMedia data port -*/ -void nand_device::data_w(uint8_t data) -{ - if (!is_present()) - return; - - switch (m_mode) - { - case SM_M_INIT: - case SM_M_READ: - case SM_M_30: - case SM_M_RANDOM_DATA_OUTPUT: - logerror("smartmedia: unexpected data port write\n"); - break; - case SM_M_PROGRAM: - case SM_M_RANDOM_DATA_INPUT: - if (m_program_byte_count++ < m_page_total_size) - { - m_pagereg[m_byte_addr] = data; - } - m_byte_addr++; - if (m_byte_addr == m_page_total_size) - m_byte_addr = (m_pointer_mode != SM_PM_C) ? 0 : m_page_data_size; - break; - case SM_M_ERASE: - case SM_M_READSTATUS: - case SM_M_READID: - logerror("smartmedia: unexpected data port write\n"); - break; - } -} - - -/* - Initialize one SmartMedia chip: may be called at driver init or image load - time (or machine init time if you don't use MESS image core) -*/ -void nand_device::device_reset() -{ - m_mode = SM_M_INIT; - m_pointer_mode = SM_PM_A; - m_status = (m_status & 0x80) | 0x40; - m_accumulated_status = 0; -} - - DEFINE_DEVICE_TYPE(SMARTMEDIA, smartmedia_image_device, "smartmedia", "SmartMedia Flash card") smartmedia_image_device::smartmedia_image_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : nand_device(mconfig, SMARTMEDIA, tag, owner, clock) , device_memcard_image_interface(mconfig, *this) { + // SmartMedia images have been read only so keep it that way until someone puts more thought into this device + nvram_enable_backup(false); } const software_list_loader &smartmedia_image_device::get_software_list_loader() const diff --git a/src/devices/machine/smartmed.h b/src/devices/machine/smartmed.h index c44c106c14b..214f4889eea 100644 --- a/src/devices/machine/smartmed.h +++ b/src/devices/machine/smartmed.h @@ -11,6 +11,7 @@ #include "formats/imageutl.h" #include "imagedev/memcard.h" +#include "machine/nandflash.h" //#define SMARTMEDIA_IMAGE_SAVE @@ -19,182 +20,6 @@ TYPE DEFINITIONS ***************************************************************************/ -// ======================> nand_device -class nand_device : public device_t -{ -public: - // "Sequential Row Read is available only on K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P" - enum class chip - { - K9F5608U0D = 0, // K9F5608U0D - K9F5608U0D_J, // K9F5608U0D-Jxxx - K9F5608U0B, // K9F5608U0B - K9F1G08U0B, // K9F1G08U0B - K9LAG08U0M // K9LAG08U0M - }; - - // construction/destruction - nand_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - - auto rnb_wr_callback() { return m_write_rnb.bind(); } - - void set_nand_type(chip type) - { - switch (type) - { - case chip::K9F5608U0D: - m_id_len = 2; - m_id[0] = 0xec; - m_id[1] = 0x75; - m_page_data_size = 512; - m_page_total_size = 512 + 16; - m_log2_pages_per_block = compute_log2(32); - m_num_pages = 32 * 2048; - m_col_address_cycles = 1; - m_row_address_cycles = 2; - m_sequential_row_read = 1; - break; - case chip::K9F5608U0D_J: - case chip::K9F5608U0B: - m_id_len = 2; - m_id[0] = 0xec; - m_id[1] = 0x75; - m_page_data_size = 512; - m_page_total_size = 512 + 16; - m_log2_pages_per_block = compute_log2(32); - m_num_pages = 32 * 2048; - m_col_address_cycles = 1; - m_row_address_cycles = 2; - m_sequential_row_read = 0; - break; - case chip::K9F1G08U0B: - m_id_len = 5; - m_id[0] = 0xec; - m_id[1] = 0xf1; - m_id[2] = 0x00; - m_id[3] = 0x95; - m_id[4] = 0x40; - m_page_data_size = 2048; - m_page_total_size = 2048 + 64; - m_log2_pages_per_block = compute_log2(64); - m_num_pages = 64 * 1024; - m_col_address_cycles = 2; - m_row_address_cycles = 2; - m_sequential_row_read = 0; - break; - case chip::K9LAG08U0M: - m_id_len = 5; - m_id[0] = 0xec; - m_id[1] = 0xd5; - m_id[2] = 0x55; - m_id[3] = 0x25; - m_id[4] = 0x68; - m_page_data_size = 2048; - m_page_total_size = 2048 + 64; - m_log2_pages_per_block = compute_log2(128); - m_num_pages = 128 * 8192; - m_col_address_cycles = 2; - m_row_address_cycles = 3; - m_sequential_row_read = 0; - break; - default: - printf("Unknown NAND type!\n"); - m_id_len = 0; - m_page_data_size = 0; - m_page_total_size = 0; - m_log2_pages_per_block = 0; - m_num_pages = 0; - m_col_address_cycles = 0; - m_row_address_cycles = 0; - m_sequential_row_read = 0; - break; - } - } - - int is_present(); - int is_protected(); - int is_busy(); - - uint8_t data_r(); - void command_w(uint8_t data); - void address_w(uint8_t data); - void data_w(uint8_t data); - - void set_data_ptr(void *ptr); - -protected: - enum sm_mode_t - { - SM_M_INIT, // initial state - SM_M_READ, // read page data - SM_M_PROGRAM, // program page data - SM_M_ERASE, // erase block data - SM_M_READSTATUS,// read status - SM_M_READID, // read ID - SM_M_30, - SM_M_RANDOM_DATA_INPUT, - SM_M_RANDOM_DATA_OUTPUT - }; - - enum pointer_sm_mode_t - { - SM_PM_A, // accessing first 256-byte half of 512-byte data field - SM_PM_B, // accessing second 256-byte half of 512-byte data field - SM_PM_C // accessing spare field - }; - - nand_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); - - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; - - int m_page_data_size; // 256 for a 2MB card, 512 otherwise - int m_page_total_size;// 264 for a 2MB card, 528 otherwise - int m_num_pages; // 8192 for a 4MB card, 16184 for 8MB, 32768 for 16MB, - // 65536 for 32MB, 131072 for 64MB, 262144 for 128MB... - // 0 means no card loaded - int m_log2_pages_per_block; // log2 of number of pages per erase block (usually 4 or 5) - - uint8_t *m_feeprom_data; // FEEPROM data area - std::unique_ptr m_feeprom_data_alloc; - std::unique_ptr m_data_uid_ptr; - - sm_mode_t m_mode; // current operation mode - pointer_sm_mode_t m_pointer_mode; // pointer mode - - unsigned int m_page_addr; // page address pointer - int m_byte_addr; // byte address pointer - int m_addr_load_ptr; // address load pointer - - int m_status; // current status - int m_accumulated_status; // accumulated status - - std::unique_ptr m_pagereg; // page register used by program command - uint8_t m_id[5]; // chip ID - uint8_t m_mp_opcode; // multi-plane operation code - - int m_mode_3065; - - // Palm Z22 NAND has 512 + 16 byte pages but, for some reason, Palm OS writes 512 + 64 bytes when - // programming a page, so we need to keep track of the number of bytes written so we can ignore the - // last 48 (64 - 16) bytes or else the first 48 bytes get overwritten - int m_program_byte_count; - - int m_id_len; - int m_col_address_cycles; - int m_row_address_cycles; - int m_sequential_row_read; - - devcb_write_line m_write_rnb; - -#ifdef SMARTMEDIA_IMAGE_SAVE - int m_image_format; -#endif -}; - - - class smartmedia_image_device : public nand_device, public device_memcard_image_interface { public: @@ -210,17 +35,23 @@ public: virtual std::error_condition call_load() override; virtual void call_unload() override; + // Because nand_device is a NVRAM device now, stub these to make it not do anything (read only) + virtual void nvram_default() override {}; + virtual bool nvram_read(util::read_stream &file) override { return true; }; + virtual bool nvram_write(util::write_stream &file) override { return false; }; + protected: virtual const software_list_loader &get_software_list_loader() const override; std::error_condition smartmedia_format_1(); std::error_condition smartmedia_format_2(); int detect_geometry(uint8_t id1, uint8_t id2); + + uint8_t m_mp_opcode; // multi-plane operation code }; // device type definition -DECLARE_DEVICE_TYPE(NAND, nand_device) DECLARE_DEVICE_TYPE(SMARTMEDIA, smartmedia_image_device) #endif // MAME_MACHINE_SMARTMEDIA_H diff --git a/src/devices/sound/spu.cpp b/src/devices/sound/spu.cpp index 7cc987a8067..a06d7af7a28 100644 --- a/src/devices/sound/spu.cpp +++ b/src/devices/sound/spu.cpp @@ -959,15 +959,18 @@ spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t { } -//------------------------------------------------- -// static_set_irqf - configuration helper to set -// the IRQ callback -//------------------------------------------------- - void spu_device::device_start() { m_irq_handler.resolve_safe(); + spu_base_frequency_hz = clock() / 768.0f; + generate_linear_rate_table(); + generate_pos_exp_rate_table(); + generate_neg_exp_rate_table(); + generate_decay_rate_table(); + generate_linear_release_rate_table(); + generate_exp_release_rate_table(); + voice=new voiceinfo [24]; spu_ram=std::make_unique(spu_ram_size); @@ -1100,7 +1103,7 @@ void spu_device::init_stream() rev=new reverb(hz); cdda_freq=(unsigned int)((44100.0f/(float)hz)*4096.0f); - freq_multiplier=(float)spu_base_frequency_hz/(float)hz; + freq_multiplier=spu_base_frequency_hz/(float)hz; } // diff --git a/src/devices/sound/spu.h b/src/devices/sound/spu.h index 7aee602e38c..e8cf2bfb25f 100644 --- a/src/devices/sound/spu.h +++ b/src/devices/sound/spu.h @@ -26,7 +26,6 @@ class spu_device : public device_t, public device_sound_interface }; protected: - static constexpr unsigned int spu_base_frequency_hz=44100; class reverb; // device-level overrides @@ -37,14 +36,13 @@ protected: virtual void sound_stream_update(sound_stream &stream, std::vector const &inputs, std::vector &outputs) override; - static constexpr float ms_to_rate(float ms) { return 1.0f / (ms * (float(spu_base_frequency_hz) / 1000.0f)); } - static constexpr float s_to_rate(float s) { return ms_to_rate(s * 1000.0f); } - static const float linear_rate[]; - static const float pos_exp_rate[]; - static const float neg_exp_rate[]; - static const float decay_rate[]; - static const float linear_release_rate[]; - static const float exp_release_rate[]; + float spu_base_frequency_hz; + float linear_rate[108]; + float pos_exp_rate[100]; + float neg_exp_rate[108]; + float decay_rate[16]; + float linear_release_rate[27]; + float exp_release_rate[27]; // internal state devcb_write_line m_irq_handler; @@ -145,6 +143,9 @@ protected: static reverb_preset reverb_presets[]; static reverb_params *spu_reverb_cfg; + float ms_to_rate(float ms) const { return 1.0f / (ms * (spu_base_frequency_hz / 1000.0f)); } + float s_to_rate(float s) const { return ms_to_rate(s * 1000.0f); } + void key_on(const int v); void key_off(const int v); bool update_envelope(const int v); @@ -187,17 +188,25 @@ protected: void write_cache_pointer(outfile *fout, cache_pointer *cp, sample_loop_cache *lc=nullptr); void read_cache_pointer(infile *fin, cache_pointer *cp, sample_loop_cache **lc=nullptr); #endif - static float get_linear_rate(const int n); - static float get_linear_rate_neg_phase(const int n); - static float get_pos_exp_rate(const int n); - static float get_pos_exp_rate_neg_phase(const int n); - static float get_neg_exp_rate(const int n); - static float get_neg_exp_rate_neg_phase(const int n); - static float get_decay_rate(const int n); - static float get_sustain_level(const int n); - static float get_linear_release_rate(const int n); - static float get_exp_release_rate(const int n); - static reverb_preset *find_reverb_preset(const unsigned short *param); + + void generate_linear_rate_table(); + void generate_pos_exp_rate_table(); + void generate_neg_exp_rate_table(); + void generate_decay_rate_table(); + void generate_linear_release_rate_table(); + void generate_exp_release_rate_table(); + + float get_linear_rate(const int n); + float get_linear_rate_neg_phase(const int n); + float get_pos_exp_rate(const int n); + float get_pos_exp_rate_neg_phase(const int n); + float get_neg_exp_rate(const int n); + float get_neg_exp_rate_neg_phase(const int n); + float get_decay_rate(const int n); + float get_sustain_level(const int n); + float get_linear_release_rate(const int n); + float get_exp_release_rate(const int n); + reverb_preset *find_reverb_preset(const unsigned short *param); public: spu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, psxcpu_device *cpu); diff --git a/src/devices/sound/spu_tables.cpp b/src/devices/sound/spu_tables.cpp index 1bf9c851b00..39cdf87d4b7 100644 --- a/src/devices/sound/spu_tables.cpp +++ b/src/devices/sound/spu_tables.cpp @@ -4,420 +4,6 @@ #include "spu.h" #include "spureverb.h" -const float spu_device::linear_rate[]= -{ - ms_to_rate(0.05f), - ms_to_rate(0.06f), - ms_to_rate(0.07f), - ms_to_rate(0.09f), - ms_to_rate(0.10f), - ms_to_rate(0.12f), - ms_to_rate(0.15f), - ms_to_rate(0.18f), - ms_to_rate(0.21f), - ms_to_rate(0.24f), - ms_to_rate(0.29f), - ms_to_rate(0.36f), - ms_to_rate(0.41f), - ms_to_rate(0.48f), - ms_to_rate(0.58f), - ms_to_rate(0.73f), - ms_to_rate(0.83f), - ms_to_rate(0.97f), - ms_to_rate(1.2f), - ms_to_rate(1.5f), - ms_to_rate(1.7f), - ms_to_rate(1.9f), - ms_to_rate(2.3f), - ms_to_rate(2.9f), - ms_to_rate(3.3f), - ms_to_rate(3.9f), - ms_to_rate(4.6f), - ms_to_rate(5.8f), - ms_to_rate(6.6f), - ms_to_rate(7.7f), - ms_to_rate(9.3f), - ms_to_rate(12.0f), - ms_to_rate(13.0f), - ms_to_rate(15.0f), - ms_to_rate(19.0f), - ms_to_rate(23.0f), - ms_to_rate(27.0f), - ms_to_rate(31.0f), - ms_to_rate(37.0f), - ms_to_rate(46.0f), - ms_to_rate(53.0f), - ms_to_rate(62.0f), - ms_to_rate(74.0f), - ms_to_rate(93.0f), - s_to_rate(0.11f), - s_to_rate(0.12f), - s_to_rate(0.15f), - s_to_rate(0.19f), - s_to_rate(0.21f), - s_to_rate(0.25f), - s_to_rate(0.30f), - s_to_rate(0.37f), - s_to_rate(0.42f), - s_to_rate(0.50f), - s_to_rate(0.59f), - s_to_rate(0.74f), - s_to_rate(0.85f), - s_to_rate(0.99f), - s_to_rate(1.2f), - s_to_rate(1.5f), - s_to_rate(1.7f), - s_to_rate(2.0f), - s_to_rate(2.4f), - s_to_rate(3.0f), - s_to_rate(3.4f), - s_to_rate(4.0f), - s_to_rate(4.8f), - s_to_rate(5.9f), - s_to_rate(6.8f), - s_to_rate(7.9f), - s_to_rate(9.5f), - s_to_rate(12.0f), - s_to_rate(14.0f), - s_to_rate(16.0f), - s_to_rate(19.0f), - s_to_rate(24.0f), - s_to_rate(27.0f), - s_to_rate(32.0f), - s_to_rate(38.0f), - s_to_rate(48.0f), - s_to_rate(54.0f), - s_to_rate(63.0f), - s_to_rate(76.0f), - s_to_rate(95.0f), - s_to_rate(109.0f), - s_to_rate(127.0f), - s_to_rate(152.0f), - s_to_rate(190.0f), - s_to_rate(218.0f), - s_to_rate(254.0f), - s_to_rate(304.0f), - s_to_rate(380.0f), - s_to_rate(436.0f), - s_to_rate(508.0f), - s_to_rate(608.0f), - s_to_rate(760.0f), - s_to_rate(872.0f), - s_to_rate(1016.0f), - s_to_rate(1216.0f), - s_to_rate(1520.0f), - s_to_rate(1744.0f), - s_to_rate(2032.0f), - s_to_rate(2432.0f), - s_to_rate(3040.0f), - s_to_rate(3488.0f), - s_to_rate(4064.0f), - s_to_rate(4864.0f), - s_to_rate(6080.0f) -}; - - -const float spu_device::pos_exp_rate[]= -{ - ms_to_rate(0.09f), - ms_to_rate(0.11f), - ms_to_rate(0.13f), - ms_to_rate(0.16f), - ms_to_rate(0.18f), - ms_to_rate(0.21f), - ms_to_rate(0.25f), - ms_to_rate(0.32f), - ms_to_rate(0.36f), - ms_to_rate(0.42f), - ms_to_rate(0.51f), - ms_to_rate(0.64f), - ms_to_rate(0.73f), - ms_to_rate(0.85f), - ms_to_rate(1.0f), - ms_to_rate(1.3f), - ms_to_rate(1.5f), - ms_to_rate(1.7f), - ms_to_rate(2.0f), - ms_to_rate(2.5f), - ms_to_rate(2.9f), - ms_to_rate(3.4f), - ms_to_rate(4.1f), - ms_to_rate(5.1f), - ms_to_rate(5.8f), - ms_to_rate(6.8f), - ms_to_rate(8.1f), - ms_to_rate(10.0f), - ms_to_rate(12.0f), - ms_to_rate(14.0f), - ms_to_rate(16.0f), - ms_to_rate(20.0f), - ms_to_rate(23.0f), - ms_to_rate(27.0f), - ms_to_rate(33.0f), - ms_to_rate(41.0f), - ms_to_rate(46.0f), - ms_to_rate(54.0f), - ms_to_rate(65.0f), - ms_to_rate(81.0f), - ms_to_rate(93.0f), - s_to_rate(0.11f), - s_to_rate(0.13f), - s_to_rate(0.16f), - s_to_rate(0.19f), - s_to_rate(0.22f), - s_to_rate(0.26f), - s_to_rate(0.33f), - s_to_rate(0.37f), - s_to_rate(0.43f), - s_to_rate(0.52f), - s_to_rate(0.65f), - s_to_rate(0.74f), - s_to_rate(0.87f), - s_to_rate(1.0f), - s_to_rate(1.3f), - s_to_rate(1.5f), - s_to_rate(1.7f), - s_to_rate(2.1f), - s_to_rate(2.6f), - s_to_rate(3.0f), - s_to_rate(3.5f), - s_to_rate(4.2f), - s_to_rate(5.2f), - s_to_rate(5.9f), - s_to_rate(6.9f), - s_to_rate(8.3f), - s_to_rate(10.0f), - s_to_rate(12.0f), - s_to_rate(14.0f), - s_to_rate(17.0f), - s_to_rate(21.0f), - s_to_rate(24.0f), - s_to_rate(28.0f), - s_to_rate(33.0f), - s_to_rate(42.0f), - s_to_rate(48.0f), - s_to_rate(55.0f), - s_to_rate(67.0f), - s_to_rate(83.0f), - s_to_rate(95.0f), - s_to_rate(111.0f), - s_to_rate(133.0f), - s_to_rate(166.0f), - s_to_rate(190.0f), - s_to_rate(222.0f), - s_to_rate(266.0f), - s_to_rate(333.0f), - s_to_rate(380.0f), - s_to_rate(444.0f), - s_to_rate(532.0f), - s_to_rate(666.0f), - s_to_rate(760.0f), - s_to_rate(888.0f), - s_to_rate(1064.0f), - s_to_rate(1332.0f), - s_to_rate(1520.0f), - s_to_rate(1776.0f), - s_to_rate(2128.0f), - s_to_rate(2664.0f) -}; - - -const float spu_device::neg_exp_rate[]= -{ - ms_to_rate(0.07f), - ms_to_rate(0.09f), - ms_to_rate(0.11f), - ms_to_rate(0.14f), - ms_to_rate(0.18f), - ms_to_rate(0.21f), - ms_to_rate(0.25f), - ms_to_rate(0.31f), - ms_to_rate(0.39f), - ms_to_rate(0.45f), - ms_to_rate(0.53f), - ms_to_rate(0.64f), - ms_to_rate(0.81f), - ms_to_rate(0.93f), - ms_to_rate(1.1f), - ms_to_rate(1.3f), - ms_to_rate(1.6f), - ms_to_rate(1.9f), - ms_to_rate(2.2f), - ms_to_rate(2.6f), - ms_to_rate(3.3f), - ms_to_rate(3.8f), - ms_to_rate(4.4f), - ms_to_rate(5.3f), - ms_to_rate(6.7f), - ms_to_rate(7.6f), - ms_to_rate(8.9f), - ms_to_rate(11.0f), - ms_to_rate(13.0f), - ms_to_rate(15.0f), - ms_to_rate(18.0f), - ms_to_rate(21.0f), - ms_to_rate(27.0f), - ms_to_rate(31.0f), - ms_to_rate(36.0f), - ms_to_rate(43.0f), - ms_to_rate(53.0f), - ms_to_rate(61.0f), - ms_to_rate(71.0f), - ms_to_rate(86.0f), - s_to_rate(0.11f), - s_to_rate(0.12f), - s_to_rate(0.14f), - s_to_rate(0.17f), - s_to_rate(0.21f), - s_to_rate(0.24f), - s_to_rate(0.29f), - s_to_rate(0.34f), - s_to_rate(0.43f), - s_to_rate(0.49f), - s_to_rate(0.57f), - s_to_rate(0.68f), - s_to_rate(0.86f), - s_to_rate(0.98f), - s_to_rate(1.1f), - s_to_rate(1.4f), - s_to_rate(1.7f), - s_to_rate(2.0f), - s_to_rate(2.3f), - s_to_rate(2.7f), - s_to_rate(3.4f), - s_to_rate(3.9f), - s_to_rate(4.6f), - s_to_rate(5.5f), - s_to_rate(6.8f), - s_to_rate(7.8f), - s_to_rate(9.1f), - s_to_rate(11.0f), - s_to_rate(14.0f), - s_to_rate(16.0f), - s_to_rate(18.0f), - s_to_rate(22.0f), - s_to_rate(27.0f), - s_to_rate(31.0f), - s_to_rate(36.0f), - s_to_rate(44.0f), - s_to_rate(55.0f), - s_to_rate(63.0f), - s_to_rate(73.0f), - s_to_rate(88.0f), - s_to_rate(109.0f), - s_to_rate(125.0f), - s_to_rate(146.0f), - s_to_rate(175.0f), - s_to_rate(219.0f), - s_to_rate(250.0f), - s_to_rate(292.0f), - s_to_rate(350.0f), - s_to_rate(438.0f), - s_to_rate(500.0f), - s_to_rate(584.0f), - s_to_rate(700.0f), - s_to_rate(876.0f), - s_to_rate(1000.0f), - s_to_rate(1168.0f), - s_to_rate(1400.0f), - s_to_rate(1752.0f), - s_to_rate(2000.0f), - s_to_rate(2336.0f), - s_to_rate(2800.0f), - s_to_rate(3504.0f), - s_to_rate(4000.0f), - s_to_rate(4672.0f), - s_to_rate(5600.0f), - s_to_rate(7008.0f), - s_to_rate(8000.0f), - s_to_rate(9344.0f), - s_to_rate(11200.0f) -}; - - -const float spu_device::decay_rate[16]= -{ - ms_to_rate(0.07f), - ms_to_rate(0.18f), - ms_to_rate(0.39f), - ms_to_rate(0.81f), - ms_to_rate(1.6f), - ms_to_rate(3.3f), - ms_to_rate(6.7f), - ms_to_rate(13.0f), - ms_to_rate(27.0f), - ms_to_rate(53.0f), - s_to_rate(0.11f), - s_to_rate(0.21f), - s_to_rate(0.43f), - s_to_rate(0.86f), - s_to_rate(1.7f), - s_to_rate(3.4f), -}; - -const float spu_device::linear_release_rate[]= -{ - ms_to_rate(0.04f), - ms_to_rate(0.09f), - ms_to_rate(0.18f), - ms_to_rate(0.36f), - ms_to_rate(0.73f), - ms_to_rate(1.5f), - ms_to_rate(2.9f), - ms_to_rate(5.8f), - ms_to_rate(12.0f), - ms_to_rate(23.0f), - ms_to_rate(46.0f), - ms_to_rate(93.0f), - s_to_rate(0.19f), - s_to_rate(0.37f), - s_to_rate(1.74f), - s_to_rate(1.5f), - s_to_rate(3.0f), - s_to_rate(5.9f), - s_to_rate(12.0f), - s_to_rate(24.0f), - s_to_rate(48.0f), - s_to_rate(95.0f), - s_to_rate(190.0f), - s_to_rate(380.0f), - s_to_rate(760.0f), - s_to_rate(1520.0f), - s_to_rate(3040.0f) -}; - - -const float spu_device::exp_release_rate[]= -{ - ms_to_rate(0.07f), - ms_to_rate(0.18f), - ms_to_rate(0.39f), - ms_to_rate(0.81f), - ms_to_rate(1.6f), - ms_to_rate(3.3f), - ms_to_rate(6.7f), - ms_to_rate(13.0f), - ms_to_rate(27.0f), - ms_to_rate(53.0f), - s_to_rate(0.11f), - s_to_rate(0.21f), - s_to_rate(0.43f), - s_to_rate(0.86f), - s_to_rate(1.7f), - s_to_rate(3.4f), - s_to_rate(6.8f), - s_to_rate(14.0f), - s_to_rate(27.0f), - s_to_rate(55.0f), - s_to_rate(109.0f), - s_to_rate(219.0f), - s_to_rate(438.0f), - s_to_rate(876.0f), - s_to_rate(1752.0f), - s_to_rate(3504.0f), - s_to_rate(7008.0f) -}; - // // @@ -615,9 +201,423 @@ spu_device::reverb_preset spu_device::reverb_presets[]= // // + + +void spu_device::generate_linear_rate_table() +{ + linear_rate[0] = ms_to_rate(0.05f); + linear_rate[1] = ms_to_rate(0.06f); + linear_rate[2] = ms_to_rate(0.07f); + linear_rate[3] = ms_to_rate(0.09f); + linear_rate[4] = ms_to_rate(0.10f); + linear_rate[5] = ms_to_rate(0.12f); + linear_rate[6] = ms_to_rate(0.15f); + linear_rate[7] = ms_to_rate(0.18f); + linear_rate[8] = ms_to_rate(0.21f); + linear_rate[9] = ms_to_rate(0.24f); + linear_rate[10] = ms_to_rate(0.29f); + linear_rate[11] = ms_to_rate(0.36f); + linear_rate[12] = ms_to_rate(0.41f); + linear_rate[13] = ms_to_rate(0.48f); + linear_rate[14] = ms_to_rate(0.58f); + linear_rate[15] = ms_to_rate(0.73f); + linear_rate[16] = ms_to_rate(0.83f); + linear_rate[17] = ms_to_rate(0.97f); + linear_rate[18] = ms_to_rate(1.2f); + linear_rate[19] = ms_to_rate(1.5f); + linear_rate[20] = ms_to_rate(1.7f); + linear_rate[21] = ms_to_rate(1.9f); + linear_rate[22] = ms_to_rate(2.3f); + linear_rate[23] = ms_to_rate(2.9f); + linear_rate[24] = ms_to_rate(3.3f); + linear_rate[25] = ms_to_rate(3.9f); + linear_rate[26] = ms_to_rate(4.6f); + linear_rate[27] = ms_to_rate(5.8f); + linear_rate[28] = ms_to_rate(6.6f); + linear_rate[29] = ms_to_rate(7.7f); + linear_rate[30] = ms_to_rate(9.3f); + linear_rate[31] = ms_to_rate(12.0f); + linear_rate[32] = ms_to_rate(13.0f); + linear_rate[33] = ms_to_rate(15.0f); + linear_rate[34] = ms_to_rate(19.0f); + linear_rate[35] = ms_to_rate(23.0f); + linear_rate[36] = ms_to_rate(27.0f); + linear_rate[37] = ms_to_rate(31.0f); + linear_rate[38] = ms_to_rate(37.0f); + linear_rate[39] = ms_to_rate(46.0f); + linear_rate[40] = ms_to_rate(53.0f); + linear_rate[41] = ms_to_rate(62.0f); + linear_rate[42] = ms_to_rate(74.0f); + linear_rate[43] = ms_to_rate(93.0f); + linear_rate[44] = s_to_rate(0.11f); + linear_rate[45] = s_to_rate(0.12f); + linear_rate[46] = s_to_rate(0.15f); + linear_rate[47] = s_to_rate(0.19f); + linear_rate[48] = s_to_rate(0.21f); + linear_rate[49] = s_to_rate(0.25f); + linear_rate[50] = s_to_rate(0.30f); + linear_rate[51] = s_to_rate(0.37f); + linear_rate[52] = s_to_rate(0.42f); + linear_rate[53] = s_to_rate(0.50f); + linear_rate[54] = s_to_rate(0.59f); + linear_rate[55] = s_to_rate(0.74f); + linear_rate[56] = s_to_rate(0.85f); + linear_rate[57] = s_to_rate(0.99f); + linear_rate[58] = s_to_rate(1.2f); + linear_rate[59] = s_to_rate(1.5f); + linear_rate[60] = s_to_rate(1.7f); + linear_rate[61] = s_to_rate(2.0f); + linear_rate[62] = s_to_rate(2.4f); + linear_rate[63] = s_to_rate(3.0f); + linear_rate[64] = s_to_rate(3.4f); + linear_rate[65] = s_to_rate(4.0f); + linear_rate[66] = s_to_rate(4.8f); + linear_rate[67] = s_to_rate(5.9f); + linear_rate[68] = s_to_rate(6.8f); + linear_rate[69] = s_to_rate(7.9f); + linear_rate[70] = s_to_rate(9.5f); + linear_rate[71] = s_to_rate(12.0f); + linear_rate[72] = s_to_rate(14.0f); + linear_rate[73] = s_to_rate(16.0f); + linear_rate[74] = s_to_rate(19.0f); + linear_rate[75] = s_to_rate(24.0f); + linear_rate[76] = s_to_rate(27.0f); + linear_rate[77] = s_to_rate(32.0f); + linear_rate[78] = s_to_rate(38.0f); + linear_rate[79] = s_to_rate(48.0f); + linear_rate[80] = s_to_rate(54.0f); + linear_rate[81] = s_to_rate(63.0f); + linear_rate[82] = s_to_rate(76.0f); + linear_rate[83] = s_to_rate(95.0f); + linear_rate[84] = s_to_rate(109.0f); + linear_rate[85] = s_to_rate(127.0f); + linear_rate[86] = s_to_rate(152.0f); + linear_rate[87] = s_to_rate(190.0f); + linear_rate[88] = s_to_rate(218.0f); + linear_rate[89] = s_to_rate(254.0f); + linear_rate[90] = s_to_rate(304.0f); + linear_rate[91] = s_to_rate(380.0f); + linear_rate[92] = s_to_rate(436.0f); + linear_rate[93] = s_to_rate(508.0f); + linear_rate[94] = s_to_rate(608.0f); + linear_rate[95] = s_to_rate(760.0f); + linear_rate[96] = s_to_rate(872.0f); + linear_rate[97] = s_to_rate(1016.0f); + linear_rate[98] = s_to_rate(1216.0f); + linear_rate[99] = s_to_rate(1520.0f); + linear_rate[100] = s_to_rate(1744.0f); + linear_rate[101] = s_to_rate(2032.0f); + linear_rate[102] = s_to_rate(2432.0f); + linear_rate[103] = s_to_rate(3040.0f); + linear_rate[104] = s_to_rate(3488.0f); + linear_rate[105] = s_to_rate(4064.0f); + linear_rate[106] = s_to_rate(4864.0f); + linear_rate[107] = s_to_rate(6080.0f); +} + + +void spu_device::generate_pos_exp_rate_table() +{ + pos_exp_rate[0] = ms_to_rate(0.09f); + pos_exp_rate[1] = ms_to_rate(0.11f); + pos_exp_rate[2] = ms_to_rate(0.13f); + pos_exp_rate[3] = ms_to_rate(0.16f); + pos_exp_rate[4] = ms_to_rate(0.18f); + pos_exp_rate[5] = ms_to_rate(0.21f); + pos_exp_rate[6] = ms_to_rate(0.25f); + pos_exp_rate[7] = ms_to_rate(0.32f); + pos_exp_rate[8] = ms_to_rate(0.36f); + pos_exp_rate[9] = ms_to_rate(0.42f); + pos_exp_rate[10] = ms_to_rate(0.51f); + pos_exp_rate[11] = ms_to_rate(0.64f); + pos_exp_rate[12] = ms_to_rate(0.73f); + pos_exp_rate[13] = ms_to_rate(0.85f); + pos_exp_rate[14] = ms_to_rate(1.0f); + pos_exp_rate[15] = ms_to_rate(1.3f); + pos_exp_rate[16] = ms_to_rate(1.5f); + pos_exp_rate[17] = ms_to_rate(1.7f); + pos_exp_rate[18] = ms_to_rate(2.0f); + pos_exp_rate[19] = ms_to_rate(2.5f); + pos_exp_rate[20] = ms_to_rate(2.9f); + pos_exp_rate[21] = ms_to_rate(3.4f); + pos_exp_rate[22] = ms_to_rate(4.1f); + pos_exp_rate[23] = ms_to_rate(5.1f); + pos_exp_rate[24] = ms_to_rate(5.8f); + pos_exp_rate[25] = ms_to_rate(6.8f); + pos_exp_rate[26] = ms_to_rate(8.1f); + pos_exp_rate[27] = ms_to_rate(10.0f); + pos_exp_rate[28] = ms_to_rate(12.0f); + pos_exp_rate[29] = ms_to_rate(14.0f); + pos_exp_rate[30] = ms_to_rate(16.0f); + pos_exp_rate[31] = ms_to_rate(20.0f); + pos_exp_rate[32] = ms_to_rate(23.0f); + pos_exp_rate[33] = ms_to_rate(27.0f); + pos_exp_rate[34] = ms_to_rate(33.0f); + pos_exp_rate[35] = ms_to_rate(41.0f); + pos_exp_rate[36] = ms_to_rate(46.0f); + pos_exp_rate[37] = ms_to_rate(54.0f); + pos_exp_rate[38] = ms_to_rate(65.0f); + pos_exp_rate[39] = ms_to_rate(81.0f); + pos_exp_rate[40] = ms_to_rate(93.0f); + pos_exp_rate[41] = s_to_rate(0.11f); + pos_exp_rate[42] = s_to_rate(0.13f); + pos_exp_rate[43] = s_to_rate(0.16f); + pos_exp_rate[44] = s_to_rate(0.19f); + pos_exp_rate[45] = s_to_rate(0.22f); + pos_exp_rate[46] = s_to_rate(0.26f); + pos_exp_rate[47] = s_to_rate(0.33f); + pos_exp_rate[48] = s_to_rate(0.37f); + pos_exp_rate[49] = s_to_rate(0.43f); + pos_exp_rate[50] = s_to_rate(0.52f); + pos_exp_rate[51] = s_to_rate(0.65f); + pos_exp_rate[52] = s_to_rate(0.74f); + pos_exp_rate[53] = s_to_rate(0.87f); + pos_exp_rate[54] = s_to_rate(1.0f); + pos_exp_rate[55] = s_to_rate(1.3f); + pos_exp_rate[56] = s_to_rate(1.5f); + pos_exp_rate[57] = s_to_rate(1.7f); + pos_exp_rate[58] = s_to_rate(2.1f); + pos_exp_rate[59] = s_to_rate(2.6f); + pos_exp_rate[60] = s_to_rate(3.0f); + pos_exp_rate[61] = s_to_rate(3.5f); + pos_exp_rate[62] = s_to_rate(4.2f); + pos_exp_rate[63] = s_to_rate(5.2f); + pos_exp_rate[64] = s_to_rate(5.9f); + pos_exp_rate[65] = s_to_rate(6.9f); + pos_exp_rate[66] = s_to_rate(8.3f); + pos_exp_rate[67] = s_to_rate(10.0f); + pos_exp_rate[68] = s_to_rate(12.0f); + pos_exp_rate[69] = s_to_rate(14.0f); + pos_exp_rate[70] = s_to_rate(17.0f); + pos_exp_rate[71] = s_to_rate(21.0f); + pos_exp_rate[72] = s_to_rate(24.0f); + pos_exp_rate[73] = s_to_rate(28.0f); + pos_exp_rate[74] = s_to_rate(33.0f); + pos_exp_rate[75] = s_to_rate(42.0f); + pos_exp_rate[76] = s_to_rate(48.0f); + pos_exp_rate[77] = s_to_rate(55.0f); + pos_exp_rate[78] = s_to_rate(67.0f); + pos_exp_rate[79] = s_to_rate(83.0f); + pos_exp_rate[80] = s_to_rate(95.0f); + pos_exp_rate[81] = s_to_rate(111.0f); + pos_exp_rate[82] = s_to_rate(133.0f); + pos_exp_rate[83] = s_to_rate(166.0f); + pos_exp_rate[84] = s_to_rate(190.0f); + pos_exp_rate[85] = s_to_rate(222.0f); + pos_exp_rate[86] = s_to_rate(266.0f); + pos_exp_rate[87] = s_to_rate(333.0f); + pos_exp_rate[88] = s_to_rate(380.0f); + pos_exp_rate[89] = s_to_rate(444.0f); + pos_exp_rate[90] = s_to_rate(532.0f); + pos_exp_rate[91] = s_to_rate(666.0f); + pos_exp_rate[92] = s_to_rate(760.0f); + pos_exp_rate[93] = s_to_rate(888.0f); + pos_exp_rate[94] = s_to_rate(1064.0f); + pos_exp_rate[95] = s_to_rate(1332.0f); + pos_exp_rate[96] = s_to_rate(1520.0f); + pos_exp_rate[97] = s_to_rate(1776.0f); + pos_exp_rate[98] = s_to_rate(2128.0f); + pos_exp_rate[99] = s_to_rate(2664.0f); +} + + +void spu_device::generate_neg_exp_rate_table() +{ + neg_exp_rate[0] = ms_to_rate(0.07f); + neg_exp_rate[1] = ms_to_rate(0.09f); + neg_exp_rate[2] = ms_to_rate(0.11f); + neg_exp_rate[3] = ms_to_rate(0.14f); + neg_exp_rate[4] = ms_to_rate(0.18f); + neg_exp_rate[5] = ms_to_rate(0.21f); + neg_exp_rate[6] = ms_to_rate(0.25f); + neg_exp_rate[7] = ms_to_rate(0.31f); + neg_exp_rate[8] = ms_to_rate(0.39f); + neg_exp_rate[9] = ms_to_rate(0.45f); + neg_exp_rate[10] = ms_to_rate(0.53f); + neg_exp_rate[11] = ms_to_rate(0.64f); + neg_exp_rate[12] = ms_to_rate(0.81f); + neg_exp_rate[13] = ms_to_rate(0.93f); + neg_exp_rate[14] = ms_to_rate(1.1f); + neg_exp_rate[15] = ms_to_rate(1.3f); + neg_exp_rate[16] = ms_to_rate(1.6f); + neg_exp_rate[17] = ms_to_rate(1.9f); + neg_exp_rate[18] = ms_to_rate(2.2f); + neg_exp_rate[19] = ms_to_rate(2.6f); + neg_exp_rate[20] = ms_to_rate(3.3f); + neg_exp_rate[21] = ms_to_rate(3.8f); + neg_exp_rate[22] = ms_to_rate(4.4f); + neg_exp_rate[23] = ms_to_rate(5.3f); + neg_exp_rate[24] = ms_to_rate(6.7f); + neg_exp_rate[25] = ms_to_rate(7.6f); + neg_exp_rate[26] = ms_to_rate(8.9f); + neg_exp_rate[27] = ms_to_rate(11.0f); + neg_exp_rate[28] = ms_to_rate(13.0f); + neg_exp_rate[29] = ms_to_rate(15.0f); + neg_exp_rate[30] = ms_to_rate(18.0f); + neg_exp_rate[31] = ms_to_rate(21.0f); + neg_exp_rate[32] = ms_to_rate(27.0f); + neg_exp_rate[33] = ms_to_rate(31.0f); + neg_exp_rate[34] = ms_to_rate(36.0f); + neg_exp_rate[35] = ms_to_rate(43.0f); + neg_exp_rate[36] = ms_to_rate(53.0f); + neg_exp_rate[37] = ms_to_rate(61.0f); + neg_exp_rate[38] = ms_to_rate(71.0f); + neg_exp_rate[39] = ms_to_rate(86.0f); + neg_exp_rate[40] = s_to_rate(0.11f); + neg_exp_rate[41] = s_to_rate(0.12f); + neg_exp_rate[42] = s_to_rate(0.14f); + neg_exp_rate[43] = s_to_rate(0.17f); + neg_exp_rate[44] = s_to_rate(0.21f); + neg_exp_rate[45] = s_to_rate(0.24f); + neg_exp_rate[46] = s_to_rate(0.29f); + neg_exp_rate[47] = s_to_rate(0.34f); + neg_exp_rate[48] = s_to_rate(0.43f); + neg_exp_rate[49] = s_to_rate(0.49f); + neg_exp_rate[50] = s_to_rate(0.57f); + neg_exp_rate[51] = s_to_rate(0.68f); + neg_exp_rate[52] = s_to_rate(0.86f); + neg_exp_rate[53] = s_to_rate(0.98f); + neg_exp_rate[54] = s_to_rate(1.1f); + neg_exp_rate[55] = s_to_rate(1.4f); + neg_exp_rate[56] = s_to_rate(1.7f); + neg_exp_rate[57] = s_to_rate(2.0f); + neg_exp_rate[58] = s_to_rate(2.3f); + neg_exp_rate[59] = s_to_rate(2.7f); + neg_exp_rate[60] = s_to_rate(3.4f); + neg_exp_rate[61] = s_to_rate(3.9f); + neg_exp_rate[62] = s_to_rate(4.6f); + neg_exp_rate[63] = s_to_rate(5.5f); + neg_exp_rate[64] = s_to_rate(6.8f); + neg_exp_rate[65] = s_to_rate(7.8f); + neg_exp_rate[66] = s_to_rate(9.1f); + neg_exp_rate[67] = s_to_rate(11.0f); + neg_exp_rate[68] = s_to_rate(14.0f); + neg_exp_rate[69] = s_to_rate(16.0f); + neg_exp_rate[70] = s_to_rate(18.0f); + neg_exp_rate[71] = s_to_rate(22.0f); + neg_exp_rate[72] = s_to_rate(27.0f); + neg_exp_rate[73] = s_to_rate(31.0f); + neg_exp_rate[74] = s_to_rate(36.0f); + neg_exp_rate[75] = s_to_rate(44.0f); + neg_exp_rate[76] = s_to_rate(55.0f); + neg_exp_rate[77] = s_to_rate(63.0f); + neg_exp_rate[78] = s_to_rate(73.0f); + neg_exp_rate[79] = s_to_rate(88.0f); + neg_exp_rate[80] = s_to_rate(109.0f); + neg_exp_rate[81] = s_to_rate(125.0f); + neg_exp_rate[82] = s_to_rate(146.0f); + neg_exp_rate[83] = s_to_rate(175.0f); + neg_exp_rate[84] = s_to_rate(219.0f); + neg_exp_rate[85] = s_to_rate(250.0f); + neg_exp_rate[86] = s_to_rate(292.0f); + neg_exp_rate[87] = s_to_rate(350.0f); + neg_exp_rate[88] = s_to_rate(438.0f); + neg_exp_rate[89] = s_to_rate(500.0f); + neg_exp_rate[90] = s_to_rate(584.0f); + neg_exp_rate[91] = s_to_rate(700.0f); + neg_exp_rate[92] = s_to_rate(876.0f); + neg_exp_rate[93] = s_to_rate(1000.0f); + neg_exp_rate[94] = s_to_rate(1168.0f); + neg_exp_rate[95] = s_to_rate(1400.0f); + neg_exp_rate[96] = s_to_rate(1752.0f); + neg_exp_rate[97] = s_to_rate(2000.0f); + neg_exp_rate[98] = s_to_rate(2336.0f); + neg_exp_rate[99] = s_to_rate(2800.0f); + neg_exp_rate[100] = s_to_rate(3504.0f); + neg_exp_rate[101] = s_to_rate(4000.0f); + neg_exp_rate[102] = s_to_rate(4672.0f); + neg_exp_rate[103] = s_to_rate(5600.0f); + neg_exp_rate[104] = s_to_rate(7008.0f); + neg_exp_rate[105] = s_to_rate(8000.0f); + neg_exp_rate[106] = s_to_rate(9344.0f); + neg_exp_rate[107] = s_to_rate(11200.0f); +} + +void spu_device::generate_decay_rate_table() +{ + decay_rate[0] = ms_to_rate(0.07f); + decay_rate[1] = ms_to_rate(0.18f); + decay_rate[2] = ms_to_rate(0.39f); + decay_rate[3] = ms_to_rate(0.81f); + decay_rate[4] = ms_to_rate(1.6f); + decay_rate[5] = ms_to_rate(3.3f); + decay_rate[6] = ms_to_rate(6.7f); + decay_rate[7] = ms_to_rate(13.0f); + decay_rate[8] = ms_to_rate(27.0f); + decay_rate[9] = ms_to_rate(53.0f); + decay_rate[10] = s_to_rate(0.11f); + decay_rate[11] = s_to_rate(0.21f); + decay_rate[12] = s_to_rate(0.43f); + decay_rate[13] = s_to_rate(0.86f); + decay_rate[14] = s_to_rate(1.7f); + decay_rate[15] = s_to_rate(3.4f); +} + +void spu_device::generate_linear_release_rate_table() +{ + linear_release_rate[0] = ms_to_rate(0.04f); + linear_release_rate[1] = ms_to_rate(0.09f); + linear_release_rate[2] = ms_to_rate(0.18f); + linear_release_rate[3] = ms_to_rate(0.36f); + linear_release_rate[4] = ms_to_rate(0.73f); + linear_release_rate[5] = ms_to_rate(1.5f); + linear_release_rate[6] = ms_to_rate(2.9f); + linear_release_rate[7] = ms_to_rate(5.8f); + linear_release_rate[8] = ms_to_rate(12.0f); + linear_release_rate[9] = ms_to_rate(23.0f); + linear_release_rate[10] = ms_to_rate(46.0f); + linear_release_rate[11] = ms_to_rate(93.0f); + linear_release_rate[12] = s_to_rate(0.19f); + linear_release_rate[13] = s_to_rate(0.37f); + linear_release_rate[14] = s_to_rate(1.74f); + linear_release_rate[15] = s_to_rate(1.5f); + linear_release_rate[16] = s_to_rate(3.0f); + linear_release_rate[17] = s_to_rate(5.9f); + linear_release_rate[18] = s_to_rate(12.0f); + linear_release_rate[19] = s_to_rate(24.0f); + linear_release_rate[20] = s_to_rate(48.0f); + linear_release_rate[21] = s_to_rate(95.0f); + linear_release_rate[22] = s_to_rate(190.0f); + linear_release_rate[23] = s_to_rate(380.0f); + linear_release_rate[24] = s_to_rate(760.0f); + linear_release_rate[25] = s_to_rate(1520.0f); + linear_release_rate[26] = s_to_rate(3040.0f); +} + +void spu_device::generate_exp_release_rate_table() +{ + exp_release_rate[0] = ms_to_rate(0.07f); + exp_release_rate[1] = ms_to_rate(0.18f); + exp_release_rate[2] = ms_to_rate(0.39f); + exp_release_rate[3] = ms_to_rate(0.81f); + exp_release_rate[4] = ms_to_rate(1.6f); + exp_release_rate[5] = ms_to_rate(3.3f); + exp_release_rate[6] = ms_to_rate(6.7f); + exp_release_rate[7] = ms_to_rate(13.0f); + exp_release_rate[8] = ms_to_rate(27.0f); + exp_release_rate[9] = ms_to_rate(53.0f); + exp_release_rate[10] = s_to_rate(0.11f); + exp_release_rate[11] = s_to_rate(0.21f); + exp_release_rate[12] = s_to_rate(0.43f); + exp_release_rate[13] = s_to_rate(0.86f); + exp_release_rate[14] = s_to_rate(1.7f); + exp_release_rate[15] = s_to_rate(3.4f); + exp_release_rate[16] = s_to_rate(6.8f); + exp_release_rate[17] = s_to_rate(14.0f); + exp_release_rate[18] = s_to_rate(27.0f); + exp_release_rate[19] = s_to_rate(55.0f); + exp_release_rate[20] = s_to_rate(109.0f); + exp_release_rate[21] = s_to_rate(219.0f); + exp_release_rate[22] = s_to_rate(438.0f); + exp_release_rate[23] = s_to_rate(876.0f); + exp_release_rate[24] = s_to_rate(1752.0f); + exp_release_rate[25] = s_to_rate(3504.0f); + exp_release_rate[26] = s_to_rate(7008.0f); +} + float spu_device::get_linear_rate(const int n) { - static constexpr int num_linear_rates=std::size(linear_rate); + int num_linear_rates=std::size(linear_rate); if (n>=num_linear_rates) return 0.0f; return linear_rate[n]*freq_multiplier; } @@ -630,7 +630,7 @@ float spu_device::get_linear_rate_neg_phase(const int n) float spu_device::get_pos_exp_rate(const int n) { - static constexpr int num_pos_exp_rates=std::size(pos_exp_rate); + int num_pos_exp_rates=std::size(pos_exp_rate); if (n>=num_pos_exp_rates) return 0.0f; return pos_exp_rate[n]*freq_multiplier; } @@ -643,7 +643,7 @@ float spu_device::get_pos_exp_rate_neg_phase(const int n) float spu_device::get_neg_exp_rate(const int n) { - static constexpr int num_neg_exp_rates=std::size(neg_exp_rate); + int num_neg_exp_rates=std::size(neg_exp_rate); if (n>=num_neg_exp_rates) return 0.0f; return -neg_exp_rate[n]*freq_multiplier; } @@ -666,14 +666,14 @@ float spu_device::get_sustain_level(const int n) float spu_device::get_linear_release_rate(const int n) { - static constexpr int num_linear_release_rates=std::size(linear_release_rate); + int num_linear_release_rates=std::size(linear_release_rate); if (n>=num_linear_release_rates) return 0.0f; return linear_release_rate[n]*freq_multiplier; } float spu_device::get_exp_release_rate(const int n) { - static constexpr int num_exp_release_rates=std::size(exp_release_rate); + int num_exp_release_rates=std::size(exp_release_rate); if (n>=num_exp_release_rates) return 0.0f; return exp_release_rate[n]*freq_multiplier; } diff --git a/src/mame/eolith/ghosteo.cpp b/src/mame/eolith/ghosteo.cpp index f8dc3a7fcd4..e10cac07d26 100644 --- a/src/mame/eolith/ghosteo.cpp +++ b/src/mame/eolith/ghosteo.cpp @@ -61,9 +61,9 @@ ToDo: verify QS1000 hook-up #include "cpu/arm7/arm7.h" #include "cpu/arm7/arm7core.h" #include "machine/gen_latch.h" -#include "machine/s3c2410.h" -//#include "machine/smartmed.h" #include "machine/i2cmem.h" +//#include "machine/nandflash.h" +#include "machine/s3c2410.h" #include "sound/qs1000.h" #include "emupal.h" @@ -642,8 +642,7 @@ void ghosteo_state::ghosteo(machine_config &config) m_s3c2410->nand_data_r_callback().set(FUNC(ghosteo_state::s3c2410_nand_data_r)); m_s3c2410->nand_data_w_callback().set(FUNC(ghosteo_state::s3c2410_nand_data_w)); -// nand_device &nand(NAND(config, "nand", 0)); -// nand.set_nand_type(nand_device::chip::K9F5608U0D); // or another variant with ID 0xEC 0x75 ? +// samsung_k9f5608u0d_device &nand(SAMSUNG_K9F5608U0D(config, "nand", 0)); // or another variant with ID 0xEC 0x75 ? // nand.rnb_wr_callback().set(m_s3c2410, FUNC(s3c2410_device::s3c24xx_pin_frnb_w)); I2C_24C16(config, "i2cmem", 0); // M24CL16-S diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 97a46ea87f7..b4c4002fa79 100755 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -32390,20 +32390,20 @@ valkyrie // (c) 1989 (Japan) @source:namco/namcos10.cpp chocovdr // 2002.10 Uchuu Daisakusen : Chocovader Contactee +g13jnc // 2001.?? Golgo 13: Juusei no Chinkonka (Japan, GLT1 VER.A) gamshara // 2002.08 Gamshara (10021 Ver.A) gamsharaj // 2002.08 Gamshara (10021 Ver.A) gegemdb // 2007.?? Gegege no Kitarō Yōkai Yokochō Matsuri De Batoru Ja (GYM1 Ver.A) gjspace // 2001.12 Gekitoride-Jong Space (10011 Ver.A) -g13jnc // 2001.?? Golgo 13: Juusei no Chinkonka (Japan, GLT1 VER.A) gunbalina // 2000.12 Gunbalina (GNN1 Ver.A) -keroro // 2006.?? Keroro Gunso Chikyu Shinryaku Shirei Dearimasu! (KRG1 Ver.A) kd2001 // 2001.1? Knock Down 2001 (KD11 Ver.B) +keroro // 2006.?? Keroro Gunso Chikyu Shinryaku Shirei Dearimasu! (KRG1 Ver.A) knpuzzle // 2001.12 Kotoba no Puzzle Mojipittan (KPM1 Ver.A) -konotako // 2003.?? Kono Tako (10021 Ver.A) -mrdrilr2 // 2000.07 Mr Driller 2 (DR21 Ver.A) +konotako // 2003.?? Kono e Tako (10021 Ver.A) +mrdrilr2 // 2000.?? Mr Driller 2 (DR22 Ver.A) +mrdrilr2j // 2000.07 Mr Driller 2 (DR21 Ver.A) mrdrilrg // 2001.03 Mr. Driller G (DRG1 Ver.A) mrdrilrga // 2001.03 Mr. Driller G ALT (DRG1 Ver.A) -mrdrlr2a // 2000.?? Mr Driller 2 (DR22 Ver.A) nflclsfb // 2003.?? NFL Classic Football pacmball // 2003.?? Pacman Ball panikuru // 2002.03 Panicuru Panekuru diff --git a/src/mame/misc/crospuzl.cpp b/src/mame/misc/crospuzl.cpp index a80f0f1bf97..d1126b215f2 100644 --- a/src/mame/misc/crospuzl.cpp +++ b/src/mame/misc/crospuzl.cpp @@ -370,8 +370,7 @@ void crospuzl_state::crospuzl(machine_config &config) // ROM strings have references to a K9FXX08 device // TODO: use this device, in machine/smartmed.h (has issues with is_busy() emulation) -// NAND(config, m_nand, 0); -// m_nand->set_nand_type(nand_device::chip::K9F1G08U0B); // TODO: exact flavor +// SAMSUNG_K9F1G08U0B(config, m_nand, 0); // TODO: exact flavor PCF8583(config, m_rtc, 32.768_kHz_XTAL); } diff --git a/src/mame/misc/hapyfish.cpp b/src/mame/misc/hapyfish.cpp index 0fd9a31dbba..2c48af73c5f 100644 --- a/src/mame/misc/hapyfish.cpp +++ b/src/mame/misc/hapyfish.cpp @@ -51,8 +51,8 @@ #include "emu.h" #include "cpu/arm7/arm7.h" +#include "machine/nandflash.h" #include "machine/s3c2440.h" -#include "machine/smartmed.h" #include "sound/dac.h" #include "screen.h" #include "speaker.h" @@ -89,7 +89,7 @@ public: private: required_device m_maincpu; required_device m_s3c2440; - required_device m_nand, m_nand2; + required_device m_nand, m_nand2; required_device m_ldac; required_device m_rdac; required_ioport_array<6> m_inputs; @@ -470,8 +470,6 @@ uint32_t hapyfish_state::s3c2440_adc_data_r() void hapyfish_state::machine_start() { - m_nand->set_data_ptr(memregion("nand")->base()); - m_nand2->set_data_ptr(memregion("nand2")->base()); m_nand_select = true; // select NAND #1 (S3C2440 bootloader will happen before machine_reset()) m_input_select = 7; } @@ -539,12 +537,10 @@ void hapyfish_state::hapyfish(machine_config &config) m_s3c2440->nand_data_r_callback().set(FUNC(hapyfish_state::s3c2440_nand_data_r)); m_s3c2440->nand_data_w_callback().set(FUNC(hapyfish_state::s3c2440_nand_data_w)); - NAND(config, m_nand, 0); - m_nand->set_nand_type(nand_device::chip::K9LAG08U0M); + SAMSUNG_K9LAG08U0M(config, m_nand, 0); m_nand->rnb_wr_callback().set(m_s3c2440, FUNC(s3c2440_device::frnb_w)); - NAND(config, m_nand2, 0); - m_nand2->set_nand_type(nand_device::chip::K9LAG08U0M); + SAMSUNG_K9LAG08U0M(config, m_nand2, 0); m_nand2->rnb_wr_callback().set(m_s3c2440, FUNC(s3c2440_device::frnb_w)); } diff --git a/src/mame/namco/namcos10.cpp b/src/mame/namco/namcos10.cpp index 6986db45c96..708039b2962 100644 --- a/src/mame/namco/namcos10.cpp +++ b/src/mame/namco/namcos10.cpp @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:smf +// copyright-holders:smf,windyfairy /*************************************************************************** Namco System 10 - Arcade PSX Hardware @@ -405,16 +405,35 @@ This PCB is required by Point Blank 3 since it controls the gun opto signal. Onl logic and other small support parts are populated. This PCB has been found almost fully populated (minus J6) on some Taiko no Tatsujin games (TK51/TK61) (and on Knock Down 2001) but not earlier TK games, so it appears to be optional or is only used by the later TK51 and TK61 games. + +----------- + +Note about the bit scramble order: +For MEM(N) games you can use 0x8508-0x8528 and for MEM(M) games you can use 0x108-0x128 to brute force the scramble order. +Those bytes correspond to the "Sony Computer Entertainment Inc." string in the BIOS. +Note: gjspace swaps between the entire 16-bit space but every other game I've tested swaps in an 8-bit space, +so you can try every permutation of 0-7 bit swaps separately very quickly (<1 sec) first but if that fails you will need to +try all permutations of 0-15 bit swaps which will take much longer or manually work through it. + + +Known issues: +- Opening the operator menu sometimes can crash Mr. Driller 2 +- nflclsfb: confirmed working but boots to a black screen. internal error says "namcoS10Sio0Init error :no EXIO!!!", making the check pass lets the game boot like normal */ #include "emu.h" + #include "ns10crypt.h" #include "cpu/psx/psx.h" #include "cpu/tlcs900/tmp95c061.h" +#include "machine/intelfsh.h" +#include "machine/nandflash.h" #include "machine/ram.h" -//#include "sound/spu.h" +#include "machine/timer.h" +#include "sound/spu.h" #include "video/psx.h" + #include "screen.h" #include "speaker.h" @@ -427,195 +446,349 @@ public: namcos10_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag) , m_maincpu(*this, "maincpu") - , m_exio_mcu(*this, "exio_mcu") - , m_memp3_mcu(*this, "memp3_mcu") - , decrypter(*this, "decrypter") + , m_decrypter(*this, "decrypter") + , m_io_update_interrupt(*this) + , m_io_system(*this, "SYSTEM") { } void namcos10_base(machine_config &config); + + void namcos10_map_inner(address_map &map); + void namcos10_map(address_map &map); + +protected: + using unscramble_func = uint16_t (*)(uint16_t); + + virtual void machine_start() override; + virtual void machine_reset() override; + virtual void device_resolve_objects() override; + + required_device m_maincpu; + optional_device m_decrypter; // not every game has a decrypter implemented yet, so optional for now + + unscramble_func m_unscrambler; + +private: + enum : int8_t { + I2CP_IDLE, + I2CP_RECIEVE_BYTE, + I2CP_RECIEVE_ACK_1, + I2CP_RECIEVE_ACK_0 + }; + + uint16_t control_r(offs_t offset); + void control_w(offs_t offset, uint16_t data); + + uint16_t sprot_r(); + void sprot_w(uint16_t data); + + uint16_t i2c_clock_r(); + void i2c_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + uint16_t i2c_data_r(); + void i2c_data_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + void i2c_update(); + + TIMER_DEVICE_CALLBACK_MEMBER(io_update_interrupt_callback); + + devcb_write_line m_io_update_interrupt; + + uint16_t m_i2c_host_clock, m_i2c_host_data, m_i2c_dev_clock, m_i2c_dev_data, m_i2c_prev_clock, m_i2c_prev_data; + int8_t m_i2cp_mode; + uint8_t m_i2c_byte; + int32_t m_i2c_bit; + + int32_t m_sprot_bit; + uint32_t m_sprot_byte; + + required_ioport m_io_system; +}; + +class namcos10_memm_state : public namcos10_state +{ +public: + namcos10_memm_state(const machine_config &mconfig, device_type type, const char *tag) + : namcos10_state(mconfig, type, tag) + , m_nand(*this, "nand") + { } + void namcos10_memm(machine_config &config); + + void ns10_mrdrilr2(machine_config &config); + + void init_mrdrilr2(); + +protected: + virtual void machine_start() override; + virtual void machine_reset() override; + +private: + void namcos10_memm_map_inner(address_map &map); + void namcos10_memm_map(address_map &map); + + void memm_driver_init(); + + void crypto_switch_w(uint16_t data); + uint16_t range_r(offs_t offset); + void nand_w(offs_t offset, uint16_t data); + uint16_t bank_r(offs_t offset); + void bank_w(offs_t offset, uint16_t data); + + void decrypt_bios_region(int start, int end); + + required_device m_nand; + + uint32_t m_bank_idx; + uint32_t m_bank_access_nand_direct; +}; + +class namcos10_memn_state : public namcos10_state +{ +public: + namcos10_memn_state(const machine_config &mconfig, device_type type, const char *tag) + : namcos10_state(mconfig, type, tag) + , m_nand(*this, "nand%u", 0U) + , m_exio_mcu(*this, "exio_mcu") + { } + + void namcos10_memn_base(machine_config &config); void namcos10_memn(machine_config &config); - void namcos10_memn_exio(machine_config &config); - void namcos10_memp3(machine_config &config); + + void namcos10_exio(machine_config &config); + void namcos10_mgexio(machine_config &config); + void namcos10_exfinalio(machine_config &config); + void ns10_konotako(machine_config &config); - void ns10_mrdrilr2(machine_config &config); void ns10_knpuzzle(machine_config &config); void ns10_chocovdr(machine_config &config); void ns10_startrgn(machine_config &config); void ns10_gjspace(machine_config &config); void ns10_nflclsfb(machine_config &config); void ns10_gamshara(machine_config &config); + void ns10_mrdrilrg(machine_config &config); + void ns10_kd2001(machine_config &config); + void ns10_ptblank3(machine_config &config); + void ns10_panikuru(machine_config &config); + void ns10_puzzball(machine_config &config); + void ns10_pacmball(machine_config &config); + void ns10_sekaikh(machine_config &config); + void ns10_taiko6(machine_config &config); + void ns10_keroro(machine_config &config); + void ns10_gegemdb(machine_config &config); + void ns10_unks10md(machine_config &config); + void ns10_unks10md2(machine_config &config); void init_knpuzzle(); void init_panikuru(); - void init_mrdrilr2(); void init_startrgn(); - void init_gunbalna(); + void init_gunbalina(); void init_nflclsfb(); void init_gjspace(); void init_gamshara(); void init_mrdrilrg(); void init_chocovdr(); void init_konotako(); + void init_taiko6(); + void init_puzzball(); + void init_pacmball(); + void init_sekaikh(); + void init_keroro(); + void init_unks10md(); + void init_unks10md2(); protected: virtual void machine_start() override; virtual void machine_reset() override; private: - // memm variant interface - void crypto_switch_w(uint16_t data); - uint16_t range_r(offs_t offset); - void bank_w(offs_t offset, uint16_t data); - - // memn variant interface - uint16_t nand_status_r(); - void nand_address1_w(uint8_t data); - void nand_address2_w(uint8_t data); - void nand_address3_w(uint8_t data); - void nand_address4_w(uint8_t data); - uint16_t nand_data_r(); - void nand_block_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t nand_block_r(offs_t offset); - - uint16_t control_r(offs_t offset); - void control_w(offs_t offset, uint16_t data); + void namcos10_memn_map_inner(address_map &map); + void namcos10_memn_map(address_map &map); - uint16_t i2c_clock_r(); - void i2c_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint16_t i2c_data_r(); - void i2c_data_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + void nand_copy(uint8_t *nand_base, uint16_t *dst, uint32_t address, int len); + void memn_driver_init(); - uint16_t sprot_r(); - void sprot_w(uint16_t data); + void crypto_switch_w(uint16_t data); + uint16_t ctrl_reg_r(offs_t offset); + void ctrl_reg_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + + uint16_t nand_rnb_r(); + void nand_cmd_w(uint8_t data); + void nand_address_column_w(uint8_t data); + void nand_address_row_w(uint8_t data); + void nand_address_page_w(uint8_t data); + uint16_t nand_data_r(); + void nand_data_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + void nand_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); - uint8_t *nand_base = nullptr; - void nand_copy( uint32_t *dst, uint32_t address, int len ); + optional_device_array m_nand; + optional_device m_exio_mcu; - void namcos10_map(address_map &map); - void namcos10_memm_map(address_map &map); - void namcos10_memn_map(address_map &map); + uint32_t m_ctrl_reg; + uint32_t m_nand_device_idx; + uint8_t m_nand_rnb_state[16]; + uint32_t m_nand_address; +}; - enum { - I2CP_IDLE, - I2CP_RECIEVE_BYTE, - I2CP_RECIEVE_ACK_1, - I2CP_RECIEVE_ACK_0 - }; +class namcos10_memp3_state : public namcos10_state +{ +public: + namcos10_memp3_state(const machine_config &mconfig, device_type type, const char *tag) + : namcos10_state(mconfig, type, tag) + , m_nand(*this, "nand%u", 0U) + , m_memp3_mcu(*this, "memp3_mcu") + { } - uint32_t bank_base = 0; - uint32_t nand_address = 0; - uint16_t block[0x1ff]{}; + void namcos10_memp3_base(machine_config &config); - uint16_t i2c_host_clock = 0, i2c_host_data = 0, i2c_dev_clock = 0, i2c_dev_data = 0, i2c_prev_clock = 0, i2c_prev_data = 0; - int i2cp_mode = 0; - uint8_t i2c_byte = 0; - int i2c_bit = 0; + void ns10_g13jnc(machine_config &config); - int sprot_bit = 0, sprot_byte = 0; - uint16_t nand_read( uint32_t address ); - uint16_t nand_read2( uint32_t address ); + void init_g13jnc(); - void i2c_update(); +private: + void nand_copy(uint8_t *nand_base, uint16_t *dst, uint32_t address, int len); + void memp3_driver_init(); - void memn_driver_init( ); - required_device m_maincpu; - optional_device m_exio_mcu; + optional_device_array m_nand; optional_device m_memp3_mcu; - optional_device decrypter; }; +/////////////////////////////////////////////////////////////////////////////////////////////// -void namcos10_state::machine_start() +void namcos10_state::namcos10_base(machine_config &config) { - nand_address = 0; -} + /* basic machine hardware */ + CXD8606BQ(config, m_maincpu, XTAL(101'491'200)); + m_maincpu->set_disable_rom_berr(true); + m_maincpu->subdevice("ram")->set_default_size("16M"); // ->set_default_size("4M"); 2 IS41LV16100s + // The bios first configures the ROM window as 80000-big, then + // switches to 400000. If berr is active, the first configuration + // wipes all handlers after 1fc80000, which kills the system + // afterwards + /* video hardware */ + CXD8561CQ(config, "gpu", XTAL(53'693'175), 0x200000, subdevice("maincpu")).set_screen("screen"); // 2 54V25632s -void namcos10_state::namcos10_map(address_map &map) -{ - map(0x1f500000, 0x1f501fff).ram().share("share3"); /* ram? stores block numbers */ - map(0x9f500000, 0x9f501fff).ram().share("share3"); /* ram? stores block numbers */ - map(0xbf500000, 0xbf501fff).ram().share("share3"); /* ram? stores block numbers */ + SCREEN(config, "screen", SCREEN_TYPE_RASTER); - map(0x1fba0000, 0x1fba000f).rw(FUNC(namcos10_state::control_r), FUNC(namcos10_state::control_w)); - map(0x1fba0002, 0x1fba0003).rw(FUNC(namcos10_state::sprot_r), FUNC(namcos10_state::sprot_w)); - map(0x1fba0008, 0x1fba0009).rw(FUNC(namcos10_state::i2c_clock_r), FUNC(namcos10_state::i2c_clock_w)); - map(0x1fba000a, 0x1fba000b).rw(FUNC(namcos10_state::i2c_data_r), FUNC(namcos10_state::i2c_data_w)); -} + /* sound hardware */ + SPEAKER(config, "lspeaker").front_left(); + SPEAKER(config, "rspeaker").front_right(); + // CXD2938Q; SPU with CD-ROM controller - also seen in PSone, 101.4912MHz / 2 + // TODO: This must be replaced with a proper CXD2938Q device, also handles CD-ROM? + spu_device &spu(SPU(config, "spu", XTAL(101'491'200)/2, m_maincpu.target())); + spu.add_route(0, "lspeaker", 1.0); + spu.add_route(1, "rspeaker", 1.0); -// memm variant interface -// -// banked view with dynamic decryption over the flash. Access to the -// nand is unknown, but may just be using the memn interface. Won't -// know until the decryption is done. -// -// bios copies 62000-37ffff from the flash to 80012000 in ram through the -// decryption in range_r then jumps there + // TODO: Trace main PCB to see where JAMMA I/O goes and/or how int10 can be triggered (SM10MA3?) + m_io_update_interrupt.bind().set("maincpu:irq", FUNC(psxirq_device::intin10)); + TIMER(config, "io_timer").configure_periodic(FUNC(namcos10_state::io_update_interrupt_callback), attotime::from_hz(100)); +} -void namcos10_state::crypto_switch_w(uint16_t data) +void namcos10_state::machine_start() { - printf("crypto_switch_w: %04x\n", data); - if (!decrypter.found()) - return; + save_item(NAME(m_i2c_dev_clock)); + save_item(NAME(m_i2c_dev_data)); + save_item(NAME(m_i2c_host_clock)); + save_item(NAME(m_i2c_host_data)); + save_item(NAME(m_i2c_prev_clock)); + save_item(NAME(m_i2c_prev_data)); + save_item(NAME(m_i2cp_mode)); + save_item(NAME(m_i2c_byte)); + save_item(NAME(m_i2c_bit)); + save_item(NAME(m_sprot_bit)); + save_item(NAME(m_sprot_byte)); +} - if (BIT(data, 15) != 0) - decrypter->activate(data & 0xf); - else - decrypter->deactivate(); +void namcos10_state::machine_reset() +{ + m_i2c_dev_clock = m_i2c_dev_data = 1; + m_i2c_host_clock = m_i2c_host_data = 1; + m_i2c_prev_clock = m_i2c_prev_data = 1; + m_i2cp_mode = I2CP_IDLE; + m_i2c_byte = 0x00; + m_i2c_bit = 0; + m_sprot_bit = 0; + m_sprot_byte = 0; } -void namcos10_state::bank_w(offs_t offset, uint16_t data) +void namcos10_state::device_resolve_objects() { - bank_base = 0x100000 * offset; + m_io_update_interrupt.resolve_safe(); } -uint16_t namcos10_state::range_r(offs_t offset) +TIMER_DEVICE_CALLBACK_MEMBER(namcos10_state::io_update_interrupt_callback) { - uint16_t data = ((const uint16_t *)(memregion("maincpu:rom")->base()))[bank_base+offset]; + m_io_update_interrupt(1); +} - if (!decrypter.found()) - return data; +void namcos10_state::namcos10_map_inner(address_map &map) +{ + // ram? stores block index to offset lookup table + map(0xf500000, 0xf5fffff).ram().share("share3"); + + map(0xfb60000, 0xfb60003).noprw(); // ? + map(0xfba0000, 0xfba001f).rw(FUNC(namcos10_state::control_r), FUNC(namcos10_state::control_w)); + map(0xfba0002, 0xfba0003).rw(FUNC(namcos10_state::sprot_r), FUNC(namcos10_state::sprot_w)); + map(0xfba0004, 0xfba0007).portr("IN1"); + map(0xfba0008, 0xfba0009).rw(FUNC(namcos10_state::i2c_clock_r), FUNC(namcos10_state::i2c_clock_w)); + map(0xfba000a, 0xfba000b).rw(FUNC(namcos10_state::i2c_data_r), FUNC(namcos10_state::i2c_data_w)); + + // TODO: Expansion I/O board registers (EXIO, etc) + // 0x1fe06000-1fe0ffff appears to be a memory space? 0xa000 bytes from the ROM is copied here. sub CPU program? + // 0x1fe0c65c = JVS data gets written here (e0 ff 03 f0 d9, etc) + // 0x1fe0c066 = status reg? + // 0x1fe0ca7c = JVS responses get read from here + // 0x1fe0c080 = must respond with 0 and then the packet length to read x + 3 bytes from JVS response??? + // 0x1fe0cea2 = needs to return 0 for exio to be seen as available + // 0x1fe0ce9c, 0x1fe0ce9e, 0x1fe0cea0, 0x1fe0ceb2 = cmd sent to exio + // 0x1fe18000 = set to 0 before reading/writing, set to 1 when done. Lock? + // 0x1fe28000 = sub CPU boot status flag, if 2 is not set then won't read response from sub CPU + // 0x1fe10000, 0x1fe20000, 0x1fe30000 are registers relating to the sub CPU +} - if (decrypter->is_active()) - return decrypter->decrypt(data); - else - return data; +void namcos10_state::namcos10_map(address_map &map) +{ + map(0x10000000, 0x1fffffff).m(FUNC(namcos10_memm_state::namcos10_map_inner)); + map(0x90000000, 0x9fffffff).m(FUNC(namcos10_memm_state::namcos10_map_inner)); + map(0xb0000000, 0xbfffffff).m(FUNC(namcos10_memm_state::namcos10_map_inner)); } uint16_t namcos10_state::control_r(offs_t offset) { - logerror("%s: control_r %d (%x)\n", machine().describe_context(), offset); - if(offset == 2) - return 1^0xffff; + // logerror("%s: control_r %d\n", machine().describe_context(), offset); + if(offset == 0) + return m_io_system->read(); + + if(offset == 13) { + // bit = cleared registers + // 0 = 1fba0012 + // 1 = 1fba0014, 1fe20000 + // 2 = 1fba0016 + // 3 = 1fba0018 (forces I/O update) + return 8; + } + return 0; } void namcos10_state::control_w(offs_t offset, uint16_t data) { - logerror("%s: control_w %d, %04x (%x)\n", machine().describe_context(), offset, data); + // logerror("%s: control_w %d, %04x\n", machine().describe_context(), offset, data); } void namcos10_state::sprot_w(uint16_t data) { - logerror("%s: sprot_w %04x (%x)\n", machine().describe_context(), data); - sprot_bit = 7; - sprot_byte = 0; + logerror("%s: sprot_w %04x\n", machine().describe_context(), data); + m_sprot_bit = 7; + m_sprot_byte = 0; } -// startrgn: -// 8004b6f8: jal 4b730, dies if v0!=0 (answers 1) -// flash access, unhappy with the results - -// 800128d8: jal 37b58 (flash death) -// 800128e0: jal 1649c -// 800128e8: jal 2c47c - uint16_t namcos10_state::sprot_r() { - // If line 3 has 0x30/0x31 in it, something happens. That - // something currently kills the system though. + // Seems to be some kind of system configuration read in as a response to the i2c commands sent? + // If line 3 has 0x30/0x31 then it will try to initialize the sub CPU for EXIO causing games to hang (waiting for 0x1fe18000 to return 0?). + // I/O will also try to poll 0x1fe50000 and 0x1fe58000. + // line 3 must return 0x31 to enable JVS for nflclsfb to run const static uint8_t prot[0x40] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, @@ -623,790 +796,1362 @@ uint16_t namcos10_state::sprot_r() 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x50, 0x51, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, }; - uint16_t res = sprot_byte >= 0x20 ? 0x3 : - (((prot[sprot_byte ] >> sprot_bit) & 1) ? 1 : 0) | - (((prot[sprot_byte+0x20] >> sprot_bit) & 1) ? 2 : 0); - - sprot_bit--; - if(sprot_bit == -1) { - sprot_bit = 7; - sprot_byte++; + uint16_t res = m_sprot_byte >= 0x20 ? 0x3 : + (((prot[m_sprot_byte ] >> m_sprot_bit) & 1) ? 1 : 0) | + (((prot[m_sprot_byte+0x20] >> m_sprot_bit) & 1) ? 2 : 0); + + m_sprot_bit--; + if(m_sprot_bit == -1) { + m_sprot_bit = 7; + m_sprot_byte++; } return res; } uint16_t namcos10_state::i2c_clock_r() { - uint16_t res = i2c_dev_clock & i2c_host_clock & 1; - // logerror("i2c_clock_r %d (%x)\n", res, m_maincpu->pc()); + uint16_t res = m_i2c_dev_clock & m_i2c_host_clock & 1; + // logerror("i2c_clock_r %d (%x)\n", res, m_maincpu->pc()); return res; } - void namcos10_state::i2c_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&i2c_host_clock); - // logerror("i2c_clock_w %d (%x)\n", data, m_maincpu->pc()); + COMBINE_DATA(&m_i2c_host_clock); + // logerror("i2c_clock_w %d (%x)\n", data, m_maincpu->pc()); i2c_update(); } uint16_t namcos10_state::i2c_data_r() { - uint16_t res = i2c_dev_data & i2c_host_data & 1; - // logerror("i2c_data_r %d (%x)\n", res, m_maincpu->pc()); + uint16_t res = m_i2c_dev_data & m_i2c_host_data & 1; + // logerror("i2c_data_r %d (%x)\n", res, m_maincpu->pc()); return res; } - void namcos10_state::i2c_data_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA(&i2c_host_data); - // logerror("i2c_data_w %d (%x)\n", data, m_maincpu->pc()); + COMBINE_DATA(&m_i2c_host_data); + // logerror("i2c_data_w %d (%x)\n", data, m_maincpu->pc()); i2c_update(); } void namcos10_state::i2c_update() { - uint16_t clock = i2c_dev_clock & i2c_host_clock & 1; - uint16_t data = i2c_dev_data & i2c_host_data & 1; + uint16_t clock = m_i2c_dev_clock & m_i2c_host_clock & 1; + uint16_t data = m_i2c_dev_data & m_i2c_host_data & 1; - if(i2c_prev_data == data && i2c_prev_clock == clock) + if(m_i2c_prev_data == data && m_i2c_prev_clock == clock) return; - switch(i2cp_mode) { + switch(m_i2cp_mode) { case I2CP_IDLE: if(clock && !data) { logerror("i2c: start bit\n"); - i2c_byte = 0; - i2c_bit = 7; - i2cp_mode = I2CP_RECIEVE_BYTE; + m_i2c_byte = 0; + m_i2c_bit = 7; + m_i2cp_mode = I2CP_RECIEVE_BYTE; } break; case I2CP_RECIEVE_BYTE: - if(clock && data && !i2c_prev_data) { + if(clock && data && !m_i2c_prev_data) { logerror("i2c stop bit\n"); - i2cp_mode = I2CP_IDLE; - } else if(clock && !i2c_prev_clock) { - i2c_byte |= (data << i2c_bit); - // logerror("i2c_byte = %02x (%d)\n", i2c_byte, i2c_bit); - i2c_bit--; - if(i2c_bit < 0) { - i2cp_mode = I2CP_RECIEVE_ACK_1; - logerror("i2c received byte %02x\n", i2c_byte); - i2c_dev_data = 0; + m_i2cp_mode = I2CP_IDLE; + } else if(clock && !m_i2c_prev_clock) { + m_i2c_byte |= (data << m_i2c_bit); + // logerror("i2c_byte = %02x (%d)\n", m_i2c_byte, m_i2c_bit); + m_i2c_bit--; + if(m_i2c_bit < 0) { + m_i2cp_mode = I2CP_RECIEVE_ACK_1; + logerror("i2c received byte %02x\n", m_i2c_byte); + m_i2c_dev_data = 0; data = 0; } } break; case I2CP_RECIEVE_ACK_1: - if(clock && !i2c_prev_clock) { - // logerror("i2c ack on\n"); - i2cp_mode = I2CP_RECIEVE_ACK_0; + if(clock && !m_i2c_prev_clock) { + // logerror("i2c ack on\n"); + m_i2cp_mode = I2CP_RECIEVE_ACK_0; } break; case I2CP_RECIEVE_ACK_0: - if(!clock && i2c_prev_clock) { - // logerror("i2c ack off\n"); - i2c_dev_data = 1; - data = i2c_host_data & 1; - i2c_byte = 0; - i2c_bit = 7; - i2cp_mode = I2CP_RECIEVE_BYTE; + if(!clock && m_i2c_prev_clock) { + // logerror("i2c ack off\n"); + m_i2c_dev_data = 1; + data = m_i2c_host_data & 1; + m_i2c_byte = 0; + m_i2c_bit = 7; + m_i2cp_mode = I2CP_RECIEVE_BYTE; } break; } - i2c_prev_data = data; - i2c_prev_clock = clock; + m_i2c_prev_data = data; + m_i2c_prev_clock = clock; } -void namcos10_state::namcos10_memm_map(address_map &map) + +/////////////////////////////////////////////////////////////////////////////////////////////// +// MEM(M) + +void namcos10_memm_state::crypto_switch_w(uint16_t data) { - namcos10_map(map); + logerror("%s: crypto_switch_w: %04x\n", machine().describe_context(), data); + if (!m_decrypter.found()) + return; - map(0x1f300000, 0x1f300001).w(FUNC(namcos10_state::crypto_switch_w)); - map(0x1f400000, 0x1f5fffff).r(FUNC(namcos10_state::range_r)); - map(0x1fb40000, 0x1fb4000f).w(FUNC(namcos10_state::bank_w)); + if (BIT(data, 15) != 0) + m_decrypter->activate(data & 0xf); + else + m_decrypter->deactivate(); } +uint16_t namcos10_memm_state::bank_r(offs_t offset) +{ + // Probably not correct but it works as a predictor + m_bank_access_nand_direct = 1; + return 0; +} -// memn variant interface -// -// Block access to the nand. Something strange is going on with the -// status port. Interaction with the decryption is unclear at best. +void namcos10_memm_state::bank_w(offs_t offset, uint16_t data) +{ + /* + Can address banks 0x00 to 0x1f + Bank 0x00-0x08 are mapped to the NAND + Bank 0x10-0x18 are mapped to .1d? + Bank 0x18-0x1f are mapped to .2e? + */ + + m_bank_idx = offset; + m_bank_access_nand_direct = offset >= 0x10; +} -uint16_t namcos10_state::nand_status_r() +uint16_t namcos10_memm_state::range_r(offs_t offset) { - return 0; + if (m_bank_access_nand_direct == 0) { + // Direct flash access + return m_nand->read((0x100000 * m_bank_idx) + offset); + } + + const uint16_t *bank_data; + if (m_bank_idx < 0x10) { + bank_data = &((uint16_t*)memregion("nand")->base())[0x100000 * m_bank_idx]; + } else { + bank_data = &((uint16_t*)memregion("data")->base())[0x100000 * (m_bank_idx - 0x10)]; + } + + uint16_t data = bank_data[offset]; + + if (m_decrypter.found() && m_decrypter->is_active()) + return m_decrypter->decrypt(data); + + if (m_bank_idx < 0x10) { + // TODO: Need more MEM(M) samples to verify if all of the data ROMs are unscrambled normally + data = m_unscrambler(data ^ 0xaaaa); + } + + return data; } -void namcos10_state::nand_address1_w(uint8_t data) +void namcos10_memm_state::nand_w(offs_t offset, uint16_t data) { - logerror("%s: nand_a1_w %08x (%08x)\n", machine().describe_context(), data); - // nand_address = ( nand_address & 0x00ffffff ) | ( data << 24 ); + if (m_bank_access_nand_direct != 0) + return; + + m_nand->write(offset, data); } -void namcos10_state::nand_address2_w(uint8_t data) +void namcos10_memm_state::namcos10_memm(machine_config &config) { - logerror("%s: nand_a2_w %08x (%08x)\n", machine().describe_context(), data); - nand_address = ( nand_address & 0xffffff00 ) | ( data << 0 ); + namcos10_base(config); + + // Can be an Intel 28F640J5 or a Sharp flash with a chip ID of 0xc0 + INTEL_28F640J5(config, m_nand); + + m_maincpu->set_addrmap(AS_PROGRAM, &namcos10_memm_state::namcos10_memm_map); } -void namcos10_state::nand_address3_w(uint8_t data) +void namcos10_memm_state::machine_start() { - logerror("%s: nand_a3_w %08x (%08x)\n", machine().describe_context(), data); - nand_address = ( nand_address & 0xffff00ff ) | ( data << 8 ); + namcos10_state::machine_start(); + + save_item(NAME(m_bank_idx)); + save_item(NAME(m_bank_access_nand_direct)); } -void namcos10_state::nand_address4_w(uint8_t data) +void namcos10_memm_state::machine_reset() { - nand_address = ( nand_address & 0xff00ffff ) | ( data << 16 ); - logerror("%s: nand_a4_w %08x (%08x) -> %08x\n", machine().describe_context(), data, nand_address*2); + namcos10_state::machine_reset(); + + m_bank_idx = 0; + m_bank_access_nand_direct = 0; } -uint16_t namcos10_state::nand_read( uint32_t address ) +void namcos10_memm_state::namcos10_memm_map_inner(address_map &map) { - int index = ( ( address / 512 ) * 528 ) + ( address % 512 ); - return nand_base[ index ] | ( nand_base[ index + 1 ] << 8 ); + // f210000 = if this returns 0xffff then it sets 1f801008 (EXP1 delay/size) and 1f80100c (EXP3 delay/size) + map(0xf300000, 0xf300001).w(FUNC(namcos10_memm_state::crypto_switch_w)); + map(0xf400000, 0xf5fffff).rw(FUNC(namcos10_memm_state::range_r), FUNC(namcos10_memm_state::nand_w)); + map(0xfb40000, 0xfb5ffff).rw(FUNC(namcos10_memm_state::bank_r), FUNC(namcos10_memm_state::bank_w)); } -uint16_t namcos10_state::nand_read2( uint32_t address ) +void namcos10_memm_state::namcos10_memm_map(address_map &map) { - int index = ( ( address / 512 ) * 528 ) + ( address % 512 ); - return nand_base[ index + 1 ] | ( nand_base[ index ] << 8 ); + namcos10_map(map); + + map(0x10000000, 0x1fffffff).m(FUNC(namcos10_memm_state::namcos10_memm_map_inner)); + map(0x90000000, 0x9fffffff).m(FUNC(namcos10_memm_state::namcos10_memm_map_inner)); + map(0xb0000000, 0xbfffffff).m(FUNC(namcos10_memm_state::namcos10_memm_map_inner)); } -uint16_t namcos10_state::nand_data_r() +void namcos10_memm_state::decrypt_bios_region(int start, int end) { - uint16_t data = nand_read2( nand_address * 2 ); + uint16_t *bios = (uint16_t *)(memregion("maincpu:rom")->base() + start); - // logerror("read %08x = %04x\n", nand_address*2, data); - // printf("read %08x = %04x\n", nand_address*2, data); + for(int i = start / 2; i < end / 2; i++) { + bios[i] = m_unscrambler(bios[i] ^ 0xaaaa); + } +} +void namcos10_memm_state::memm_driver_init() +{ + memcpy( + (uint8_t *)memregion("maincpu:rom")->base(), + (uint8_t *)memregion("nand")->base(), + 0x62000 + ); +} -/* printf( "data<-%08x (%08x)\n", data, nand_address ); */ - nand_address++; +void namcos10_memm_state::init_mrdrilr2() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3); }; + memm_driver_init(); + decrypt_bios_region(0, 0x62000); +} - if (!decrypter.found()) - return data; +void namcos10_memm_state::ns10_mrdrilr2(machine_config &config) +{ + namcos10_memm(config); + /* decrypter device (CPLD in hardware?) */ + MRDRILR2_DECRYPTER(config, m_decrypter, 0); +} - if (decrypter->is_active()) - return decrypter->decrypt(data); + +/////////////////////////////////////////////////////////////////////////////////////////////// +// MEM(N) + +uint16_t namcos10_memn_state::nand_rnb_r() +{ + return m_nand_rnb_state[m_nand_device_idx]; +} + +void namcos10_memn_state::crypto_switch_w(uint16_t data) +{ + logerror("%s: crypto_switch_w: %04x\n", machine().describe_context(), data); + if (!m_decrypter.found()) + return; + + if (BIT(data, 15) != 0) + m_decrypter->activate(data & 0xf); else - return data; + m_decrypter->deactivate(); +} + +void namcos10_memn_state::nand_cmd_w(uint8_t data) +{ + // TODO: Sometimes the upper byte is non-zero, why? + logerror("%s: nand_cmd_w %08x\n", machine().describe_context(), data); + if (m_nand[m_nand_device_idx]) + m_nand[m_nand_device_idx]->command_w(data & 0xff); +} + +void namcos10_memn_state::nand_address_column_w(uint8_t data) +{ + if (m_nand[m_nand_device_idx]) + m_nand[m_nand_device_idx]->address_w(data & 0xff); + m_nand_address = (m_nand_address & 0xffff00) | data; + logerror("%s: nand_address_column_w %02x %08x\n", machine().describe_context(), data, m_nand_address); +} + +void namcos10_memn_state::nand_address_row_w(uint8_t data) +{ + if (m_nand[m_nand_device_idx]) + m_nand[m_nand_device_idx]->address_w(data & 0xff); + m_nand_address = (m_nand_address & 0xff00ff) | (data << 8); + logerror("%s: nand_address_row_w %02x %08x\n", machine().describe_context(), data, m_nand_address); +} + +void namcos10_memn_state::nand_address_page_w(uint8_t data) +{ + if (m_nand[m_nand_device_idx]) + m_nand[m_nand_device_idx]->address_w(data & 0xff); + m_nand_address = (m_nand_address & 0x00ffff) | (data << 16); + logerror("%s: nand_address_page_w %02x %08x\n", machine().describe_context(), data, m_nand_address); } -void namcos10_state::nand_copy( uint32_t *dst, uint32_t address, int len ) +uint16_t namcos10_memn_state::nand_data_r() { - while( len > 0 ) + if (!m_nand[m_nand_device_idx]) + return 0xffff; + + uint16_t data = (m_nand[m_nand_device_idx]->data_r() << 8) + | m_nand[m_nand_device_idx]->data_r(); + + if (m_decrypter.found() && m_decrypter->is_active()) + return m_decrypter->decrypt(data); + + // There should never be scrambled data beyond 0x3ec + // Only the first device's beginning blocks are treated specially and can't contain scrambled data + // because it's guaranteed to always have important NAND layout information + EEP data + if ((BIT(m_nand_address, 8, 16) >> 5) < 0x3ec + && (m_nand_device_idx != 0 || (m_nand_device_idx == 0 && (BIT(m_nand_address, 8, 16) >> 5) >= 0x0a))) { - *( dst++ ) = nand_read( address ) | ( nand_read( address + 2 ) << 16 ); - address += 4; - len -= 4; + data = m_unscrambler(data ^ 0xaaaa); } + + return data; } -void namcos10_state::nand_block_w(offs_t offset, uint16_t data, uint16_t mem_mask) +void namcos10_memn_state::nand_data_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - COMBINE_DATA( &block[offset] ); + if (!m_nand[m_nand_device_idx]) + return; + + m_nand[m_nand_device_idx]->data_w(data >> 8); + m_nand[m_nand_device_idx]->data_w(data & 0xff); } -uint16_t namcos10_state::nand_block_r(offs_t offset) +void namcos10_memn_state::nand_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - return block[ offset ]; + logerror("%s: nand_bank_w: %04x %08x\n", machine().describe_context(), data, (data * 0x3ec) << 0x0e); + + if ((m_ctrl_reg & 4) == 0) + m_nand_device_idx = data; } -void namcos10_state::namcos10_memn_map(address_map &map) +void namcos10_memn_state::ctrl_reg_w(offs_t offset, uint16_t data, uint16_t mem_mask) { - namcos10_map(map); + // Set to 4 before using 1f410000-1f450000 registers and then set to 0 after it's finished. + // 4 is either a device lock kind of flag or maybe it controls direct NAND access? + // 2 has also been seen + logerror("%s ctrl_reg_w: %04x\n", machine().describe_context(), data); + m_ctrl_reg = data; +} - map(0x1f300000, 0x1f300001).w(FUNC(namcos10_state::crypto_switch_w)); - map(0x1f380000, 0x1f380001).w(FUNC(namcos10_state::crypto_switch_w)); - map(0x1f400000, 0x1f400001).r(FUNC(namcos10_state::nand_status_r)); - map(0x1f410000, 0x1f410000).w(FUNC(namcos10_state::nand_address1_w)); - map(0x1f420000, 0x1f420000).w(FUNC(namcos10_state::nand_address2_w)); - map(0x1f430000, 0x1f430000).w(FUNC(namcos10_state::nand_address3_w)); - map(0x1f440000, 0x1f440000).w(FUNC(namcos10_state::nand_address4_w)); - map(0x1f450000, 0x1f450001).r(FUNC(namcos10_state::nand_data_r)); - map(0x1fb60000, 0x1fb60001).rw(FUNC(namcos10_state::nand_block_r), FUNC(namcos10_state::nand_block_w)); +uint16_t namcos10_memn_state::ctrl_reg_r(offs_t offset) +{ + return m_ctrl_reg; } -void namcos10_state::memn_driver_init( ) +void namcos10_memn_state::namcos10_memn_base(machine_config &config) { - uint8_t *BIOS = (uint8_t *)memregion( "maincpu:rom" )->base(); - nand_base = (uint8_t *)memregion( "user2" )->base(); + namcos10_base(config); - nand_copy( (uint32_t *)( BIOS + 0x0000000 ), 0x08000, 0x001c000 ); - nand_copy( (uint32_t *)( BIOS + 0x0020000 ), 0x24000, 0x03e0000 ); + m_maincpu->set_addrmap(AS_PROGRAM, &namcos10_memn_state::namcos10_memn_map); } -static void decrypt_bios( running_machine &machine, const char *regionName, int start, int end, int b15, int b14, int b13, int b12, int b11, int b10, int b9, int b8, - int b7, int b6, int b5, int b4, int b3, int b2, int b1, int b0 ) +void namcos10_memn_state::namcos10_exio(machine_config &config) { - memory_region *region = machine.root_device().memregion( regionName ); - uint16_t *BIOS = (uint16_t *)( region->base() + start ); - int len = (end - start) / 2; + TMP95C061(config, m_exio_mcu, XTAL(22'118'400)).set_disable(); // not hooked up +} + +void namcos10_memn_state::namcos10_mgexio(machine_config &config) +{ + TMP95C061(config, m_exio_mcu, XTAL(22'118'400)).set_disable(); // not hooked up +} + +void namcos10_memn_state::namcos10_exfinalio(machine_config &config) +{ + TMP95C061(config, m_exio_mcu, XTAL(22'118'400)).set_disable(); // not hooked up +} + +void namcos10_memn_state::machine_start() +{ + namcos10_state::machine_start(); + + save_item(NAME(m_ctrl_reg)); + save_item(NAME(m_nand_device_idx)); + save_item(NAME(m_nand_address)); + save_item(NAME(m_nand_rnb_state)); +} + +void namcos10_memn_state::machine_reset() +{ + namcos10_state::machine_reset(); - for( int i = 0; i < len; i++ ) + m_ctrl_reg = 0; + m_nand_device_idx = 0; + m_nand_address = 0; + + std::fill(std::begin(m_nand_rnb_state), std::end(m_nand_rnb_state), 0); +} + +void namcos10_memn_state::namcos10_memn_map_inner(address_map &map) +{ + map(0xf300000, 0xf300001).w(FUNC(namcos10_memn_state::crypto_switch_w)); + map(0xf380000, 0xf380001).w(FUNC(namcos10_memn_state::crypto_switch_w)); + map(0xf400000, 0xf400001).r(FUNC(namcos10_memn_state::nand_rnb_r)); + map(0xf410000, 0xf410000).w(FUNC(namcos10_memn_state::nand_cmd_w)); + map(0xf420000, 0xf420000).w(FUNC(namcos10_memn_state::nand_address_column_w)); + map(0xf430000, 0xf430000).w(FUNC(namcos10_memn_state::nand_address_row_w)); + map(0xf440000, 0xf440000).w(FUNC(namcos10_memn_state::nand_address_page_w)); + map(0xf450000, 0xf450001).rw(FUNC(namcos10_memn_state::nand_data_r), FUNC(namcos10_memn_state::nand_data_w)); + map(0xf460000, 0xf460001).w(FUNC(namcos10_memn_state::nand_bank_w)); + map(0xf470000, 0xf470001).rw(FUNC(namcos10_memn_state::ctrl_reg_r), FUNC(namcos10_memn_state::ctrl_reg_w)); + //map(0xf480000, 0xf480001).w(); // 0xffff is written here after a nand write/erase? + // fb20000 something to do with DMAs? +} + +void namcos10_memn_state::namcos10_memn_map(address_map &map) +{ + namcos10_map(map); + + // konotako wants to access registers through 0xbf450000 so mirror the registers the way the PS1 normally + // mirrors these ranges + map(0x10000000, 0x1fffffff).m(FUNC(namcos10_memn_state::namcos10_memn_map_inner)); + map(0x90000000, 0x9fffffff).m(FUNC(namcos10_memn_state::namcos10_memn_map_inner)); + map(0xb0000000, 0xbfffffff).m(FUNC(namcos10_memn_state::namcos10_memn_map_inner)); +} + +void namcos10_memn_state::nand_copy(uint8_t *nand_base, uint16_t *dst, uint32_t start_page, int len) +{ + for (int page = start_page; page < start_page + len; page++) { - BIOS[ i ] = bitswap<16>( BIOS[ i ] ^ 0xaaaa, - b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5, b4, b3, b2, b1, b0 ); + int address = page * 0x210; + + for (int i = 0; i < 0x200; i += 2) { + uint16_t data = nand_base[address + i + 1] | (nand_base[address + i] << 8); + *dst = m_unscrambler(data ^ 0xaaaa); + dst++; + } } } -void namcos10_state::init_mrdrilr2() +void namcos10_memn_state::memn_driver_init() { - int regSize = memregion("maincpu:rom")->bytes(); + uint8_t *bios = (uint8_t *)memregion("maincpu:rom")->base(); + uint8_t *nand_base = (uint8_t *)memregion("nand0")->base(); - decrypt_bios(machine(), "maincpu:rom", 0, 0x62000, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3); - decrypt_bios(machine(), "maincpu:rom", 0x380000, regSize, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3); + nand_copy(nand_base, (uint16_t *)bios, 0x40, 0xe0); + nand_copy(nand_base, (uint16_t *)(bios + 0x0020000), 0x120, 0x1f00); } -void namcos10_state::init_gjspace() +void namcos10_memn_state::init_gjspace() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x0, 0x2, 0xe, 0xd, 0xf, 0x6, 0xc, 0x7, 0x5, 0x1, 0x9, 0x8, 0xa, 0x3, 0x4, 0xb); - decrypt_bios(machine(), "user2", 0x0210000, 0x104e800, 0x0, 0x2, 0xe, 0xd, 0xf, 0x6, 0xc, 0x7, 0x5, 0x1, 0x9, 0x8, 0xa, 0x3, 0x4, 0xb); - decrypt_bios(machine(), "user2", 0x1077c00, regSize, 0x0, 0x2, 0xe, 0xd, 0xf, 0x6, 0xc, 0x7, 0x5, 0x1, 0x9, 0x8, 0xa, 0x3, 0x4, 0xb); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0x8, 0xa, 0x6, 0x5, 0x7, 0xe, 0x4, 0xf, 0xd, 0x9, 0x1, 0x0, 0x2, 0xb, 0xc, 0x3); }; memn_driver_init(); } -void namcos10_state::init_mrdrilrg() +void namcos10_memn_state::init_mrdrilrg() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x8400, regSize, 0x6, 0x4, 0x7, 0x5, 0x2, 0x1, 0x0, 0x3, 0xc, 0xd, 0xe, 0xf, 0x8, 0x9, 0xb, 0xa); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xc, 0xf, 0xd, 0xa, 0x9, 0x8, 0xb, 0x4, 0x5, 0x6, 0x7, 0x0, 0x1, 0x3, 0x2); }; memn_driver_init(); } -void namcos10_state::init_knpuzzle() +void namcos10_memn_state::init_knpuzzle() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x6, 0x7, 0x4, 0x5, 0x2, 0x0, 0x3, 0x1, 0xc, 0xd, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa); - decrypt_bios(machine(), "user2", 0x047ac00, 0x1042200, 0x6, 0x7, 0x4, 0x5, 0x2, 0x0, 0x3, 0x1, 0xc, 0xd, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa); - decrypt_bios(machine(), "user2", 0x104a600, regSize , 0x6, 0x7, 0x4, 0x5, 0x2, 0x0, 0x3, 0x1, 0xc, 0xd, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xf, 0xc, 0xd, 0xa, 0x8, 0xb, 0x9, 0x4, 0x5, 0x6, 0x7, 0x1, 0x3, 0x0, 0x2); }; memn_driver_init(); } -void namcos10_state::init_startrgn() +void namcos10_memn_state::init_startrgn() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x00b9a00, 0x105ae00, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x1080000, regSize , 0x6, 0x7, 0x4, 0x5, 0x0, 0x1, 0x3, 0x2, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xd, 0xc, 0xf, 0x9, 0xb, 0x8, 0xa, 0x4, 0x5, 0x6, 0x7, 0x0, 0x3, 0x2, 0x1); }; memn_driver_init(); } -void namcos10_state::init_gamshara() +void namcos10_memn_state::init_gamshara() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb); - decrypt_bios(machine(), "user2", 0x014e200, 0x105ae00, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb); - decrypt_bios(machine(), "user2", 0x1080000, regSize , 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa, 0x5, 0x7, 0x4, 0x6, 0x0, 0x1, 0x2, 0x3); }; memn_driver_init(); } -void namcos10_state::init_gunbalna() +void namcos10_memn_state::init_gunbalina() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x8400, regSize, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x9, 0x8, 0xa, 0xb); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa, 0x5, 0x7, 0x4, 0x6, 0x1, 0x0, 0x2, 0x3); }; memn_driver_init(); } -void namcos10_state::init_chocovdr() +void namcos10_memn_state::init_chocovdr() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x5, 0x4, 0x6, 0x7, 0x1, 0x0, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x01eae00, 0x105ae00, 0x5, 0x4, 0x6, 0x7, 0x1, 0x0, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x1080000, regSize , 0x5, 0x4, 0x6, 0x7, 0x1, 0x0, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x8, 0xb, 0xa, 0x9); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xc, 0xe, 0xf, 0x9, 0x8, 0xa, 0xb, 0x4, 0x7, 0x6, 0x5, 0x0, 0x3, 0x2, 0x1); }; memn_driver_init(); } -void namcos10_state::init_panikuru() +void namcos10_memn_state::init_panikuru() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x8400, regSize, 0x6, 0x4, 0x7, 0x5, 0x0, 0x1, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x9, 0x8, 0xb, 0xa); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xc, 0xf, 0xd, 0x8, 0x9, 0xa, 0xb, 0x4, 0x7, 0x6, 0x5, 0x1, 0x0, 0x3, 0x2); }; memn_driver_init(); } -void namcos10_state::init_nflclsfb() +void namcos10_memn_state::init_nflclsfb() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x0214200, 0x105ae00, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9); - decrypt_bios(machine(), "user2", 0x1080000, regSize , 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xd, 0xc, 0xf, 0x9, 0xb, 0x8, 0xa, 0x4, 0x5, 0x6, 0x7, 0x0, 0x3, 0x2, 0x1); }; memn_driver_init(); } -void namcos10_state::init_konotako() +void namcos10_memn_state::init_konotako() { - int regSize = memregion("user2")->bytes(); - decrypt_bios(machine(), "user2", 0x0008400, 0x0029400, 0x6, 0x7, 0x4, 0x5, 0x0, 0x1, 0x3, 0x2, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa); - decrypt_bios(machine(), "user2", 0x00b9a00, 0x105ae00, 0x6, 0x7, 0x4, 0x5, 0x0, 0x1, 0x3, 0x2, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa); - decrypt_bios(machine(), "user2", 0x1080000, regSize , 0x6, 0x7, 0x4, 0x5, 0x0, 0x1, 0x3, 0x2, 0xd, 0xc, 0xf, 0xe, 0x8, 0x9, 0xb, 0xa); + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xf, 0xc, 0xd, 0x8, 0x9, 0xb, 0xa, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2); }; memn_driver_init(); } +void namcos10_memn_state::init_taiko6() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xc, 0xf, 0xd, 0x9, 0xb, 0x8, 0xa, 0x5, 0x4, 0x7, 0x6, 0x2, 0x1, 0x0, 0x3); }; + memn_driver_init(); +} -void namcos10_state::machine_reset() +void namcos10_memn_state::init_puzzball() { - i2c_dev_clock = i2c_dev_data = 1; - i2c_host_clock = i2c_host_data = 1; - i2c_prev_clock = i2c_prev_data = 1; - i2cp_mode = I2CP_IDLE; - i2c_byte = 0x00; - i2c_bit = 0; + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xc, 0xf, 0xe, 0xd, 0x8, 0x9, 0xa, 0xb, 0x4, 0x5, 0x7, 0x6, 0x1, 0x0, 0x2, 0x3); }; + memn_driver_init(); } -void namcos10_state::namcos10_base(machine_config &config) +void namcos10_memn_state::init_pacmball() { - /* basic machine hardware */ - CXD8606BQ(config, m_maincpu, XTAL(101'491'200)); - m_maincpu->set_disable_rom_berr(true); - m_maincpu->subdevice("ram")->set_default_size("16M"); // ->set_default_size("4M"); 2 IS41LV16100s - // The bios first configures the ROM window as 80000-big, then - // switches to 400000. If berr is active, the first configuration - // wipes all handlers after 1fc80000, which kills the system - // afterwards + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xf, 0xc, 0xe, 0x8, 0xb, 0xa, 0x9, 0x4, 0x5, 0x7, 0x6, 0x0, 0x3, 0x2, 0x1); }; + memn_driver_init(); +} - /* video hardware */ - CXD8561CQ(config, "gpu", XTAL(53'693'175), 0x200000, subdevice("maincpu")).set_screen("screen"); // 2 54V25632s +void namcos10_memn_state::init_sekaikh() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xc, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa, 0x6, 0x5, 0x4, 0x7, 0x2, 0x3, 0x0, 0x1); }; + memn_driver_init(); +} - SCREEN(config, "screen", SCREEN_TYPE_RASTER); +void namcos10_memn_state::init_keroro() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xf, 0xc, 0xd, 0xa, 0x8, 0xb, 0x9, 0x4, 0x5, 0x7, 0x6, 0x2, 0x1, 0x0, 0x3); }; + memn_driver_init(); +} - /* sound hardware */ - SPEAKER(config, "lspeaker").front_left(); - SPEAKER(config, "rspeaker").front_right(); +void namcos10_memn_state::init_unks10md() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb, 0x5, 0x4, 0x6, 0x7, 0x2, 0x3, 0x0, 0x1); }; + memn_driver_init(); +} - // CXD2938Q; SPU with CD-ROM controller - also seen in PSone, 101.4912MHz / 3? +void namcos10_memn_state::init_unks10md2() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xd, 0xc, 0xe, 0xf, 0xa, 0xb, 0x8, 0x9, 0x5, 0x4, 0x6, 0x7, 0x1, 0x3, 0x0, 0x2); }; + memn_driver_init(); } -void namcos10_state::namcos10_memm(machine_config &config) +void namcos10_memn_state::ns10_chocovdr(machine_config &config) { - namcos10_base(config); - m_maincpu->set_addrmap(AS_PROGRAM, &namcos10_state::namcos10_memm_map); + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + CHOCOVDR_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 5; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::namcos10_memn(machine_config &config) +void namcos10_memn_state::ns10_gamshara(machine_config &config) { - namcos10_base(config); - m_maincpu->set_addrmap(AS_PROGRAM, &namcos10_state::namcos10_memn_map); + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + GAMSHARA_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::namcos10_memn_exio(machine_config &config) +void namcos10_memn_state::ns10_gjspace(machine_config &config) { - namcos10_memn(config); - TMP95C061(config, m_exio_mcu, XTAL(22'118'400)).set_disable(); // not hooked up + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + GJSPACE_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 4; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::namcos10_memp3(machine_config &config) +void namcos10_memn_state::ns10_knpuzzle(machine_config &config) { - namcos10_memn(config); - TMP95C061(config, m_memp3_mcu, XTAL(16'934'400)).set_disable(); // not hooked up - // LC82310 16.9344MHz + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + KNPUZZLE_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 3; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_mrdrilr2(machine_config &config) +void namcos10_memn_state::ns10_konotako(machine_config &config) { - namcos10_memm(config); + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - MRDRILR2_DECRYPTER(config, "decrypter", 0); + KONOTAKO_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_chocovdr(machine_config &config) +void namcos10_memn_state::ns10_nflclsfb(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + namcos10_exio(config); + /* decrypter device (CPLD in hardware?) */ - CHOCOVDR_DECRYPTER(config, "decrypter", 0); + NFLCLSFB_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 4; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_gamshara(machine_config &config) +void namcos10_memn_state::ns10_startrgn(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - GAMSHARA_DECRYPTER(config, "decrypter", 0); + STARTRGN_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_gjspace(machine_config &config) +void namcos10_memn_state::ns10_mrdrilrg(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - GJSPACE_DECRYPTER(config, "decrypter", 0); + // MRDRILRG_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 3; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_kd2001(machine_config &config) +{ + namcos10_memn_base(config); + + // TODO: Also has a "pdrive" ROM? What's that for? + + /* decrypter device (CPLD in hardware?) */ + // KD2001_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_ptblank3(machine_config &config) +{ + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + // PTBLANK3_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_panikuru(machine_config &config) +{ + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + // PANIKURU_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 3; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_knpuzzle(machine_config &config) +void namcos10_memn_state::ns10_puzzball(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - KNPUZZLE_DECRYPTER(config, "decrypter", 0); + // PUZZBALL_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_konotako(machine_config &config) +void namcos10_memn_state::ns10_pacmball(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + + /* decrypter device (CPLD in hardware?) */ + // PACMBALL_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_sekaikh(machine_config &config) +{ + namcos10_memn_base(config); + namcos10_mgexio(config); + + /* decrypter device (CPLD in hardware?) */ + // SEKAIKH_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_taiko6(machine_config &config) +{ + namcos10_memn_base(config); + namcos10_exfinalio(config); + + /* decrypter device (CPLD in hardware?) */ + // TAIKO6_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 3; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_keroro(machine_config &config) +{ + namcos10_memn_base(config); + namcos10_exio(config); + + /* decrypter device (CPLD in hardware?) */ + // KERORO_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + // Uses a larger NAND chip than any of the others + SAMSUNG_K9F5608U0D(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_gegemdb(machine_config &config) +{ + namcos10_memn_base(config); + namcos10_exio(config); + + /* decrypter device (CPLD in hardware?) */ + // GEGEMDB_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + // Uses a larger NAND chip than any of the others + SAMSUNG_K9F5608U0D(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + +void namcos10_memn_state::ns10_unks10md(machine_config &config) +{ + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - KONOTAKO_DECRYPTER(config, "decrypter", 0); + // UNKS10MD_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } -void namcos10_state::ns10_nflclsfb(machine_config &config) +void namcos10_memn_state::ns10_unks10md2(machine_config &config) { - namcos10_memn(config); + namcos10_memn_base(config); + /* decrypter device (CPLD in hardware?) */ - NFLCLSFB_DECRYPTER(config, "decrypter", 0); + // UNKS10MD2_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 2; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } +} + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// MEM(P3) + +void namcos10_memp3_state::nand_copy(uint8_t *nand_base, uint16_t *dst, uint32_t start_page, int len) +{ + for (int page = start_page; page < start_page + len; page++) + { + int address = page * 0x210; + + for (int i = 0; i < 0x200; i += 2) { + uint16_t data = nand_base[address + i + 1] | (nand_base[address + i] << 8); + *dst = m_unscrambler(data ^ 0xaaaa); + dst++; + } + } +} + +void namcos10_memp3_state::memp3_driver_init() +{ + uint8_t *bios = (uint8_t *)memregion("maincpu:rom")->base(); + uint8_t *nand_base = (uint8_t *)memregion("nand0")->base(); + + nand_copy(nand_base, (uint16_t *)bios, 0x40, 0xe0); + nand_copy(nand_base, (uint16_t *)(bios + 0x0020000), 0x120, 0x1f00); +} + +void namcos10_memp3_state::namcos10_memp3_base(machine_config &config) +{ + namcos10_base(config); + + TMP95C061(config, m_memp3_mcu, XTAL(16'934'400)).set_disable(); // not hooked up + // LC82310 16.9344MHz +} + +void namcos10_memp3_state::init_g13jnc() +{ + m_unscrambler = [] (uint16_t data) { return bitswap<16>(data, 0xe, 0xd, 0xc, 0xf, 0x9, 0xb, 0x8, 0xa, 0x6, 0x7, 0x4, 0x5, 0x1, 0x3, 0x0, 0x2); }; + memp3_driver_init(); } -void namcos10_state::ns10_startrgn(machine_config &config) +void namcos10_memp3_state::ns10_g13jnc(machine_config &config) { - namcos10_memn(config); + namcos10_memp3_base(config); + /* decrypter device (CPLD in hardware?) */ - STARTRGN_DECRYPTER(config, "decrypter", 0); + // G13JNC_DECRYPTER(config, m_decrypter, 0); + + for (int i = 0; i < 6; i++) { + SAMSUNG_K9F2808U0B(config, m_nand[i], 0); + // m_nand[i]->rnb_wr_callback().set([this, i] (int state) { m_nand_rnb_state[i] = state != 1; }); + } } +/////////////////////////////////////////////////////////////////////////////////////////////// + static INPUT_PORTS_START( namcos10 ) - /* IN 0 */ PORT_START("SYSTEM") - PORT_SERVICE_NO_TOGGLE( 0x8000, IP_ACTIVE_HIGH ) - PORT_BIT( 0x7fff, IP_ACTIVE_HIGH, IPT_UNUSED ) - - /* IN 1 */ - PORT_START("P1") - PORT_BIT( 0x8000, IP_ACTIVE_HIGH, IPT_START1 ) - PORT_DIPSETTING( 0x0000, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x8000, DEF_STR( On ) ) - PORT_BIT( 0x4000, IP_ACTIVE_HIGH, IPT_SERVICE1 ) - PORT_DIPSETTING( 0x0000, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x4000, DEF_STR( On ) ) - PORT_BIT( 0x2000, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY - PORT_BIT( 0x1000, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY - PORT_BIT( 0x0800, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY - PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY - PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_BUTTON1 ) - PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_BUTTON2 ) - PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_BUTTON3 ) - PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_BUTTON4 ) - PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_BUTTON5 ) - PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_BUTTON6 ) - PORT_BIT( 0x000f, IP_ACTIVE_HIGH, IPT_UNUSED ) - - /* IN 2 */ - PORT_START("P2") - PORT_BIT( 0x8000, IP_ACTIVE_HIGH, IPT_START2 ) - PORT_DIPSETTING( 0x0000, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x8000, DEF_STR( On ) ) - PORT_BIT( 0x4000, IP_ACTIVE_HIGH, IPT_SERVICE2 ) - PORT_DIPSETTING( 0x0000, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x4000, DEF_STR( On ) ) - PORT_BIT( 0x2000, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) - PORT_BIT( 0x1000, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) - PORT_BIT( 0x0800, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) - PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) - PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) - PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2) - PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2) - PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_PLAYER(2) - PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_PLAYER(2) - PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_PLAYER(2) - PORT_BIT( 0x000f, IP_ACTIVE_HIGH, IPT_UNUSED ) - - /* IN 3 */ - PORT_START("COINS") - PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 ) + PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNUSED ) + // TODO: 0x400 might be required for extension boards + PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "DIP SW:8" ) + PORT_DIPUNKNOWN_DIPLOC( 0x02, IP_ACTIVE_LOW, "DIP SW:7" ) + PORT_DIPUNKNOWN_DIPLOC( 0x04, IP_ACTIVE_LOW, "DIP SW:6" ) + PORT_DIPUNKNOWN_DIPLOC( 0x08, IP_ACTIVE_LOW, "DIP SW:5" ) + PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "DIP SW:4" ) + PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "DIP SW:3" ) + PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "DIP SW:2" ) + PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "DIP SW:1" ) + + PORT_START("IN1") + PORT_BIT( 0x0f110000, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) + PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) + PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) + PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) + PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) + PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) + PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) + PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_START1 ) + PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1) + PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1) + PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1) + + PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) + PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) + PORT_BIT( 0x00000400, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) + PORT_BIT( 0x00000800, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) + PORT_BIT( 0x00001000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) + PORT_BIT( 0x00002000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) + PORT_BIT( 0x00004000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) + PORT_BIT( 0x00008000, IP_ACTIVE_LOW, IPT_START2 ) + PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2) + PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(2) + PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2) + + PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_COIN2 ) + PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Test SW + PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_SERVICE1 ) + INPUT_PORTS_END +static INPUT_PORTS_START( mrdrilr2 ) + PORT_INCLUDE(namcos10) -ROM_START( mrdrilr2 ) - ROM_REGION32_LE( 0x800000, "maincpu:rom", 0 ) /* main prg */ - ROM_LOAD( "dr21vera.1a", 0x000000, 0x800000, CRC(f93532a2) SHA1(8b72f2868978be1f0e0abd11425a3c8b2b0c4e99) ) + PORT_MODIFY("IN1") + PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1) + PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1) + PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1) + PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(1) + PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2) + PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2) + PORT_BIT( 0x00000400, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2) + PORT_BIT( 0x00000800, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(2) + +INPUT_PORTS_END + +static INPUT_PORTS_START( gamshara ) + PORT_INCLUDE(namcos10) + + PORT_MODIFY("IN1") + PORT_BIT( 0x0fff0000, IP_ACTIVE_LOW, IPT_UNUSED ) // Disable P1 and P2 4-6 buttons + +INPUT_PORTS_END + +static INPUT_PORTS_START( startrgn ) + PORT_INCLUDE(namcos10) + + PORT_MODIFY("IN1") + PORT_BIT( 0x0fffff6f, IP_ACTIVE_LOW, IPT_UNUSED ) // This game only uses 1 button and start, no P2 at all + +INPUT_PORTS_END + +static INPUT_PORTS_START( konotako ) + PORT_INCLUDE(namcos10) + + PORT_MODIFY("IN1") + PORT_BIT( 0x1fff4040, IP_ACTIVE_LOW, IPT_UNUSED ) + +INPUT_PORTS_END - ROM_REGION( 0x4000000, "user2", 0 ) /* main prg */ +static INPUT_PORTS_START( nflclsfb ) + PORT_INCLUDE(namcos10) + + // TODO: Trackball (EXIO) + // TODO: IN1 controls, can't find all inputs + // 0x00000080 right side decide + // 0x00000008 select up + // 0x00000004 select down + // 0x00000002 left side choose l + // 0x00000001 left side choose r + // 0x00000010 enter + // 0x00000020 start 1p + // 0x00000040 start 2p + // 0x00008000 left side decide + // 0x00000200 left side choose r + // 0x00000100 right side choose r + // 0x00002000 start 3p + // 0x00004000 start 4p + +INPUT_PORTS_END + +// MEM(M) +ROM_START( mrdrilr2j ) + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) + ROM_FILL( 0x0000000, 0x400000, 0x55 ) + + ROM_REGION32_LE( 0x800000, "nand", 0 ) + ROM_LOAD( "dr21vera.1a", 0x000000, 0x800000, CRC(f93532a2) SHA1(8b72f2868978be1f0e0abd11425a3c8b2b0c4e99) ) + + ROM_REGION( 0x2000000, "data", 0 ) ROM_LOAD( "dr21ma1.1d", 0x0000000, 0x1000000, CRC(26dc6f55) SHA1(a9cedf547fa7a4d5850b9b3b867d46e577a035e0) ) ROM_LOAD( "dr21ma2.2d", 0x1000000, 0x1000000, CRC(702556ff) SHA1(c95defd5fd6a9b406fc8d8f28ecfab732ef1ff42) ) ROM_END -ROM_START( mrdrlr2a ) - ROM_REGION32_LE( 0x800000, "maincpu:rom", 0 ) /* main prg */ - ROM_LOAD( "dr22vera.1a", 0x000000, 0x800000, CRC(f2633388) SHA1(42e56c9758ee833390003d4b41956f75f5a22760) ) +ROM_START( mrdrilr2 ) + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) + ROM_FILL( 0x0000000, 0x400000, 0x55 ) + + ROM_REGION32_LE( 0x800000, "nand", 0 ) + ROM_LOAD( "dr22vera.1a", 0x000000, 0x800000, CRC(f2633388) SHA1(42e56c9758ee833390003d4b41956f75f5a22760) ) - ROM_REGION( 0x4000000, "user2", 0 ) /* main prg */ + ROM_REGION( 0x2000000, "data", 0 ) ROM_LOAD( "dr21ma1.1d", 0x0000000, 0x1000000, CRC(26dc6f55) SHA1(a9cedf547fa7a4d5850b9b3b867d46e577a035e0) ) ROM_LOAD( "dr21ma2.2d", 0x1000000, 0x1000000, CRC(702556ff) SHA1(c95defd5fd6a9b406fc8d8f28ecfab732ef1ff42) ) ROM_END + +// MEM(N) ROM_START( gjspace ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x4200000, "user2", 0 ) /* main prg */ + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) ROM_LOAD( "10011a_0.bin", 0x0000000, 0x1080000, CRC(df862033) SHA1(4141357ed315adb4de636d7bf752354e953e8cbf) ) - ROM_LOAD( "10011a_1.bin", 0x1080000, 0x1080000, CRC(734c7ac0) SHA1(2f325236a4e4f2dba886682e9a7e8e243b5fbb3d) ) - ROM_LOAD( "10011a_2.bin", 0x2100000, 0x1080000, CRC(3bbbc0b7) SHA1(ad02ec2e5f401f0f5d40a413038649ebd25d5343) ) - ROM_LOAD( "10011a_3.bin", 0x3180000, 0x1080000, CRC(fb0de5ca) SHA1(50a462a52ff4a0bc112b9d89f2b2d032c60cf59c) ) -ROM_END + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "10011a_1.bin", 0x0000000, 0x1080000, CRC(734c7ac0) SHA1(2f325236a4e4f2dba886682e9a7e8e243b5fbb3d) ) -ROM_START( g13jnc ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ - ROM_FILL( 0x0000000, 0x400000, 0x55 ) + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "10011a_2.bin", 0x0000000, 0x1080000, CRC(3bbbc0b7) SHA1(ad02ec2e5f401f0f5d40a413038649ebd25d5343) ) - ROM_REGION16_LE( 0x6300000, "user2", 0 ) /* main prg */ - ROM_LOAD( "glt1_ver.a.0", 0x0000000, 0x1080000, CRC(e60f78d3) SHA1(5c876ac7366b5c46b5229a6b6f694ad222f36195) ) - ROM_LOAD( "glt1_ver.a.1", 0x1080000, 0x1080000, CRC(c3f31dd9) SHA1(05e6d39f33191979bcc00a585b64904a077000dc) ) - ROM_LOAD( "glt1_ver.a.2", 0x2100000, 0x1080000, CRC(e464e03a) SHA1(751f6bd753dacbb881fb47bc1b146ef59245bd10) ) - ROM_LOAD( "glt1_ver.a.3", 0x3180000, 0x1080000, CRC(f7486979) SHA1(a44c33ae7004e79fe66c6d2cba3d11671ce2582c) ) - ROM_LOAD( "glt1_ver.a.4", 0x4200000, 0x1080000, CRC(e39969b4) SHA1(3348839c0cc4a4bcaa7803ef22981420c527e1a4) ) - ROM_LOAD( "glt1_ver.a.5", 0x5280000, 0x1080000, CRC(a82800b4) SHA1(ce4cc479acdf7ac5a7237d07422ea3ee580d899a) ) + ROM_REGION32_LE( 0x1080000, "nand3", 0 ) + ROM_LOAD( "10011a_3.bin", 0x0000000, 0x1080000, CRC(fb0de5ca) SHA1(50a462a52ff4a0bc112b9d89f2b2d032c60cf59c) ) ROM_END ROM_START( mrdrilrg ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x3180000, "user2", 0 ) /* main prg */ - ROM_LOAD( "drg1a_0.bin", 0x0000000, 0x1080000, CRC(e0801878) SHA1(fbb771c1e76e0690f6dffed2287eb470b561ec20) ) - ROM_LOAD( "drg1a_1.bin", 0x1080000, 0x1080000, CRC(4d8cde73) SHA1(62a5fab8be8fd0a6bfeb101020d4cf58866a757c) ) - ROM_LOAD( "drg1a_2.bin", 0x2100000, 0x1080000, CRC(ccfabf7b) SHA1(0cbd91ce8abd6efca5d427b52279ce265f685aa9) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "drg1a_0.bin", 0x0000000, 0x1080000, CRC(e0801878) SHA1(fbb771c1e76e0690f6dffed2287eb470b561ec20) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "drg1a_1.bin", 0x0000000, 0x1080000, CRC(4d8cde73) SHA1(62a5fab8be8fd0a6bfeb101020d4cf58866a757c) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "drg1a_2.bin", 0x0000000, 0x1080000, CRC(ccfabf7b) SHA1(0cbd91ce8abd6efca5d427b52279ce265f685aa9) ) ROM_END ROM_START( mrdrilrga ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x3180000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(def72bcd) SHA1(e243b7ef23b2b00612c185e01493cd01be51f154) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(c87b5e86) SHA1(b034210da30e1f2f7d04f77e00bf7724437e2024) ) - ROM_LOAD( "2.7e", 0x2100000, 0x1080000, CRC(e0a9339f) SHA1(4284e7233876cfaf8021440d78ccc8c70d00cc00) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(def72bcd) SHA1(e243b7ef23b2b00612c185e01493cd01be51f154) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(c87b5e86) SHA1(b034210da30e1f2f7d04f77e00bf7724437e2024) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "2.7e", 0x0000000, 0x1080000, CRC(e0a9339f) SHA1(4284e7233876cfaf8021440d78ccc8c70d00cc00) ) ROM_END ROM_START( knpuzzle ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x3180000, "user2", 0 ) /* main prg */ - ROM_LOAD( "kpm1a_0.bin", 0x0000000, 0x1080000, CRC(b2947eb8) SHA1(fa941bf3598bb25d2c8f0a93154e32bf78a6507c) ) - ROM_LOAD( "kpm1a_1.bin", 0x1080000, 0x1080000, CRC(f3aa855a) SHA1(87b94e22db4bc4169324bbff93c4ea19c1d99b40) ) - ROM_LOAD( "kpm1a_2.bin", 0x2100000, 0x1080000, CRC(b297cc8d) SHA1(c3494e7a8a0b4e0c8c40b99121373effbfe848eb) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "kpm1a_0.bin", 0x0000000, 0x1080000, CRC(b2947eb8) SHA1(fa941bf3598bb25d2c8f0a93154e32bf78a6507c) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "kpm1a_1.bin", 0x0000000, 0x1080000, CRC(f3aa855a) SHA1(87b94e22db4bc4169324bbff93c4ea19c1d99b40) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "kpm1a_2.bin", 0x0000000, 0x1080000, CRC(b297cc8d) SHA1(c3494e7a8a0b4e0c8c40b99121373effbfe848eb) ) ROM_END ROM_START( startrgn ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "stt1a_0.bin", 0x0000000, 0x1080000, CRC(1e090644) SHA1(a7a293e2bd9eea2eb64a492a47272d9d9ee2c724) ) - ROM_LOAD( "stt1a_1.bin", 0x1080000, 0x1080000, CRC(aa527694) SHA1(a25dcbeca58a1443070848b3487a24d51d41a34b) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "stt1a_0.bin", 0x0000000, 0x1080000, CRC(1e090644) SHA1(a7a293e2bd9eea2eb64a492a47272d9d9ee2c724) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "stt1a_1.bin", 0x0000000, 0x1080000, CRC(aa527694) SHA1(a25dcbeca58a1443070848b3487a24d51d41a34b) ) ROM_END ROM_START( gamshara ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "10021a_e.8e", 0x0000000, 0x1080000, CRC(684ab324) SHA1(95c2e0a04c4f33039535fc451c5559d239b8fbc6) ) - ROM_LOAD( "10021a.8d", 0x1080000, 0x1080000, CRC(73669ff7) SHA1(eb8bbf931f1f8a049208d081d040512a3ffa9c00) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "10021a_e.8e", 0x0000000, 0x1080000, CRC(684ab324) SHA1(95c2e0a04c4f33039535fc451c5559d239b8fbc6) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "10021a.8d", 0x0000000, 0x1080000, CRC(73669ff7) SHA1(eb8bbf931f1f8a049208d081d040512a3ffa9c00) ) ROM_END ROM_START( gamsharaj ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "10021a.8e", 0x0000000, 0x1080000, CRC(6c0361fc) SHA1(7debf1f2e6bed31d59fb224a78a17a94fc573785) ) - ROM_LOAD( "10021a.8d", 0x1080000, 0x1080000, CRC(73669ff7) SHA1(eb8bbf931f1f8a049208d081d040512a3ffa9c00) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "10021a.8e", 0x0000000, 0x1080000, CRC(6c0361fc) SHA1(7debf1f2e6bed31d59fb224a78a17a94fc573785) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "10021a.8d", 0x0000000, 0x1080000, CRC(73669ff7) SHA1(eb8bbf931f1f8a049208d081d040512a3ffa9c00) ) ROM_END ROM_START( ptblank3 ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) // protection issues preventing the last NAND block to be dumped ROM_LOAD("gnn2a.8e", 0x0000000, 0x1080000, BAD_DUMP CRC(31b39221) SHA1(7fcb14aaa26c531928a6cd704e746d0e3ae3e031)) - ROM_LOAD( "gnn2a.8d", 0x1080000, 0x1080000, BAD_DUMP CRC(82d2cfb5) SHA1(4b5e713a55e74a7b32b1b9b5811892df2df86256) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "gnn2a.8d", 0x0000000, 0x1080000, BAD_DUMP CRC(82d2cfb5) SHA1(4b5e713a55e74a7b32b1b9b5811892df2df86256) ) ROM_END ROM_START( gunbalina ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) // protection issues preventing the last NAND block to be dumped - ROM_LOAD( "gnn1a.8e", 0x0000000, 0x1080000, BAD_DUMP CRC(981b03d4) SHA1(1c55458f1b2964afe2cf4e9d84548c0699808e9f) ) - ROM_LOAD( "gnn1a.8d", 0x1080000, 0x1080000, BAD_DUMP CRC(6cd343e0) SHA1(dcec44abae1504025895f42fe574549e5010f7d5) ) + ROM_LOAD( "gnn1a.8e", 0x0000000, 0x1080000, BAD_DUMP CRC(981b03d4) SHA1(1c55458f1b2964afe2cf4e9d84548c0699808e9f) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "gnn1a.8d", 0x0000000, 0x1080000, BAD_DUMP CRC(6cd343e0) SHA1(dcec44abae1504025895f42fe574549e5010f7d5) ) ROM_END ROM_START( chocovdr ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x5280000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(f36eebb5) SHA1(a0464186b247b28f37005ffd9e9b7370145f67ef) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(4aecd6fc) SHA1(31fe8f36e38020a92f15c44fd1a4b486636b40ce) ) - ROM_LOAD( "2.7e", 0x2100000, 0x1080000, CRC(ac212e5a) SHA1(f2d2e65a3249992730b8b90561b9bcf5eaaafb88) ) - ROM_LOAD( "3.7d", 0x3180000, 0x1080000, CRC(907d3d15) SHA1(20519d1f8bd9c6bc45b65e2d7444d588e922611d) ) - ROM_LOAD( "4.6e", 0x4200000, 0x1080000, CRC(1ed957dd) SHA1(bc8ce9f249fe496c130c6fe67b2260c4d0734ab9) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(f36eebb5) SHA1(a0464186b247b28f37005ffd9e9b7370145f67ef) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(4aecd6fc) SHA1(31fe8f36e38020a92f15c44fd1a4b486636b40ce) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "2.7e", 0x0000000, 0x1080000, CRC(ac212e5a) SHA1(f2d2e65a3249992730b8b90561b9bcf5eaaafb88) ) + + ROM_REGION32_LE( 0x1080000, "nand3", 0 ) + ROM_LOAD( "3.7d", 0x0000000, 0x1080000, CRC(907d3d15) SHA1(20519d1f8bd9c6bc45b65e2d7444d588e922611d) ) + + ROM_REGION32_LE( 0x1080000, "nand4", 0 ) + ROM_LOAD( "4.6e", 0x0000000, 0x1080000, CRC(1ed957dd) SHA1(bc8ce9f249fe496c130c6fe67b2260c4d0734ab9) ) ROM_END ROM_START( panikuru ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x3180000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(3aa66da4) SHA1(3f6ff164981e2c1825766c775442608fbf86d702) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(18e5135d) SHA1(a7b1533a1df71be5498718e301d1c9c548551fb4) ) - ROM_LOAD( "2.7e", 0x2100000, 0x1080000, CRC(cd3b25e0) SHA1(39dfebc59e71b8f1c28e718ee71032620f11440c) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(3aa66da4) SHA1(3f6ff164981e2c1825766c775442608fbf86d702) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(18e5135d) SHA1(a7b1533a1df71be5498718e301d1c9c548551fb4) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "2.7e", 0x0000000, 0x1080000, CRC(cd3b25e0) SHA1(39dfebc59e71b8f1c28e718ee71032620f11440c) ) ROM_END ROM_START( nflclsfb ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x4200000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(b08d4270) SHA1(5f5dc1c2862292a9e597f6a21c0f9db2e5796ded) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(d3f519d8) SHA1(60d5f2fafd700e39245bed17e3cc6d608cc2c088) ) - ROM_LOAD( "2.7e", 0x2100000, 0x1080000, CRC(0c65fdc2) SHA1(fa5d41a7b10ae8f8d312b61cc6d34408123bda97) ) - ROM_LOAD( "3.7d", 0x3180000, 0x1080000, CRC(0a4e601d) SHA1(9c302a0b5aaf7046390982e62092b867c3a534a5) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(b08d4270) SHA1(5f5dc1c2862292a9e597f6a21c0f9db2e5796ded) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(d3f519d8) SHA1(60d5f2fafd700e39245bed17e3cc6d608cc2c088) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "2.7e", 0x0000000, 0x1080000, CRC(0c65fdc2) SHA1(fa5d41a7b10ae8f8d312b61cc6d34408123bda97) ) + + ROM_REGION32_LE( 0x1080000, "nand3", 0 ) + ROM_LOAD( "3.7d", 0x0000000, 0x1080000, CRC(0a4e601d) SHA1(9c302a0b5aaf7046390982e62092b867c3a534a5) ) ROM_END ROM_START( konotako ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x4200000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(63d23a0c) SHA1(31b54119f20827ff13ecf0cd87803a5e27eaafe7) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(bdbed53c) SHA1(5773069c43642e6f334cee185a6fb6908eedcf4a) ) + ROM_REGION16_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(63d23a0c) SHA1(31b54119f20827ff13ecf0cd87803a5e27eaafe7) ) + + ROM_REGION16_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(bdbed53c) SHA1(5773069c43642e6f334cee185a6fb6908eedcf4a) ) ROM_END ROM_START( sekaikh ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(b0cc4a4f) SHA1(41974931901090811e07f18c04e2af853c308f88) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(65c4a8b4) SHA1(c7fefc32604bb47519a05cdb6c8b0f50034e0efd) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(b0cc4a4f) SHA1(41974931901090811e07f18c04e2af853c308f88) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(65c4a8b4) SHA1(c7fefc32604bb47519a05cdb6c8b0f50034e0efd) ) ROM_REGION( 0x8000, "mgexio", 0 ) ROM_LOAD( "m48z35y.ic11", 0x0000, 0x8000, CRC(e0e52ffc) SHA1(557490e2f286773a945851f44ed0214de731cd75) ) ROM_END ROM_START( sekaikha ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(e32c36ac) SHA1(d762723b6ecf65c8cb7c85c25d9a1fbbcdcfd27a) ) - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(7cb38ece) SHA1(e21fbc9ff09ca51e1857e32318b95107ae4b3f0b) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, CRC(e32c36ac) SHA1(d762723b6ecf65c8cb7c85c25d9a1fbbcdcfd27a) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(7cb38ece) SHA1(e21fbc9ff09ca51e1857e32318b95107ae4b3f0b) ) ROM_REGION( 0x8000, "mgexio", 0 ) ROM_LOAD( "m48z35y.ic11", 0x0000, 0x8000, CRC(e0e52ffc) SHA1(557490e2f286773a945851f44ed0214de731cd75) ) ROM_END ROM_START( taiko6 ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x3180000, "user2", 0 ) /* main prg */ - ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(a87352c9) SHA1(1816fabecfaa140da2cd46334701c3e2fb93258e) ) - ROM_LOAD( "k9f2808u0c.8d", 0x1080000, 0x1080000, CRC(e89aa7a3) SHA1(c34d693f4715ce930dbd105eda1ffc8379991c22) ) - ROM_LOAD( "k9f2808u0c.7e", 0x2100000, 0x1080000, CRC(098920ef) SHA1(06a689d8abb8454ed62dda92d93a8f5d756a6166) ) - - DISK_REGION("cd") - DISK_IMAGE_READONLY( "tk-6", 0, SHA1(ca8b8dfccc2022094c428b5e0b6391a77ec351f4) ) -ROM_END - -ROM_START( unks10md ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ - ROM_FILL( 0x0000000, 0x400000, 0x55 ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(a87352c9) SHA1(1816fabecfaa140da2cd46334701c3e2fb93258e) ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(b8ce45c6) SHA1(cfc85e796e32f5f3cc16e12ce902f0ae088eea31) ) - ROM_LOAD( "k9f2808u0c.8d", 0x1080000, 0x1080000, CRC(49a2a732) SHA1(1a473177827a6d0e58c289d9af064665b941519b) ) -ROM_END + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "k9f2808u0c.8d", 0x0000000, 0x1080000, CRC(e89aa7a3) SHA1(c34d693f4715ce930dbd105eda1ffc8379991c22) ) -ROM_START( unks10md2 ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ - ROM_FILL( 0x0000000, 0x400000, 0x55 ) + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "k9f2808u0c.7e", 0x0000000, 0x1080000, CRC(098920ef) SHA1(06a689d8abb8454ed62dda92d93a8f5d756a6166) ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(53b3e255) SHA1(6e5a3addb859023d8c7e53237acf9f028c85f57b) ) - ROM_LOAD( "k9f2808u0c.8d", 0x1080000, 0x1080000, CRC(a0ad9504) SHA1(43e9e83b0340dd2e0f28ff9ccd3667db4e70951a) ) + DISK_REGION("cd") + DISK_IMAGE_READONLY( "tk-6", 0, SHA1(ca8b8dfccc2022094c428b5e0b6391a77ec351f4) ) ROM_END ROM_START( kd2001 ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "0.8e", 0x0000000, 0x1080000, NO_DUMP ) // broken flash ROM, couldn't be dumped - ROM_LOAD( "1.8d", 0x1080000, 0x1080000, CRC(2b0d0e8c) SHA1(d679e7044e1f93bb7bd449e6d8fcb7737d154025) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "0.8e", 0x0000000, 0x1080000, NO_DUMP ) // broken flash ROM, couldn't be dumped + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "1.8d", 0x0000000, 0x1080000, CRC(2b0d0e8c) SHA1(d679e7044e1f93bb7bd449e6d8fcb7737d154025) ) ROM_REGION( 0x20000, "pdrivecpu", 0 ) ROM_LOAD( "kd11-dr0-ic10.bin", 0x00000, 0x20000, CRC(59649293) SHA1(71c3a0e73d077398e7f3d95acedc47814e99fbc6) ) ROM_END ROM_START( keroro ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x4200000, "user2", 0 ) /* main prg */ - ROM_LOAD( "krg1.8e", 0x0000000, 0x2100000, CRC(12e78c66) SHA1(83573f68f27ace345a3be16f29f874f14e593233) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen - ROM_LOAD( "krg1.8d", 0x2100000, 0x2100000, CRC(879a87b7) SHA1(fcef8eb9423b4825bf27fbfe8cae6d4018cb534f) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen + ROM_REGION32_LE( 0x2100000, "nand0", 0 ) + ROM_LOAD( "krg1.8e", 0x0000000, 0x2100000, CRC(12e78c66) SHA1(83573f68f27ace345a3be16f29f874f14e593233) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen + + ROM_REGION32_LE( 0x2100000, "nand1", 0 ) + ROM_LOAD( "krg1.8d", 0x0000000, 0x2100000, CRC(879a87b7) SHA1(fcef8eb9423b4825bf27fbfe8cae6d4018cb534f) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen ROM_END ROM_START( gegemdb ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x4200000, "user2", 0 ) /* main prg */ - ROM_LOAD( "gym1.8e", 0x0000000, 0x2100000, CRC(ea740351) SHA1(4dc7ce256a2d60be512d04a992b2103602bcfaa9) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen - ROM_LOAD( "gym1.8d", 0x2100000, 0x2100000, CRC(0145a8c1) SHA1(a32dd944d022df14450bbcb01b4d1712683c0680) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen + // gym1.8e appears to be interleaved, none of the other larger NAND chip dumps look like this. Highly suspected to be a bad dump. + ROM_REGION32_LE( 0x2100000, "nand0", 0 ) + ROM_LOAD( "gym1.8e", 0x0000000, 0x2100000, BAD_DUMP CRC(ea740351) SHA1(4dc7ce256a2d60be512d04a992b2103602bcfaa9) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen + + ROM_REGION32_LE( 0x2100000, "nand1", 0 ) + ROM_LOAD( "gym1.8d", 0x0000000, 0x2100000, CRC(0145a8c1) SHA1(a32dd944d022df14450bbcb01b4d1712683c0680) ) // K9F5608U0D, double sized wrt to the other games and PCB silkscreen ROM_REGION( 0x8000, "nvram", 0 ) ROM_LOAD( "nvram.bin", 0x0000, 0x8000, CRC(c0c87c71) SHA1(263f7f3df772644bcf973413d3fac9ae305fda6c) ) ROM_END ROM_START( pacmball ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(7b6f814d) SHA1(728167866d9350150b5fd9ebcf8fe7280efedb91) ) - ROM_LOAD( "k9f2808u0c.8d", 0x1080000, 0x1080000, CRC(f79d7199) SHA1(4ef9b758ee778e12f7fef717e063597299fb8219) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(7b6f814d) SHA1(728167866d9350150b5fd9ebcf8fe7280efedb91) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "k9f2808u0c.8d", 0x0000000, 0x1080000, CRC(f79d7199) SHA1(4ef9b758ee778e12f7fef717e063597299fb8219) ) ROM_END ROM_START( puzzball ) - ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) /* bios */ + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) + ROM_FILL( 0x0000000, 0x400000, 0x55 ) + + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(ca6642a7) SHA1(550891c80feaf2c1b262f420cf90946419319640) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "k9f2808u0c.8d", 0x0000000, 0x1080000, CRC(b13f6f45) SHA1(66917476de5417596a9d3b9169ea74d93f3037fe) ) +ROM_END + + +// MEM(P3) +ROM_START( g13jnc ) + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) ROM_FILL( 0x0000000, 0x400000, 0x55 ) - ROM_REGION16_LE( 0x2100000, "user2", 0 ) /* main prg */ - ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(ca6642a7) SHA1(550891c80feaf2c1b262f420cf90946419319640) ) - ROM_LOAD( "k9f2808u0c.8d", 0x1080000, 0x1080000, CRC(b13f6f45) SHA1(66917476de5417596a9d3b9169ea74d93f3037fe) ) + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "glt1_ver.a.0", 0x0000000, 0x1080000, CRC(e60f78d3) SHA1(5c876ac7366b5c46b5229a6b6f694ad222f36195) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "glt1_ver.a.1", 0x0000000, 0x1080000, CRC(c3f31dd9) SHA1(05e6d39f33191979bcc00a585b64904a077000dc) ) + + ROM_REGION32_LE( 0x1080000, "nand2", 0 ) + ROM_LOAD( "glt1_ver.a.2", 0x0000000, 0x1080000, CRC(e464e03a) SHA1(751f6bd753dacbb881fb47bc1b146ef59245bd10) ) + + ROM_REGION32_LE( 0x1080000, "nand3", 0 ) + ROM_LOAD( "glt1_ver.a.3", 0x0000000, 0x1080000, CRC(f7486979) SHA1(a44c33ae7004e79fe66c6d2cba3d11671ce2582c) ) + + ROM_REGION32_LE( 0x1080000, "nand4", 0 ) + ROM_LOAD( "glt1_ver.a.4", 0x0000000, 0x1080000, CRC(e39969b4) SHA1(3348839c0cc4a4bcaa7803ef22981420c527e1a4) ) + + ROM_REGION32_LE( 0x1080000, "nand5", 0 ) + ROM_LOAD( "glt1_ver.a.5", 0x0000000, 0x1080000, CRC(a82800b4) SHA1(ce4cc479acdf7ac5a7237d07422ea3ee580d899a) ) +ROM_END + + +// Unknown +ROM_START( unks10md ) + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) + ROM_FILL( 0x0000000, 0x400000, 0x55 ) + + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(b8ce45c6) SHA1(cfc85e796e32f5f3cc16e12ce902f0ae088eea31) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "k9f2808u0c.8d", 0x0000000, 0x1080000, CRC(49a2a732) SHA1(1a473177827a6d0e58c289d9af064665b941519b) ) +ROM_END + +ROM_START( unks10md2 ) + ROM_REGION32_LE( 0x400000, "maincpu:rom", 0 ) + ROM_FILL( 0x0000000, 0x400000, 0x55 ) + + ROM_REGION32_LE( 0x1080000, "nand0", 0 ) + ROM_LOAD( "k9f2808u0c.8e", 0x0000000, 0x1080000, CRC(53b3e255) SHA1(6e5a3addb859023d8c7e53237acf9f028c85f57b) ) + + ROM_REGION32_LE( 0x1080000, "nand1", 0 ) + ROM_LOAD( "k9f2808u0c.8d", 0x0000000, 0x1080000, CRC(a0ad9504) SHA1(43e9e83b0340dd2e0f28ff9ccd3667db4e70951a) ) ROM_END } // Anonymous namespace -GAME( 2000, mrdrilr2, 0, ns10_mrdrilr2, namcos10, namcos10_state, init_mrdrilr2, ROT0, "Namco", "Mr. Driller 2 (Japan, DR21 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // PORT_4WAY joysticks -GAME( 2000, mrdrlr2a, mrdrilr2, ns10_mrdrilr2, namcos10, namcos10_state, init_mrdrilr2, ROT0, "Namco", "Mr. Driller 2 (World, DR22 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // PORT_4WAY joysticks -GAME( 2000, ptblank3, 0, namcos10_memn_exio, namcos10, namcos10_state, init_gunbalna, ROT0, "Namco", "Point Blank 3 (World, GNN2 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // needs to hookup gun IO -GAME( 2000, gunbalina, ptblank3, namcos10_memn_exio, namcos10, namcos10_state, init_gunbalna, ROT0, "Namco", "Gunbalina (Japan, GNN1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // "" -GAME( 2001, gjspace, 0, ns10_gjspace, namcos10, namcos10_state, init_gjspace, ROT0, "Namco / Metro", "Gekitoride-Jong Space (10011 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2001, g13jnc, 0, namcos10_memp3, namcos10, namcos10_state, empty_init, ROT0, "Eighting / Raizing / Namco", "Golgo 13: Juusei no Chinkonka (Japan, GLT1 VER.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2001, mrdrilrg, 0, namcos10_memn, namcos10, namcos10_state, init_mrdrilrg, ROT0, "Namco", "Mr. Driller G (Japan, DRG1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // PORT_4WAY joysticks -GAME( 2001, mrdrilrga, mrdrilrg, namcos10_memn, namcos10, namcos10_state, init_mrdrilrg, ROT0, "Namco", "Mr. Driller G ALT (Japan, DRG1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // PORT_4WAY joysticks -GAME( 2001, knpuzzle, 0, ns10_knpuzzle, namcos10, namcos10_state, init_knpuzzle, ROT0, "Namco", "Kotoba no Puzzle Mojipittan (Japan, KPM1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2001, kd2001, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Knock Down 2001 (Japan, KD11 Ver. B)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2002, chocovdr, 0, ns10_chocovdr, namcos10, namcos10_state, init_chocovdr, ROT0, "Namco", "Uchuu Daisakusen: Chocovader Contactee (Japan, CVC1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2002, startrgn, 0, ns10_startrgn, namcos10, namcos10_state, init_startrgn, ROT0, "Namco", "Star Trigon (Japan, STT1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2002, panikuru, 0, namcos10_memn, namcos10, namcos10_state, init_panikuru, ROT0, "Namco", "Panicuru Panekuru (Japan, PPA1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2002, gamshara, 0, ns10_gamshara, namcos10, namcos10_state, init_gamshara, ROT0, "Mitchell", "Gamshara (World, 10021 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Ver. 20020912A ETC -GAME( 2002, gamsharaj, gamshara, ns10_gamshara, namcos10, namcos10_state, init_gamshara, ROT0, "Mitchell", "Gamshara (Japan, 10021 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2002, puzzball, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Puzz Ball (Japan, PZB1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // title guessed based on known game list and PCB sticker -GAME( 2003, nflclsfb, 0, ns10_nflclsfb, namcos10, namcos10_state, init_nflclsfb, ROT0, "Namco", "NFL Classic Football (US, NCF3 Ver.A.)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2003, pacmball, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Pacman BALL (PMB2 Ver.A.)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) -GAME( 2003, konotako, 0, ns10_konotako, namcos10, namcos10_state, init_konotako, ROT0, "Mitchell", "Kono Tako (10021 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2004, sekaikh, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Sekai Kaseki Hakken (Japan, SKH1 Ver.B)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2004, sekaikha, sekaikh, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Sekai Kaseki Hakken (Japan, SKH1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2004, taiko6, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Taiko no Tatsujin 6 (Japan, TK61 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) -GAME( 2005, unks10md2, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "unknown Namco System 10 medal game (unknown code)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // ROM VER. B0 FEB 09 2005 15:29:02 in test mode -GAME( 2006, keroro, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Keroro Gunso Chikyu Shinryaku Shirei Dearimasu! (KRG1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // ケロロ軍曹　地球侵略指令…であります！ -GAME( 2007, gegemdb, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "Gegege no Kitaro Yokai Yokocho Matsuri De Batoru Ja (GYM1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // ゲゲゲの鬼太郎　妖怪横丁まつりでバトルじゃ -GAME( 200?, unks10md, 0, namcos10_memn, namcos10, namcos10_state, empty_init, ROT0, "Namco", "unknown Namco System 10 medal game (MTL1 SPR0B)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) +// MEM(M) +GAME( 2000, mrdrilr2, 0, ns10_mrdrilr2, mrdrilr2, namcos10_memm_state, init_mrdrilr2, ROT0, "Namco", "Mr. Driller 2 (World, DR22 Ver.A)", 0 ) +GAME( 2000, mrdrilr2j, mrdrilr2, ns10_mrdrilr2, mrdrilr2, namcos10_memm_state, init_mrdrilr2, ROT0, "Namco", "Mr. Driller 2 (Japan, DR21 Ver.A)", 0 ) + +// MEM(N) +GAME( 2000, ptblank3, 0, ns10_ptblank3, namcos10, namcos10_memn_state, init_gunbalina, ROT0, "Namco", "Point Blank 3 (World, GNN2 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // needs to hookup gun IO +GAME( 2000, gunbalina, ptblank3, ns10_ptblank3, namcos10, namcos10_memn_state, init_gunbalina, ROT0, "Namco", "Gunbalina (Japan, GNN1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // "" +GAME( 2001, gjspace, 0, ns10_gjspace, namcos10, namcos10_memn_state, init_gjspace, ROT0, "Namco / Metro", "Gekitoride-Jong Space (10011 Ver.A)", MACHINE_NOT_WORKING ) // broken decrypter? +GAME( 2001, mrdrilrg, 0, ns10_mrdrilrg, mrdrilr2, namcos10_memn_state, init_mrdrilrg, ROT0, "Namco", "Mr. Driller G (Japan, DRG1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2001, mrdrilrga, mrdrilrg, ns10_mrdrilrg, mrdrilr2, namcos10_memn_state, init_mrdrilrg, ROT0, "Namco", "Mr. Driller G (Japan, DRG1 Ver.A, set 2)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2001, knpuzzle, 0, ns10_knpuzzle, namcos10, namcos10_memn_state, init_knpuzzle, ROT0, "Namco", "Kotoba no Puzzle Mojipittan (Japan, KPM1 Ver.A)", MACHINE_NOT_WORKING ) +GAME( 2001, kd2001, 0, ns10_kd2001, namcos10, namcos10_memn_state, empty_init, ROT0, "Namco", "Knock Down 2001 (Japan, KD11 Ver. B)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2002, chocovdr, 0, ns10_chocovdr, namcos10, namcos10_memn_state, init_chocovdr, ROT0, "Namco", "Uchuu Daisakusen: Chocovader Contactee (Japan, CVC1 Ver.A)", 0 ) +GAME( 2002, startrgn, 0, ns10_startrgn, startrgn, namcos10_memn_state, init_startrgn, ROT0, "Namco", "Star Trigon (Japan, STT1 Ver.A)", 0) +GAME( 2002, panikuru, 0, ns10_panikuru, namcos10, namcos10_memn_state, init_panikuru, ROT0, "Namco", "Panicuru Panekuru (Japan, PPA1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2002, gamshara, 0, ns10_gamshara, gamshara, namcos10_memn_state, init_gamshara, ROT0, "Mitchell", "Gamshara (World, 10021 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // Ver. 20020912A ETC +GAME( 2002, gamsharaj, gamshara, ns10_gamshara, gamshara, namcos10_memn_state, init_gamshara, ROT0, "Mitchell", "Gamshara (Japan, 10021 Ver.A)", 0 ) +GAME( 2002, puzzball, 0, ns10_puzzball, namcos10, namcos10_memn_state, init_puzzball, ROT0, "Namco", "Puzz Ball (Japan, PZB1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // title guessed based on known game list and PCB sticker +GAME( 2003, nflclsfb, 0, ns10_nflclsfb, nflclsfb, namcos10_memn_state, init_nflclsfb, ROT0, "Namco", "NFL Classic Football (US, NCF3 Ver.A.)", MACHINE_NOT_WORKING ) +GAME( 2003, pacmball, 0, ns10_pacmball, namcos10, namcos10_memn_state, init_pacmball, ROT0, "Namco", "Pacman BALL (PMB2 Ver.A.)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2003, konotako, 0, ns10_konotako, konotako, namcos10_memn_state, init_konotako, ROT0, "Mitchell", "Kono e Tako (10021 Ver.A)", 0) +GAME( 2004, sekaikh, 0, ns10_sekaikh, namcos10, namcos10_memn_state, init_sekaikh, ROT0, "Namco", "Sekai Kaseki Hakken (Japan, SKH1 Ver.B)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2004, sekaikha, sekaikh, ns10_sekaikh, namcos10, namcos10_memn_state, init_sekaikh, ROT0, "Namco", "Sekai Kaseki Hakken (Japan, SKH1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2004, taiko6, 0, ns10_taiko6, namcos10, namcos10_memn_state, init_taiko6, ROT0, "Namco", "Taiko no Tatsujin 6 (Japan, TK61 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) + +GAME( 2006, keroro, 0, ns10_keroro, namcos10, namcos10_memn_state, init_keroro, ROT0, "Namco", "Keroro Gunso Chikyu Shinryaku Shirei Dearimasu! (KRG1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // ケロロ軍曹　地球侵略指令…であります！ +GAME( 2007, gegemdb, 0, ns10_gegemdb, namcos10, namcos10_memn_state, empty_init, ROT0, "Namco", "Gegege no Kitaro Yokai Yokocho Matsuri De Batoru Ja (GYM1 Ver.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // ゲゲゲの鬼太郎　妖怪横丁まつりでバトルじゃ + +// MEM(P3) +GAME( 2001, g13jnc, 0, ns10_g13jnc, namcos10, namcos10_memp3_state, init_g13jnc, ROT0, "Eighting / Raizing / Namco", "Golgo 13: Juusei no Chinkonka (Japan, GLT1 VER.A)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) + +// Unknown +GAME( 200?, unks10md, 0, ns10_unks10md, namcos10, namcos10_memn_state, init_unks10md, ROT0, "Namco", "unknown Namco System 10 medal game (MTL1 SPR0B)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) +GAME( 2005, unks10md2, 0, ns10_unks10md2, namcos10, namcos10_memn_state, init_unks10md2, ROT0, "Namco", "unknown Namco System 10 medal game (unknown code)", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION ) // ROM VER. B0 FEB 09 2005 15:29:02 in test mode diff --git a/src/mame/palm/palmz22.cpp b/src/mame/palm/palmz22.cpp index db1f512422c..35e3e68af7f 100644 --- a/src/mame/palm/palmz22.cpp +++ b/src/mame/palm/palmz22.cpp @@ -65,8 +65,8 @@ end #include "emu.h" #include "cpu/arm7/arm7.h" +#include "machine/nandflash.h" #include "machine/s3c2410.h" -#include "machine/smartmed.h" #include "screen.h" #include @@ -101,7 +101,7 @@ protected: private: required_device m_maincpu; required_device m_s3c2410; - required_device m_nand; + required_device m_nand; uint32_t m_port[8]; @@ -265,8 +265,6 @@ INPUT_CHANGED_MEMBER(palmz22_state::input_changed) void palmz22_state::machine_start() { - m_nand->set_data_ptr( memregion("nand")->base()); - save_item(NAME(m_port)); } @@ -319,8 +317,7 @@ void palmz22_state::palmz22(machine_config &config) m_s3c2410->nand_data_r_callback().set(FUNC(palmz22_state::s3c2410_nand_data_r)); m_s3c2410->nand_data_w_callback().set(FUNC(palmz22_state::s3c2410_nand_data_w)); - NAND(config, m_nand, 0); - m_nand->set_nand_type(nand_device::chip::K9F5608U0D_J); + SAMSUNG_K9F5608U0DJ(config, m_nand, 0); m_nand->rnb_wr_callback().set(m_s3c2410, FUNC(s3c2410_device::frnb_w)); } diff --git a/src/mame/skeleton/mini2440.cpp b/src/mame/skeleton/mini2440.cpp index 0264ff63b59..1a8efc7771f 100644 --- a/src/mame/skeleton/mini2440.cpp +++ b/src/mame/skeleton/mini2440.cpp @@ -8,8 +8,8 @@ #include "emu.h" #include "cpu/arm7/arm7.h" +#include "machine/nandflash.h" #include "machine/s3c2440.h" -#include "machine/smartmed.h" #include "sound/dac.h" #include "screen.h" #include "speaker.h" @@ -43,7 +43,7 @@ public: private: required_device m_maincpu; required_device m_s3c2440; - required_device m_nand; + required_device m_nand; required_device m_ldac; required_device m_rdac; required_ioport m_penx; @@ -200,7 +200,6 @@ INPUT_CHANGED_MEMBER(mini2440_state::mini2440_input_changed) void mini2440_state::machine_start() { - m_nand->set_data_ptr(memregion("nand")->base()); } void mini2440_state::machine_reset() @@ -260,8 +259,7 @@ void mini2440_state::mini2440(machine_config &config) m_s3c2440->nand_data_r_callback().set(FUNC(mini2440_state::s3c2440_nand_data_r)); m_s3c2440->nand_data_w_callback().set(FUNC(mini2440_state::s3c2440_nand_data_w)); - NAND(config, m_nand, 0); - m_nand->set_nand_type(nand_device::chip::K9F1G08U0B); + SAMSUNG_K9F1G08U0B(config, m_nand, 0); m_nand->rnb_wr_callback().set(m_s3c2440, FUNC(s3c2440_device::frnb_w)); } -- cgit v1.2.3