From d3fbba3a5ed0fd98b8ff78a2dc8bdf042e52d6d2 Mon Sep 17 00:00:00 2001 From: hap Date: Sun, 18 Dec 2022 17:06:07 +0100 Subject: m6809: rename *.ops to *.lst --- scripts/src/cpu.lua | 6 +- src/devices/cpu/m6809/base6x09.lst | 720 ++++++++++++++++++++++++ src/devices/cpu/m6809/base6x09.ops | 720 ------------------------ src/devices/cpu/m6809/hd6309.lst | 1086 ++++++++++++++++++++++++++++++++++++ src/devices/cpu/m6809/hd6309.ops | 1086 ------------------------------------ src/devices/cpu/m6809/konami.lst | 628 +++++++++++++++++++++ src/devices/cpu/m6809/konami.ops | 628 --------------------- src/devices/cpu/m6809/m6809.lst | 605 ++++++++++++++++++++ src/devices/cpu/m6809/m6809.ops | 605 -------------------- 9 files changed, 3042 insertions(+), 3042 deletions(-) create mode 100644 src/devices/cpu/m6809/base6x09.lst delete mode 100644 src/devices/cpu/m6809/base6x09.ops create mode 100644 src/devices/cpu/m6809/hd6309.lst delete mode 100644 src/devices/cpu/m6809/hd6309.ops create mode 100644 src/devices/cpu/m6809/konami.lst delete mode 100644 src/devices/cpu/m6809/konami.ops create mode 100644 src/devices/cpu/m6809/m6809.lst delete mode 100644 src/devices/cpu/m6809/m6809.ops diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 475486173c8..50b1b5ee0f2 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -1841,9 +1841,9 @@ if CPUS["M6809"] then } custombuildtask { - { MAME_DIR .. "src/devices/cpu/m6809/m6809.ops" , GEN_DIR .. "emu/cpu/m6809/m6809.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.ops" }, {"@echo Generating m6809 source file...", PYTHON .. " $(1) $(<) > $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6809/hd6309.ops" , GEN_DIR .. "emu/cpu/m6809/hd6309.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.ops" }, {"@echo Generating hd6309 source file...", PYTHON .. " $(1) $(<) > $(@)" }}, - { MAME_DIR .. "src/devices/cpu/m6809/konami.ops" , GEN_DIR .. "emu/cpu/m6809/konami.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.ops" }, {"@echo Generating konami source file...", PYTHON .. " $(1) $(<) > $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6809/m6809.lst" , GEN_DIR .. "emu/cpu/m6809/m6809.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.lst" }, {"@echo Generating m6809 source file...", PYTHON .. " $(1) $(<) > $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6809/hd6309.lst" , GEN_DIR .. "emu/cpu/m6809/hd6309.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.lst" }, {"@echo Generating hd6309 source file...", PYTHON .. " $(1) $(<) > $(@)" }}, + { MAME_DIR .. "src/devices/cpu/m6809/konami.lst" , GEN_DIR .. "emu/cpu/m6809/konami.hxx", { MAME_DIR .. "src/devices/cpu/m6809/m6809make.py" , MAME_DIR .. "src/devices/cpu/m6809/base6x09.lst" }, {"@echo Generating konami source file...", PYTHON .. " $(1) $(<) > $(@)" }}, } end diff --git a/src/devices/cpu/m6809/base6x09.lst b/src/devices/cpu/m6809/base6x09.lst new file mode 100644 index 00000000000..d7387dc02ea --- /dev/null +++ b/src/devices/cpu/m6809/base6x09.lst @@ -0,0 +1,720 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods +NMI: + m_nmi_asserted = false; + @dummy_read_opcode_arg(0); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + m_cc |= CC_E; + set_regop16(m_s); + m_temp.w = entire_state_registers(); + %PUSH_REGISTERS; + m_cc |= CC_I | CC_F; + set_ea(VECTOR_NMI); + standard_irq_callback(INPUT_LINE_NMI); + goto INTERRUPT_VECTOR; + +FIRQ: + @dummy_read_opcode_arg(0); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + if (firq_saves_entire_state()) + { + m_cc |= CC_E; + m_temp.w = entire_state_registers(); + } + else + { + m_cc &= ~CC_E; + m_temp.w = partial_state_registers(); + } + set_regop16(m_s); + %PUSH_REGISTERS; + m_cc |= CC_I | CC_F; + set_ea(VECTOR_FIRQ); + standard_irq_callback(M6809_FIRQ_LINE); + goto INTERRUPT_VECTOR; + +IRQ: + @dummy_read_opcode_arg(0); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + m_cc |= CC_E; + set_regop16(m_s); + m_temp.w = entire_state_registers(); + %PUSH_REGISTERS; + m_cc |= CC_I; + set_ea(VECTOR_IRQ); + standard_irq_callback(M6809_IRQ_LINE); + goto INTERRUPT_VECTOR; + +INTERRUPT_VECTOR: + @dummy_vma(1); + @m_pc.b.h = read_operand(0); + @m_pc.b.l = read_operand(1); + @dummy_vma(1); + return; + +NEG8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZVC, (uint8_t)0, m_temp.b.l, -m_temp.b.l); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +COM8: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_V; + m_cc |= CC_C; + m_temp.b.l = set_flags(CC_NZ, (uint8_t) ~m_temp.b.l); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +LSR8: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_C; + m_cc |= (m_temp.b.l & 1) ? CC_C : 0; + m_temp.b.l = set_flags(CC_NZ, m_temp.b.l >> 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +ROR8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZ, rotate_right(m_temp.b.l)); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +ASR8: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_C; + m_cc |= (m_temp.b.l & 1) ? CC_C : 0; + m_temp.b.l = set_flags(CC_NZ, ((int8_t) m_temp.b.l) >> 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +ASL8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZVC, m_temp.b.l, m_temp.b.l, m_temp.b.l << 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +ROL8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, m_temp.b.l, rotate_left(m_temp.b.l)); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +DEC8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, 1, m_temp.b.l - 1); + if(!hd6309_native_mode() || !is_register_addressing_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +INC8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, 1, m_temp.b.l + 1); + if(!hd6309_native_mode() || !is_register_addressing_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +TST8: + @m_temp.b.l = read_operand(); + set_flags(CC_NZV, m_temp.b.l); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + if(!is_register_addressing_mode()) + { + @dummy_vma(1); + ; + } + return; + +JMP: + m_pc.w = m_ea.w; + return; + +CLR8: + @read_operand(); + m_cc &= ~CC_NZVC; + m_cc |= CC_Z; + if(!hd6309_native_mode() || !is_register_addressing_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0); + return; + +NEG16: + m_temp.b.h = read_operand(0); + m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZVC, (uint16_t)0, m_temp.w, -m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +LSR16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_C; + m_cc |= (m_temp.w & 1) ? CC_C : 0; + m_temp.w = set_flags(CC_NZ, m_temp.w >> 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ROR16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZ, rotate_right(m_temp.w)); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ASR16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_C; + m_cc |= (m_temp.w & 1) ? CC_C : 0; + m_temp.w = set_flags(CC_NZ, ((int16_t) m_temp.w) >> 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ASL16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZVC, m_temp.w, m_temp.w, m_temp.w << 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ROL16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZV, rotate_left(m_temp.w)); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +DEC16: + m_temp.b.h = read_operand(0); + m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZVC, m_temp.w, 1, m_temp.w - 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +INC16: + m_temp.b.h = read_operand(0); + m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZVC, m_temp.w, 1, m_temp.w + 1); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +TST16: + m_temp.b.h = read_operand(0); + m_temp.b.l = read_operand(1); + set_flags(CC_NZV, m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + if(!is_register_addressing_mode()) + { + @dummy_vma(1); + ; + } + return; + +CLR16: + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + m_cc &= ~CC_NZVC; + m_cc |= CC_Z; + write_operand(0, 0x00); + write_operand(1, 0x00); + return; + +SUB8: + m_temp.b.l = read_operand(); + regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l); + return; + +CMP8: + m_temp.b.l = read_operand(); + set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l); + return; + +SBC8: + m_temp.b.l = read_operand(); + regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l - (m_cc & CC_C ? 1 : 0)); + return; + +AND8: + m_cc &= ~CC_V; + regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() & read_operand()); + return; + +BIT8: + m_cc &= ~CC_V; + set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() & read_operand()); + return; + +EOR8: + m_cc &= ~CC_V; + regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() ^ read_operand()); + return; + +ADC8: + m_temp.b.l = read_operand(); + regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.b.l + (m_cc & CC_C ? 1 : 0)); + return; + +OR8: + m_cc &= ~CC_V; + regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() | read_operand()); + return; + +ADD8: + m_temp.b.l = read_operand(); + regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.b.l); + return; + +ADD16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +SUB16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +CMP16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +LD8: + regop8() = read_operand(); + set_flags(CC_NZV, regop8()); + return; + +LD16: + @regop16().b.h = read_operand(0); + @regop16().b.l = read_operand(1); + set_flags(CC_NZV, regop16().w); + if (®op16() == &m_s) + m_lds_encountered = true; + return; + +ST8: + write_ea(set_flags(CC_NZV, regop8())); + return; + +ST16: + @write_operand(0, regop16().b.h); + @write_operand(1, regop16().b.l); + set_flags(CC_NZV, regop16().w); + return; + +NOP: + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +SYNC: + // SYNC stops processing instructions until an interrupt request happens. + // This doesn't require the corresponding interrupt to be enabled: if it + // is disabled, execution continues with the next instruction. + @dummy_read_opcode_arg(0); + + while(!m_nmi_asserted && !m_firq_line && !m_irq_line) + { + // massaging the PC this way makes the debugger's behavior more + // intuitive + m_pc.w--; + + @eat_remaining(); + + // unmassage... + m_pc.w++; + } + @eat(1); + return; + +DAA: + daa(); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +ORCC: + m_cc |= read_operand(); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +ANDCC: + m_cc &= read_operand(); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +SEX: + m_q.r.d = set_flags(CC_NZ, (int8_t) m_q.r.b); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +BRANCH: + @m_temp.b.l = read_opcode_arg(); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + if (branch_taken()) + { + m_pc.w += (int8_t) m_temp.b.l; + } + return; + +LBRANCH: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + if (branch_taken()) + { + m_pc.w += m_temp.w; + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + } + return; + +BSR: + @m_temp.b.l = read_opcode_arg(); + m_ea.w = m_pc.w + (int8_t) m_temp.b.l; + @dummy_vma(hd6309_native_mode() ? 2 : 3); + goto GOTO_SUBROUTINE; + +LBSR: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_ea.w = m_pc.w + (int16_t) m_temp.w; + @dummy_vma(hd6309_native_mode() ? 2 : 4); + goto GOTO_SUBROUTINE; + +JSR: + @dummy_read_opcode_arg(0); + @dummy_vma(1); + goto GOTO_SUBROUTINE; + +GOTO_SUBROUTINE: + @write_memory(--m_s.w, m_pc.b.l); + @write_memory(--m_s.w, m_pc.b.h); + m_pc.w = m_ea.w; + return; + +RTS: + m_temp.w = 0x80; // RTS is equivalent to "PULS PC" + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + set_regop16(m_s); + goto PULL_REGISTERS; + +ABX: + m_x.w += m_q.r.b; + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + @dummy_vma(1); + ; + } + return; + +MUL: + mul(); + @dummy_read_opcode_arg(0); + @dummy_vma(hd6309_native_mode() ? 8 : 9); + return; + +RTI: + @dummy_read_opcode_arg(0); + set_regop16(m_s); + @m_cc = read_memory(regop16().w++); // PULS CC + m_temp.w = ((m_cc & CC_E) ? entire_state_registers() : partial_state_registers()) & ~0x01; + goto PULL_REGISTERS; + +CWAI: + @m_cc &= read_opcode_arg(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + + m_cc |= CC_E; + set_regop16(m_s); + m_temp.w = entire_state_registers(); + %PUSH_REGISTERS; + + while((m_ea.w = get_pending_interrupt()) == 0) + { + // massaging the PC this way makes the debugger's behavior more + // intuitive + m_pc.w -= 2; + + @eat_remaining(); + + // unmassage... + m_pc.w += 2; + } + + if (m_nmi_asserted) + m_nmi_asserted = false; + + set_ea(m_ea.w); // need to do this to set the addressing mode + m_cc |= CC_I | (m_ea.w != VECTOR_IRQ ? CC_F : 0); + + // invoke standard interrupt callback for MAME core + switch (m_ea.w) + { + case VECTOR_NMI: standard_irq_callback(INPUT_LINE_NMI); break; + case VECTOR_FIRQ: standard_irq_callback(M6809_FIRQ_LINE); break; + case VECTOR_IRQ: standard_irq_callback(M6809_IRQ_LINE); break; + default: break; + } + + goto INTERRUPT_VECTOR; + +LEA_xy: + regop16().w = set_flags(CC_Z, m_ea.w); + @dummy_vma(1); + return; + +LEA_us: + if (®op16() == &m_s) + m_lds_encountered = true; + regop16().w = m_ea.w; + @dummy_vma(1); + return; + +PSHS: + @m_temp.w = read_opcode_arg(); + @dummy_vma(2); + set_regop16(m_s); + if(!hd6309_native_mode()) + { + @(void)read_memory(regop16().w); + ; + } + goto PUSH_REGISTERS; + +PULS: + @m_temp.w = read_opcode_arg(); + @dummy_vma(hd6309_native_mode() ? 1 : 2); + set_regop16(m_s); + goto PULL_REGISTERS; + +PSHU: + @m_temp.w = read_opcode_arg(); + @dummy_vma(2); + set_regop16(m_u); + if(!hd6309_native_mode()) + { + @(void)read_memory(regop16().w); + ; + } + goto PUSH_REGISTERS; + +PULU: + @m_temp.w = read_opcode_arg(); + @dummy_vma(hd6309_native_mode() ? 1 : 2); + set_regop16(m_u); + goto PULL_REGISTERS; + +SWI: + // doesn't use SOFTWARE_INTERRUPT label because SWI will + // inhibit IRQ/FIRQ + set_ea(VECTOR_SWI); + standard_irq_callback(M6809_SWI); + m_cc |= CC_E; + set_regop16(m_s); + m_temp.w = entire_state_registers(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + %PUSH_REGISTERS; + m_cc |= CC_I | CC_F; + goto INTERRUPT_VECTOR; + +SWI2: + set_ea(VECTOR_SWI2); + standard_irq_callback(M6809_SWI); + goto SOFTWARE_INTERRUPT; + +SWI3: + set_ea(VECTOR_SWI3); + standard_irq_callback(M6809_SWI); + goto SOFTWARE_INTERRUPT; + +SOFTWARE_INTERRUPT: + // used for SWI2/SWI3 and illegal/div0 on 6309 + m_cc |= CC_E; + set_regop16(m_s); + m_temp.w = entire_state_registers(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + %PUSH_REGISTERS; + goto INTERRUPT_VECTOR; + +DIRECT: + @set_ea(((uint16_t)m_dp << 8) | read_opcode_arg()); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + return; + +EXTENDED: + @set_ea_h(read_opcode_arg()); + @set_ea_l(read_opcode_arg()); + if(!hd6309_native_mode()) + { + @dummy_vma(1); + ; + } + return; diff --git a/src/devices/cpu/m6809/base6x09.ops b/src/devices/cpu/m6809/base6x09.ops deleted file mode 100644 index d7387dc02ea..00000000000 --- a/src/devices/cpu/m6809/base6x09.ops +++ /dev/null @@ -1,720 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Nathan Woods -NMI: - m_nmi_asserted = false; - @dummy_read_opcode_arg(0); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - m_cc |= CC_E; - set_regop16(m_s); - m_temp.w = entire_state_registers(); - %PUSH_REGISTERS; - m_cc |= CC_I | CC_F; - set_ea(VECTOR_NMI); - standard_irq_callback(INPUT_LINE_NMI); - goto INTERRUPT_VECTOR; - -FIRQ: - @dummy_read_opcode_arg(0); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - if (firq_saves_entire_state()) - { - m_cc |= CC_E; - m_temp.w = entire_state_registers(); - } - else - { - m_cc &= ~CC_E; - m_temp.w = partial_state_registers(); - } - set_regop16(m_s); - %PUSH_REGISTERS; - m_cc |= CC_I | CC_F; - set_ea(VECTOR_FIRQ); - standard_irq_callback(M6809_FIRQ_LINE); - goto INTERRUPT_VECTOR; - -IRQ: - @dummy_read_opcode_arg(0); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - m_cc |= CC_E; - set_regop16(m_s); - m_temp.w = entire_state_registers(); - %PUSH_REGISTERS; - m_cc |= CC_I; - set_ea(VECTOR_IRQ); - standard_irq_callback(M6809_IRQ_LINE); - goto INTERRUPT_VECTOR; - -INTERRUPT_VECTOR: - @dummy_vma(1); - @m_pc.b.h = read_operand(0); - @m_pc.b.l = read_operand(1); - @dummy_vma(1); - return; - -NEG8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZVC, (uint8_t)0, m_temp.b.l, -m_temp.b.l); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -COM8: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_V; - m_cc |= CC_C; - m_temp.b.l = set_flags(CC_NZ, (uint8_t) ~m_temp.b.l); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -LSR8: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_C; - m_cc |= (m_temp.b.l & 1) ? CC_C : 0; - m_temp.b.l = set_flags(CC_NZ, m_temp.b.l >> 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -ROR8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZ, rotate_right(m_temp.b.l)); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -ASR8: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_C; - m_cc |= (m_temp.b.l & 1) ? CC_C : 0; - m_temp.b.l = set_flags(CC_NZ, ((int8_t) m_temp.b.l) >> 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -ASL8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZVC, m_temp.b.l, m_temp.b.l, m_temp.b.l << 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -ROL8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, m_temp.b.l, rotate_left(m_temp.b.l)); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -DEC8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, 1, m_temp.b.l - 1); - if(!hd6309_native_mode() || !is_register_addressing_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -INC8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZV, m_temp.b.l, 1, m_temp.b.l + 1); - if(!hd6309_native_mode() || !is_register_addressing_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(m_temp.b.l); - return; - -TST8: - @m_temp.b.l = read_operand(); - set_flags(CC_NZV, m_temp.b.l); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - if(!is_register_addressing_mode()) - { - @dummy_vma(1); - ; - } - return; - -JMP: - m_pc.w = m_ea.w; - return; - -CLR8: - @read_operand(); - m_cc &= ~CC_NZVC; - m_cc |= CC_Z; - if(!hd6309_native_mode() || !is_register_addressing_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0); - return; - -NEG16: - m_temp.b.h = read_operand(0); - m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZVC, (uint16_t)0, m_temp.w, -m_temp.w); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -LSR16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_C; - m_cc |= (m_temp.w & 1) ? CC_C : 0; - m_temp.w = set_flags(CC_NZ, m_temp.w >> 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ROR16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZ, rotate_right(m_temp.w)); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ASR16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_C; - m_cc |= (m_temp.w & 1) ? CC_C : 0; - m_temp.w = set_flags(CC_NZ, ((int16_t) m_temp.w) >> 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ASL16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZVC, m_temp.w, m_temp.w, m_temp.w << 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ROL16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZV, rotate_left(m_temp.w)); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -DEC16: - m_temp.b.h = read_operand(0); - m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZVC, m_temp.w, 1, m_temp.w - 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -INC16: - m_temp.b.h = read_operand(0); - m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZVC, m_temp.w, 1, m_temp.w + 1); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -TST16: - m_temp.b.h = read_operand(0); - m_temp.b.l = read_operand(1); - set_flags(CC_NZV, m_temp.w); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - if(!is_register_addressing_mode()) - { - @dummy_vma(1); - ; - } - return; - -CLR16: - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - m_cc &= ~CC_NZVC; - m_cc |= CC_Z; - write_operand(0, 0x00); - write_operand(1, 0x00); - return; - -SUB8: - m_temp.b.l = read_operand(); - regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l); - return; - -CMP8: - m_temp.b.l = read_operand(); - set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l); - return; - -SBC8: - m_temp.b.l = read_operand(); - regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l - (m_cc & CC_C ? 1 : 0)); - return; - -AND8: - m_cc &= ~CC_V; - regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() & read_operand()); - return; - -BIT8: - m_cc &= ~CC_V; - set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() & read_operand()); - return; - -EOR8: - m_cc &= ~CC_V; - regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() ^ read_operand()); - return; - -ADC8: - m_temp.b.l = read_operand(); - regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.b.l + (m_cc & CC_C ? 1 : 0)); - return; - -OR8: - m_cc &= ~CC_V; - regop8() = set_flags(CC_NZ, (uint8_t)0, regop8(), regop8() | read_operand()); - return; - -ADD8: - m_temp.b.l = read_operand(); - regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.b.l); - return; - -ADD16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -SUB16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -CMP16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -LD8: - regop8() = read_operand(); - set_flags(CC_NZV, regop8()); - return; - -LD16: - @regop16().b.h = read_operand(0); - @regop16().b.l = read_operand(1); - set_flags(CC_NZV, regop16().w); - if (®op16() == &m_s) - m_lds_encountered = true; - return; - -ST8: - write_ea(set_flags(CC_NZV, regop8())); - return; - -ST16: - @write_operand(0, regop16().b.h); - @write_operand(1, regop16().b.l); - set_flags(CC_NZV, regop16().w); - return; - -NOP: - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -SYNC: - // SYNC stops processing instructions until an interrupt request happens. - // This doesn't require the corresponding interrupt to be enabled: if it - // is disabled, execution continues with the next instruction. - @dummy_read_opcode_arg(0); - - while(!m_nmi_asserted && !m_firq_line && !m_irq_line) - { - // massaging the PC this way makes the debugger's behavior more - // intuitive - m_pc.w--; - - @eat_remaining(); - - // unmassage... - m_pc.w++; - } - @eat(1); - return; - -DAA: - daa(); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -ORCC: - m_cc |= read_operand(); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -ANDCC: - m_cc &= read_operand(); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -SEX: - m_q.r.d = set_flags(CC_NZ, (int8_t) m_q.r.b); - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - return; - -BRANCH: - @m_temp.b.l = read_opcode_arg(); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - if (branch_taken()) - { - m_pc.w += (int8_t) m_temp.b.l; - } - return; - -LBRANCH: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - if (branch_taken()) - { - m_pc.w += m_temp.w; - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - } - return; - -BSR: - @m_temp.b.l = read_opcode_arg(); - m_ea.w = m_pc.w + (int8_t) m_temp.b.l; - @dummy_vma(hd6309_native_mode() ? 2 : 3); - goto GOTO_SUBROUTINE; - -LBSR: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_ea.w = m_pc.w + (int16_t) m_temp.w; - @dummy_vma(hd6309_native_mode() ? 2 : 4); - goto GOTO_SUBROUTINE; - -JSR: - @dummy_read_opcode_arg(0); - @dummy_vma(1); - goto GOTO_SUBROUTINE; - -GOTO_SUBROUTINE: - @write_memory(--m_s.w, m_pc.b.l); - @write_memory(--m_s.w, m_pc.b.h); - m_pc.w = m_ea.w; - return; - -RTS: - m_temp.w = 0x80; // RTS is equivalent to "PULS PC" - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - ; - } - set_regop16(m_s); - goto PULL_REGISTERS; - -ABX: - m_x.w += m_q.r.b; - if(!hd6309_native_mode()) - { - @dummy_read_opcode_arg(0); - @dummy_vma(1); - ; - } - return; - -MUL: - mul(); - @dummy_read_opcode_arg(0); - @dummy_vma(hd6309_native_mode() ? 8 : 9); - return; - -RTI: - @dummy_read_opcode_arg(0); - set_regop16(m_s); - @m_cc = read_memory(regop16().w++); // PULS CC - m_temp.w = ((m_cc & CC_E) ? entire_state_registers() : partial_state_registers()) & ~0x01; - goto PULL_REGISTERS; - -CWAI: - @m_cc &= read_opcode_arg(); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - - m_cc |= CC_E; - set_regop16(m_s); - m_temp.w = entire_state_registers(); - %PUSH_REGISTERS; - - while((m_ea.w = get_pending_interrupt()) == 0) - { - // massaging the PC this way makes the debugger's behavior more - // intuitive - m_pc.w -= 2; - - @eat_remaining(); - - // unmassage... - m_pc.w += 2; - } - - if (m_nmi_asserted) - m_nmi_asserted = false; - - set_ea(m_ea.w); // need to do this to set the addressing mode - m_cc |= CC_I | (m_ea.w != VECTOR_IRQ ? CC_F : 0); - - // invoke standard interrupt callback for MAME core - switch (m_ea.w) - { - case VECTOR_NMI: standard_irq_callback(INPUT_LINE_NMI); break; - case VECTOR_FIRQ: standard_irq_callback(M6809_FIRQ_LINE); break; - case VECTOR_IRQ: standard_irq_callback(M6809_IRQ_LINE); break; - default: break; - } - - goto INTERRUPT_VECTOR; - -LEA_xy: - regop16().w = set_flags(CC_Z, m_ea.w); - @dummy_vma(1); - return; - -LEA_us: - if (®op16() == &m_s) - m_lds_encountered = true; - regop16().w = m_ea.w; - @dummy_vma(1); - return; - -PSHS: - @m_temp.w = read_opcode_arg(); - @dummy_vma(2); - set_regop16(m_s); - if(!hd6309_native_mode()) - { - @(void)read_memory(regop16().w); - ; - } - goto PUSH_REGISTERS; - -PULS: - @m_temp.w = read_opcode_arg(); - @dummy_vma(hd6309_native_mode() ? 1 : 2); - set_regop16(m_s); - goto PULL_REGISTERS; - -PSHU: - @m_temp.w = read_opcode_arg(); - @dummy_vma(2); - set_regop16(m_u); - if(!hd6309_native_mode()) - { - @(void)read_memory(regop16().w); - ; - } - goto PUSH_REGISTERS; - -PULU: - @m_temp.w = read_opcode_arg(); - @dummy_vma(hd6309_native_mode() ? 1 : 2); - set_regop16(m_u); - goto PULL_REGISTERS; - -SWI: - // doesn't use SOFTWARE_INTERRUPT label because SWI will - // inhibit IRQ/FIRQ - set_ea(VECTOR_SWI); - standard_irq_callback(M6809_SWI); - m_cc |= CC_E; - set_regop16(m_s); - m_temp.w = entire_state_registers(); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - %PUSH_REGISTERS; - m_cc |= CC_I | CC_F; - goto INTERRUPT_VECTOR; - -SWI2: - set_ea(VECTOR_SWI2); - standard_irq_callback(M6809_SWI); - goto SOFTWARE_INTERRUPT; - -SWI3: - set_ea(VECTOR_SWI3); - standard_irq_callback(M6809_SWI); - goto SOFTWARE_INTERRUPT; - -SOFTWARE_INTERRUPT: - // used for SWI2/SWI3 and illegal/div0 on 6309 - m_cc |= CC_E; - set_regop16(m_s); - m_temp.w = entire_state_registers(); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - %PUSH_REGISTERS; - goto INTERRUPT_VECTOR; - -DIRECT: - @set_ea(((uint16_t)m_dp << 8) | read_opcode_arg()); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - return; - -EXTENDED: - @set_ea_h(read_opcode_arg()); - @set_ea_l(read_opcode_arg()); - if(!hd6309_native_mode()) - { - @dummy_vma(1); - ; - } - return; diff --git a/src/devices/cpu/m6809/hd6309.lst b/src/devices/cpu/m6809/hd6309.lst new file mode 100644 index 00000000000..becb5c09d4b --- /dev/null +++ b/src/devices/cpu/m6809/hd6309.lst @@ -0,0 +1,1086 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods +MAIN: + // check interrupt lines + switch(get_pending_interrupt()) + { + case VECTOR_NMI: goto NMI; + case VECTOR_FIRQ: goto FIRQ; + case VECTOR_IRQ: goto IRQ; + } + + // debugger hook + m_ppc = m_pc; + debugger_instruction_hook(m_pc.w); + + // opcode fetch + @m_opcode = read_opcode(); + + // dispatch opcode + switch(m_opcode) + { + case 0x00: %DIRECT; %NEG8; return; + case 0x01: %IMM_IM; %DIRECT; %OIM; return; + case 0x02: %IMM_IM; %DIRECT; %AIM; return; + case 0x03: %DIRECT; %COM8; return; + case 0x04: %DIRECT; %LSR8; return; + case 0x05: %IMM_IM; %DIRECT; %EIM; return; + case 0x06: %DIRECT; %ROR8; return; + case 0x07: %DIRECT; %ASR8; return; + case 0x08: %DIRECT; %ASL8; return; + case 0x09: %DIRECT; %ROL8; return; + case 0x0A: %DIRECT; %DEC8; return; + case 0x0B: %IMM_IM; %DIRECT; %TIM; return; + case 0x0C: %DIRECT; %INC8; return; + case 0x0D: %DIRECT; %TST8; return; + case 0x0E: %DIRECT; %JMP; return; + case 0x0F: %DIRECT; %CLR8; return; + + case 0x10: %DISPATCH10; return; + case 0x11: %DISPATCH11; return; + case 0x12: %NOP; return; + case 0x13: %SYNC; return; + case 0x14: %SEXW; return; + case 0x16: set_cond(true); %LBRANCH; return; + case 0x17: %LBSR; return; + case 0x19: %DAA; return; + case 0x1A: set_imm(); %ORCC; return; + case 0x1C: set_imm(); %ANDCC; return; + case 0x1D: %SEX; return; + case 0x1E: %EXG; return; + case 0x1F: %TFR; return; + + case 0x20: set_cond(true); %BRANCH; return; + case 0x21: set_cond(false); %BRANCH; return; + case 0x22: set_cond(cond_hi()); %BRANCH; return; + case 0x23: set_cond(!cond_hi()); %BRANCH; return; + case 0x24: set_cond(cond_cc()); %BRANCH; return; + case 0x25: set_cond(!cond_cc()); %BRANCH; return; + case 0x26: set_cond(cond_ne()); %BRANCH; return; + case 0x27: set_cond(!cond_ne()); %BRANCH; return; + case 0x28: set_cond(cond_vc()); %BRANCH; return; + case 0x29: set_cond(!cond_vc()); %BRANCH; return; + case 0x2A: set_cond(cond_pl()); %BRANCH; return; + case 0x2B: set_cond(!cond_pl()); %BRANCH; return; + case 0x2C: set_cond(cond_ge()); %BRANCH; return; + case 0x2D: set_cond(!cond_ge()); %BRANCH; return; + case 0x2E: set_cond(cond_gt()); %BRANCH; return; + case 0x2F: set_cond(!cond_gt()); %BRANCH; return; + + case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return; + case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return; + case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return; + case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return; + case 0x34: %PSHS; return; + case 0x35: %PULS; return; + case 0x36: %PSHU; return; + case 0x37: %PULU; return; + case 0x39: %RTS; return; + case 0x3A: %ABX; return; + case 0x3B: %RTI; return; + case 0x3C: %CWAI; return; + case 0x3D: %MUL; return; + case 0x3F: %SWI; return; + + case 0x40: set_a(); %NEG8; return; + case 0x43: set_a(); %COM8; return; + case 0x44: set_a(); %LSR8; return; + case 0x46: set_a(); %ROR8; return; + case 0x47: set_a(); %ASR8; return; + case 0x48: set_a(); %ASL8; return; + case 0x49: set_a(); %ROL8; return; + case 0x4A: set_a(); %DEC8; return; + case 0x4C: set_a(); %INC8; return; + case 0x4D: set_a(); %TST8; return; + case 0x4F: set_a(); %CLR8; return; + + case 0x50: set_b(); %NEG8; return; + case 0x53: set_b(); %COM8; return; + case 0x54: set_b(); %LSR8; return; + case 0x56: set_b(); %ROR8; return; + case 0x57: set_b(); %ASR8; return; + case 0x58: set_b(); %ASL8; return; + case 0x59: set_b(); %ROL8; return; + case 0x5A: set_b(); %DEC8; return; + case 0x5C: set_b(); %INC8; return; + case 0x5D: set_b(); %TST8; return; + case 0x5F: set_b(); %CLR8; return; + + case 0x60: %INDEXED; %NEG8; return; + case 0x61: %IMM_IM; %INDEXED; %OIM; return; + case 0x62: %IMM_IM; %INDEXED; %AIM; return; + case 0x63: %INDEXED; %COM8; return; + case 0x64: %INDEXED; %LSR8; return; + case 0x65: %IMM_IM; %INDEXED; %EIM; return; + case 0x66: %INDEXED; %ROR8; return; + case 0x67: %INDEXED; %ASR8; return; + case 0x68: %INDEXED; %ASL8; return; + case 0x69: %INDEXED; %ROL8; return; + case 0x6A: %INDEXED; %DEC8; return; + case 0x6B: %IMM_IM; %INDEXED; %TIM; return; + case 0x6C: %INDEXED; %INC8; return; + case 0x6D: %INDEXED; %TST8; return; + case 0x6E: %INDEXED; %JMP; return; + case 0x6F: %INDEXED; %CLR8; return; + + case 0x70: %EXTENDED; %NEG8; return; + case 0x71: %IMM_IM; %EXTENDED; %OIM; return; + case 0x72: %IMM_IM; %EXTENDED; %AIM; return; + case 0x73: %EXTENDED; %COM8; return; + case 0x74: %EXTENDED; %LSR8; return; + case 0x75: %IMM_IM; %EXTENDED; %EIM; return; + case 0x76: %EXTENDED; %ROR8; return; + case 0x77: %EXTENDED; %ASR8; return; + case 0x78: %EXTENDED; %ASL8; return; + case 0x79: %EXTENDED; %ROL8; return; + case 0x7A: %EXTENDED; %DEC8; return; + case 0x7B: %IMM_IM; %EXTENDED; %TIM; return; + case 0x7C: %EXTENDED; %INC8; return; + case 0x7D: %EXTENDED; %TST8; return; + case 0x7E: %EXTENDED; %JMP; return; + case 0x7F: %EXTENDED; %CLR8; return; + + case 0x80: set_regop8(m_q.r.a); set_imm(); %SUB8; return; + case 0x81: set_regop8(m_q.r.a); set_imm(); %CMP8; return; + case 0x82: set_regop8(m_q.r.a); set_imm(); %SBC8; return; + case 0x83: set_regop16(m_q.p.d); set_imm(); %SUB16; return; + case 0x84: set_regop8(m_q.r.a); set_imm(); %AND8; return; + case 0x85: set_regop8(m_q.r.a); set_imm(); %BIT8; return; + case 0x86: set_regop8(m_q.r.a); set_imm(); %LD8; return; + case 0x88: set_regop8(m_q.r.a); set_imm(); %EOR8; return; + case 0x89: set_regop8(m_q.r.a); set_imm(); %ADC8; return; + case 0x8A: set_regop8(m_q.r.a); set_imm(); %OR8; return; + case 0x8B: set_regop8(m_q.r.a); set_imm(); %ADD8; return; + case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return; + case 0x8D: %BSR; return; + case 0x8E: set_regop16(m_x); set_imm(); %LD16; return; + + case 0x90: set_regop8(m_q.r.a); %DIRECT; %SUB8; return; + case 0x91: set_regop8(m_q.r.a); %DIRECT; %CMP8; return; + case 0x92: set_regop8(m_q.r.a); %DIRECT; %SBC8; return; + case 0x93: set_regop16(m_q.p.d); %DIRECT; %SUB16; return; + case 0x94: set_regop8(m_q.r.a); %DIRECT; %AND8; return; + case 0x95: set_regop8(m_q.r.a); %DIRECT; %BIT8; return; + case 0x96: set_regop8(m_q.r.a); %DIRECT; %LD8; return; + case 0x97: set_regop8(m_q.r.a); %DIRECT; %ST8; return; + case 0x98: set_regop8(m_q.r.a); %DIRECT; %EOR8; return; + case 0x99: set_regop8(m_q.r.a); %DIRECT; %ADC8; return; + case 0x9A: set_regop8(m_q.r.a); %DIRECT; %OR8; return; + case 0x9B: set_regop8(m_q.r.a); %DIRECT; %ADD8; return; + case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return; + case 0x9D: %DIRECT; %JSR; return; + case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return; + case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return; + + case 0xA0: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; + case 0xA1: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; + case 0xA2: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; + case 0xA3: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; + case 0xA4: set_regop8(m_q.r.a); %INDEXED; %AND8; return; + case 0xA5: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; + case 0xA6: set_regop8(m_q.r.a); %INDEXED; %LD8; return; + case 0xA7: set_regop8(m_q.r.a); %INDEXED; %ST8; return; + case 0xA8: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; + case 0xA9: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; + case 0xAA: set_regop8(m_q.r.a); %INDEXED; %OR8; return; + case 0xAB: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; + case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return; + case 0xAD: %INDEXED; %JSR_ind; return; + case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return; + case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return; + + case 0xB0: set_regop8(m_q.r.a); %EXTENDED; %SUB8; return; + case 0xB1: set_regop8(m_q.r.a); %EXTENDED; %CMP8; return; + case 0xB2: set_regop8(m_q.r.a); %EXTENDED; %SBC8; return; + case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %SUB16; return; + case 0xB4: set_regop8(m_q.r.a); %EXTENDED; %AND8; return; + case 0xB5: set_regop8(m_q.r.a); %EXTENDED; %BIT8; return; + case 0xB6: set_regop8(m_q.r.a); %EXTENDED; %LD8; return; + case 0xB7: set_regop8(m_q.r.a); %EXTENDED; %ST8; return; + case 0xB8: set_regop8(m_q.r.a); %EXTENDED; %EOR8; return; + case 0xB9: set_regop8(m_q.r.a); %EXTENDED; %ADC8; return; + case 0xBA: set_regop8(m_q.r.a); %EXTENDED; %OR8; return; + case 0xBB: set_regop8(m_q.r.a); %EXTENDED; %ADD8; return; + case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return; + case 0xBD: %EXTENDED; %JSR; return; + case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return; + case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return; + + case 0xC0: set_regop8(m_q.r.b); set_imm(); %SUB8; return; + case 0xC1: set_regop8(m_q.r.b); set_imm(); %CMP8; return; + case 0xC2: set_regop8(m_q.r.b); set_imm(); %SBC8; return; + case 0xC3: set_regop16(m_q.p.d); set_imm(); %ADD16; return; + case 0xC4: set_regop8(m_q.r.b); set_imm(); %AND8; return; + case 0xC5: set_regop8(m_q.r.b); set_imm(); %BIT8; return; + case 0xC6: set_regop8(m_q.r.b); set_imm(); %LD8; return; + case 0xC8: set_regop8(m_q.r.b); set_imm(); %EOR8; return; + case 0xC9: set_regop8(m_q.r.b); set_imm(); %ADC8; return; + case 0xCA: set_regop8(m_q.r.b); set_imm(); %OR8; return; + case 0xCB: set_regop8(m_q.r.b); set_imm(); %ADD8; return; + case 0xCC: set_regop16(m_q.p.d); set_imm(); %LD16; return; + case 0xCD: set_imm(); %LDQ; return; + case 0xCE: set_regop16(m_u); set_imm(); %LD16; return; + + case 0xD0: set_regop8(m_q.r.b); %DIRECT; %SUB8; return; + case 0xD1: set_regop8(m_q.r.b); %DIRECT; %CMP8; return; + case 0xD2: set_regop8(m_q.r.b); %DIRECT; %SBC8; return; + case 0xD3: set_regop16(m_q.p.d); %DIRECT; %ADD16; return; + case 0xD4: set_regop8(m_q.r.b); %DIRECT; %AND8; return; + case 0xD5: set_regop8(m_q.r.b); %DIRECT; %BIT8; return; + case 0xD6: set_regop8(m_q.r.b); %DIRECT; %LD8; return; + case 0xD7: set_regop8(m_q.r.b); %DIRECT; %ST8; return; + case 0xD8: set_regop8(m_q.r.b); %DIRECT; %EOR8; return; + case 0xD9: set_regop8(m_q.r.b); %DIRECT; %ADC8; return; + case 0xDA: set_regop8(m_q.r.b); %DIRECT; %OR8; return; + case 0xDB: set_regop8(m_q.r.b); %DIRECT; %ADD8; return; + case 0xDC: set_regop16(m_q.p.d); %DIRECT; %LD16; return; + case 0xDD: set_regop16(m_q.p.d); %DIRECT; %ST16; return; + case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return; + case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return; + + case 0xE0: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; + case 0xE1: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; + case 0xE2: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; + case 0xE3: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; + case 0xE4: set_regop8(m_q.r.b); %INDEXED; %AND8; return; + case 0xE5: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; + case 0xE6: set_regop8(m_q.r.b); %INDEXED; %LD8; return; + case 0xE7: set_regop8(m_q.r.b); %INDEXED; %ST8; return; + case 0xE8: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; + case 0xE9: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; + case 0xEA: set_regop8(m_q.r.b); %INDEXED; %OR8; return; + case 0xEB: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; + case 0xEC: set_regop16(m_q.p.d); %INDEXED; %LD16; return; + case 0xED: set_regop16(m_q.p.d); %INDEXED; %ST16; return; + case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return; + case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return; + + case 0xF0: set_regop8(m_q.r.b); %EXTENDED; %SUB8; return; + case 0xF1: set_regop8(m_q.r.b); %EXTENDED; %CMP8; return; + case 0xF2: set_regop8(m_q.r.b); %EXTENDED; %SBC8; return; + case 0xF3: set_regop16(m_q.p.d); %EXTENDED; %ADD16; return; + case 0xF4: set_regop8(m_q.r.b); %EXTENDED; %AND8; return; + case 0xF5: set_regop8(m_q.r.b); %EXTENDED; %BIT8; return; + case 0xF6: set_regop8(m_q.r.b); %EXTENDED; %LD8; return; + case 0xF7: set_regop8(m_q.r.b); %EXTENDED; %ST8; return; + case 0xF8: set_regop8(m_q.r.b); %EXTENDED; %EOR8; return; + case 0xF9: set_regop8(m_q.r.b); %EXTENDED; %ADC8; return; + case 0xFA: set_regop8(m_q.r.b); %EXTENDED; %OR8; return; + case 0xFB: set_regop8(m_q.r.b); %EXTENDED; %ADD8; return; + case 0xFC: set_regop16(m_q.p.d); %EXTENDED; %LD16; return; + case 0xFD: set_regop16(m_q.p.d); %EXTENDED; %ST16; return; + case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return; + case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return; + default: %ILLEGAL; return; + } + return; + +DISPATCH10: + @m_opcode = read_opcode(); + switch(m_opcode) + { + case 0x21: set_cond(false); %LBRANCH; return; + case 0x22: set_cond(cond_hi()); %LBRANCH; return; + case 0x23: set_cond(!cond_hi()); %LBRANCH; return; + case 0x24: set_cond(cond_cc()); %LBRANCH; return; + case 0x25: set_cond(!cond_cc()); %LBRANCH; return; + case 0x26: set_cond(cond_ne()); %LBRANCH; return; + case 0x27: set_cond(!cond_ne()); %LBRANCH; return; + case 0x28: set_cond(cond_vc()); %LBRANCH; return; + case 0x29: set_cond(!cond_vc()); %LBRANCH; return; + case 0x2A: set_cond(cond_pl()); %LBRANCH; return; + case 0x2B: set_cond(!cond_pl()); %LBRANCH; return; + case 0x2C: set_cond(cond_ge()); %LBRANCH; return; + case 0x2D: set_cond(!cond_ge()); %LBRANCH; return; + case 0x2E: set_cond(cond_gt()); %LBRANCH; return; + case 0x2F: set_cond(!cond_gt()); %LBRANCH; return; + + case 0x30: register_register_op(); %ADD*; return; + case 0x31: register_register_op(); %ADC*; return; + case 0x32: register_register_op(); %SUB*; return; + case 0x33: register_register_op(); %SBC*; return; + case 0x34: register_register_op(); %AND*; return; + case 0x35: register_register_op(); %OR*; return; + case 0x36: register_register_op(); %EOR*; return; + case 0x37: register_register_op(); %CMP*; return; + case 0x38: %PSHSW; return; + case 0x39: %PULSW; return; + case 0x3A: %PSHUW; return; + case 0x3B: %PULUW; return; + case 0x3F: %SWI2; return; + + case 0x40: set_d(); %NEG16; return; + case 0x43: set_d(); %COM16; return; + case 0x44: set_d(); %LSR16; return; + case 0x46: set_d(); %ROR16; return; + case 0x47: set_d(); %ASR16; return; + case 0x48: set_d(); %ASL16; return; + case 0x49: set_d(); %ROL16; return; + case 0x4A: set_d(); %DEC16; return; + case 0x4C: set_d(); %INC16; return; + case 0x4D: set_d(); %TST16; return; + case 0x4F: set_d(); %CLR16; return; + + case 0x50: set_w(); %NEG16; return; + case 0x53: set_w(); %COM16; return; + case 0x54: set_w(); %LSR16; return; + case 0x56: set_w(); %ROR16; return; + case 0x57: set_w(); %ASR16; return; + case 0x58: set_w(); %ASL16; return; + case 0x59: set_w(); %ROL16; return; + case 0x5A: set_w(); %DEC16; return; + case 0x5C: set_w(); %INC16; return; + case 0x5D: set_w(); %TST16; return; + case 0x5F: set_w(); %CLR16; return; + + case 0x80: set_regop16(m_q.p.w); set_imm(); %SUB16; return; + case 0x81: set_regop16(m_q.p.w); set_imm(); %CMP16; return; + case 0x82: set_regop16(m_q.p.d); set_imm(); %SBC16; return; + case 0x83: set_regop16(m_q.p.d); set_imm(); %CMP16; return; + case 0x84: set_regop16(m_q.p.d); set_imm(); %AND16; return; + case 0x85: set_regop16(m_q.p.d); set_imm(); %BIT16; return; + case 0x86: set_regop16(m_q.p.w); set_imm(); %LD16; return; + case 0x88: set_regop16(m_q.p.d); set_imm(); %EOR16; return; + case 0x89: set_regop16(m_q.p.d); set_imm(); %ADC16; return; + case 0x8A: set_regop16(m_q.p.d); set_imm(); %OR16; return; + case 0x8B: set_regop16(m_q.p.w); set_imm(); %ADD16; return; + case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return; + case 0x8E: set_regop16(m_y); set_imm(); %LD16; return; + + case 0x90: set_regop16(m_q.p.w); %DIRECT; %SUB16; return; + case 0x91: set_regop16(m_q.p.w); %DIRECT; %CMP16; return; + case 0x92: set_regop16(m_q.p.d); %DIRECT; %SBC16; return; + case 0x93: set_regop16(m_q.p.d); %DIRECT; %CMP16; return; + case 0x94: set_regop16(m_q.p.d); %DIRECT; %AND16; return; + case 0x95: set_regop16(m_q.p.d); %DIRECT; %BIT16; return; + case 0x96: set_regop16(m_q.p.w); %DIRECT; %LD16; return; + case 0x97: set_regop16(m_q.p.w); %DIRECT; %ST16; return; + case 0x98: set_regop16(m_q.p.d); %DIRECT; %EOR16; return; + case 0x99: set_regop16(m_q.p.d); %DIRECT; %ADC16; return; + case 0x9A: set_regop16(m_q.p.d); %DIRECT; %OR16; return; + case 0x9B: set_regop16(m_q.p.w); %DIRECT; %ADD16; return; + case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return; + case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return; + case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return; + + case 0xA0: set_regop16(m_q.p.w); %INDEXED; %SUB16; return; + case 0xA1: set_regop16(m_q.p.w); %INDEXED; %CMP16; return; + case 0xA2: set_regop16(m_q.p.d); %INDEXED; %SBC16; return; + case 0xA3: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; + case 0xA4: set_regop16(m_q.p.d); %INDEXED; %AND16; return; + case 0xA5: set_regop16(m_q.p.d); %INDEXED; %BIT16; return; + case 0xA6: set_regop16(m_q.p.w); %INDEXED; %LD16; return; + case 0xA7: set_regop16(m_q.p.w); %INDEXED; %ST16; return; + case 0xA8: set_regop16(m_q.p.d); %INDEXED; %EOR16; return; + case 0xA9: set_regop16(m_q.p.d); %INDEXED; %ADC16; return; + case 0xAA: set_regop16(m_q.p.d); %INDEXED; %OR16; return; + case 0xAB: set_regop16(m_q.p.w); %INDEXED; %ADD16; return; + case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return; + case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return; + case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return; + + case 0xB0: set_regop16(m_q.p.w); %EXTENDED; %SUB16; return; + case 0xB1: set_regop16(m_q.p.w); %EXTENDED; %CMP16; return; + case 0xB2: set_regop16(m_q.p.d); %EXTENDED; %SBC16; return; + case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %CMP16; return; + case 0xB4: set_regop16(m_q.p.d); %EXTENDED; %AND16; return; + case 0xB5: set_regop16(m_q.p.d); %EXTENDED; %BIT16; return; + case 0xB6: set_regop16(m_q.p.w); %EXTENDED; %LD16; return; + case 0xB7: set_regop16(m_q.p.w); %EXTENDED; %ST16; return; + case 0xB8: set_regop16(m_q.p.d); %EXTENDED; %EOR16; return; + case 0xB9: set_regop16(m_q.p.d); %EXTENDED; %ADC16; return; + case 0xBA: set_regop16(m_q.p.d); %EXTENDED; %OR16; return; + case 0xBB: set_regop16(m_q.p.w); %EXTENDED; %ADD16; return; + case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return; + case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return; + case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return; + + case 0xCE: set_regop16(m_s); set_imm(); %LD16; return; + case 0xDC: %DIRECT; %LDQ; return; + case 0xDD: %DIRECT; %STQ; return; + case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return; + case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return; + case 0xEC: %INDEXED; %LDQ; return; + case 0xED: %INDEXED; %STQ; return; + case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return; + case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return; + case 0xFC: %EXTENDED; %LDQ; return; + case 0xFD: %EXTENDED; %STQ; return; + case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return; + case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return; + + default: %ILLEGAL; return; + } + return; + +DISPATCH11: + @m_opcode = read_opcode(); + switch(m_opcode) + { + case 0x30: %BAND; return; + case 0x31: %BIAND; return; + case 0x32: %BOR; return; + case 0x33: %BIOR; return; + case 0x34: %BEOR; return; + case 0x35: %BIEOR; return; + case 0x36: %LDBT; return; + case 0x37: %STBT; return; + case 0x38: %TFM; return; + case 0x39: %TFM; return; + case 0x3A: %TFM; return; + case 0x3B: %TFM; return; + case 0x3C: set_regop8(m_md); set_imm(); %BIT8; return; + case 0x3D: set_regop8(m_md); set_imm(); %LD8; return; + case 0x3F: %SWI3; return; + + case 0x43: set_e(); %COM8; return; + case 0x4A: set_e(); %DEC8; return; + case 0x4C: set_e(); %INC8; return; + case 0x4D: set_e(); %TST8; return; + case 0x4F: set_e(); %CLR8; return; + + case 0x53: set_f(); %COM8; return; + case 0x5A: set_f(); %DEC8; return; + case 0x5C: set_f(); %INC8; return; + case 0x5D: set_f(); %TST8; return; + case 0x5F: set_f(); %CLR8; return; + + case 0x80: set_regop8(m_q.r.e); set_imm(); %SUB8; return; + case 0x81: set_regop8(m_q.r.e); set_imm(); %CMP8; return; + case 0x83: set_regop16(m_u); set_imm(); %CMP16; return; + case 0x86: set_regop8(m_q.r.e); set_imm(); %LD8; return; + case 0x8B: set_regop8(m_q.r.e); set_imm(); %ADD8; return; + case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return; + case 0x8D: set_imm(); %DIVD; return; + case 0x8E: set_imm(); %DIVQ; return; + case 0x8F: set_imm(); %MULD; return; + + case 0x90: set_regop8(m_q.r.e); %DIRECT; %SUB8; return; + case 0x91: set_regop8(m_q.r.e); %DIRECT; %CMP8; return; + case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return; + case 0x96: set_regop8(m_q.r.e); %DIRECT; %LD8; return; + case 0x97: set_regop8(m_q.r.e); %DIRECT; %ST8; return; + case 0x9B: set_regop8(m_q.r.e); %DIRECT; %ADD8; return; + case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return; + case 0x9D: %DIRECT; %DIVD; return; + case 0x9E: %DIRECT; %DIVQ; return; + case 0x9F: %DIRECT; %MULD; return; + + case 0xA0: set_regop8(m_q.r.e); %INDEXED; %SUB8; return; + case 0xA1: set_regop8(m_q.r.e); %INDEXED; %CMP8; return; + case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return; + case 0xA6: set_regop8(m_q.r.e); %INDEXED; %LD8; return; + case 0xA7: set_regop8(m_q.r.e); %INDEXED; %ST8; return; + case 0xAB: set_regop8(m_q.r.e); %INDEXED; %ADD8; return; + case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return; + case 0xAD: %INDEXED; %DIVD; return; + case 0xAE: %INDEXED; %DIVQ; return; + case 0xAF: %INDEXED; %MULD; return; + + case 0xB0: set_regop8(m_q.r.e); %EXTENDED; %SUB8; return; + case 0xB1: set_regop8(m_q.r.e); %EXTENDED; %CMP8; return; + case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return; + case 0xB6: set_regop8(m_q.r.e); %EXTENDED; %LD8; return; + case 0xB7: set_regop8(m_q.r.e); %EXTENDED; %ST8; return; + case 0xBB: set_regop8(m_q.r.e); %EXTENDED; %ADD8; return; + case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return; + case 0xBD: %EXTENDED; %DIVD; return; + case 0xBE: %EXTENDED; %DIVQ; return; + case 0xBF: %EXTENDED; %MULD; return; + + case 0xC0: set_regop8(m_q.r.f); set_imm(); %SUB8; return; + case 0xC1: set_regop8(m_q.r.f); set_imm(); %CMP8; return; + case 0xC6: set_regop8(m_q.r.f); set_imm(); %LD8; return; + case 0xCB: set_regop8(m_q.r.f); set_imm(); %ADD8; return; + + case 0xD0: set_regop8(m_q.r.f); %DIRECT; %SUB8; return; + case 0xD1: set_regop8(m_q.r.f); %DIRECT; %CMP8; return; + case 0xD6: set_regop8(m_q.r.f); %DIRECT; %LD8; return; + case 0xD7: set_regop8(m_q.r.f); %DIRECT; %ST8; return; + case 0xDB: set_regop8(m_q.r.f); %DIRECT; %ADD8; return; + + case 0xE0: set_regop8(m_q.r.f); %INDEXED; %SUB8; return; + case 0xE1: set_regop8(m_q.r.f); %INDEXED; %CMP8; return; + case 0xE6: set_regop8(m_q.r.f); %INDEXED; %LD8; return; + case 0xE7: set_regop8(m_q.r.f); %INDEXED; %ST8; return; + case 0xEB: set_regop8(m_q.r.f); %INDEXED; %ADD8; return; + + case 0xF0: set_regop8(m_q.r.f); %EXTENDED; %SUB8; return; + case 0xF1: set_regop8(m_q.r.f); %EXTENDED; %CMP8; return; + case 0xF6: set_regop8(m_q.r.f); %EXTENDED; %LD8; return; + case 0xF7: set_regop8(m_q.r.f); %EXTENDED; %ST8; return; + case 0xFB: set_regop8(m_q.r.f); %EXTENDED; %ADD8; return; + + default: %ILLEGAL; return; + } + return; + +#include "base6x09.lst" + +PUSH_REGISTERS: + if (m_temp.w & 0x80) + { + @write_memory(--regop16().w, m_pc.b.l); + @write_memory(--regop16().w, m_pc.b.h); + nop(); + } + if (m_temp.w & 0x40) + { + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); + nop(); + } + if (m_temp.w & 0x20) + { + @write_memory(--regop16().w, m_y.b.l); + @write_memory(--regop16().w, m_y.b.h); + nop(); + } + if (m_temp.w & 0x10) + { + @write_memory(--regop16().w, m_x.b.l); + @write_memory(--regop16().w, m_x.b.h); + nop(); + } + if (m_temp.w & 0x08) + { + @write_memory(--regop16().w, m_dp); + nop(); + } + if (m_temp.w & 0x200) + { + @write_memory(--regop16().w, m_q.r.f); + nop(); + } + if (m_temp.w & 0x100) + { + @write_memory(--regop16().w, m_q.r.e); + nop(); + } + if (m_temp.w & 0x04) + { + @write_memory(--regop16().w, m_q.r.b); + nop(); + } + if (m_temp.w & 0x02) + { + @write_memory(--regop16().w, m_q.r.a); + nop(); + } + if (m_temp.w & 0x01) + { + @write_memory(--regop16().w, m_cc); + nop(); + } + return; + +PULL_REGISTERS: + if (m_temp.w & 0x01) + { + @m_cc = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x02) + { + @m_q.r.a = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x04) + { + @m_q.r.b = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x100) + { + @m_q.r.e = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x200) + { + @m_q.r.f = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x08) + { + @m_dp = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x10) + { + @m_x.b.h = read_memory(regop16().w++); + @m_x.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x20) + { + @m_y.b.h = read_memory(regop16().w++); + @m_y.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x40) + { + @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); + @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x80) + { + @m_pc.b.h = read_memory(regop16().w++); + @m_pc.b.l = read_memory(regop16().w++); + nop(); + } + @eat(1); + return; + +INDEXED: + @m_opcode = read_opcode_arg(); + if (m_opcode & 0x80) + { + switch(m_opcode & 0x7F) + { + case 0x00: case 0x20: case 0x40: case 0x60: + m_temp.w = ireg(); + ireg()++; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3); + break; + + case 0x01: case 0x21: case 0x41: case 0x61: + case 0x11: case 0x31: case 0x51: case 0x71: + m_temp.w = ireg(); + ireg() += 2; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4); + break; + + case 0x02: case 0x22: case 0x42: case 0x62: + ireg()--; + m_temp.w = ireg(); + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3); + break; + + case 0x03: case 0x23: case 0x43: case 0x63: + case 0x13: case 0x33: case 0x53: case 0x73: + ireg() -= 2; + m_temp.w = ireg(); + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4); + break; + + case 0x04: case 0x24: case 0x44: case 0x64: + case 0x14: case 0x34: case 0x54: case 0x74: + m_temp.w = ireg(); + eat(1); + break; + + case 0x05: case 0x25: case 0x45: case 0x65: + case 0x15: case 0x35: case 0x55: case 0x75: + m_temp.w = ireg() + (int8_t) m_q.r.b; + eat(2); + break; + + case 0x06: case 0x26: case 0x46: case 0x66: + case 0x16: case 0x36: case 0x56: case 0x76: + m_temp.w = ireg() + (int8_t) m_q.r.a; + eat(2); + break; + + case 0x08: case 0x28: case 0x48: case 0x68: + case 0x18: case 0x38: case 0x58: case 0x78: + @m_temp.w = ireg() + (int8_t) read_opcode_arg(); + eat(1); + break; + + case 0x09: case 0x29: case 0x49: case 0x69: + case 0x19: case 0x39: case 0x59: case 0x79: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = ireg() + m_temp.w; + eat(hd6309_native_mode() ? 2 : 3); + break; + + case 0x0B: case 0x2B: case 0x4B: case 0x6B: + case 0x1B: case 0x3B: case 0x5B: case 0x7B: + m_temp.w = ireg() + m_q.r.d; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 5); + break; + + case 0x0C: case 0x2C: case 0x4C: case 0x6C: + case 0x1C: case 0x3C: case 0x5C: case 0x7C: + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_pc.w + (int8_t) m_temp.b.l; + eat(1); + break; + + case 0x0D: case 0x2D: case 0x4D: case 0x6D: + case 0x1D: case 0x3D: case 0x5D: case 0x7D: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_pc.w + (int16_t) m_temp.w; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); + break; + + case 0x1F: case 0x3F: case 0x5F: case 0x7F: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + eat(1); + break; + + case 0x07: case 0x27: case 0x47: case 0x67: + case 0x17: case 0x37: case 0x57: case 0x77: + // 6309 specific mode + m_temp.w = ireg() + (int8_t) m_q.r.e; + eat(2); + break; + + case 0x0A: case 0x2A: case 0x4A: case 0x6A: + case 0x1A: case 0x3A: case 0x5A: case 0x7A: + // 6309 specific mode + m_temp.w = ireg() + (int8_t) m_q.r.f; + eat(2); + break; + + case 0x0E: case 0x2E: case 0x4E: case 0x6E: + case 0x1E: case 0x3E: case 0x5E: case 0x7E: + // 6309 specific mode + m_temp.w = ireg() + m_q.r.w; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 5); + break; + + case 0x0F: + // 6309 specific mode + m_temp.w = m_q.r.w; + eat(1); + break; + + case 0x2F: + // 6309 specific mode + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_q.r.w + m_temp.w; + eat(hd6309_native_mode() ? 1 : 5); + break; + + case 0x4F: + // 6309 specific mode + m_temp.w = m_q.r.w; + m_q.r.w += 2; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); + break; + + case 0x6F: + // 6309 specific mode + m_q.r.w -= 2; + m_temp.w = m_q.r.w; + eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); + break; + + default: + goto ILLEGAL; + } + + // indirect mode + if (m_opcode & 0x10) + { + set_ea(m_temp.w); + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + eat(1); + } + } + else + { + // 5-bit offset + m_temp.w = ireg() + (int8_t) ((m_opcode & 0x0F) | (m_opcode & 0x10 ? 0xF0 : 0x00)); + eat(2); + } + @set_ea(m_temp.w); + return; + +EXG: + { + uint8_t param = read_opcode_arg(); + uint16_t reg1 = read_exgtfr_register(param >> 4); + uint16_t reg2 = read_exgtfr_register(param >> 0); + write_exgtfr_register(param >> 4, reg2); + write_exgtfr_register(param >> 0, reg1); + } + eat(hd6309_native_mode() ? 3 : 6); + return; + +TFR: + { + uint8_t param = read_opcode_arg(); + uint16_t reg = read_exgtfr_register(param >> 4); + write_exgtfr_register(param >> 0, reg); + } + eat(hd6309_native_mode() ? 2 : 4); + return; + +ILLEGAL: + m_md |= 0x40; // illegal op flag + set_ea(VECTOR_ILLEGAL); + goto SOFTWARE_INTERRUPT; + +DIVIDE_BY_ZERO: + m_md |= 0x80; // divide by zero flag + set_ea(VECTOR_ILLEGAL); + goto SOFTWARE_INTERRUPT; + +IMM_IM: + @m_temp_im = read_opcode_arg(); + return; + +JSR_ind: + // this is dubious, but the old core did this + eat(hd6309_native_mode() ? -1 : 0); + goto JSR; + +LDQ: + @m_q.r.a = read_operand(0); + @m_q.r.b = read_operand(1); + @m_q.r.e = read_operand(2); + @m_q.r.f = read_operand(3); + set_flags(CC_NZV, m_q.q); + return; + +STQ: + @write_operand(0, m_q.r.a); + @write_operand(1, m_q.r.b); + @write_operand(2, m_q.r.e); + @write_operand(3, m_q.r.f); + set_flags(CC_NZV, m_q.q); + return; + +OIM: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_V; + m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l | m_temp_im); + @eat(1); // this is just a guess + @write_operand(m_temp.b.l); + return; + +AIM: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_V; + m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l & m_temp_im); + @eat(1); // this is just a guess + @write_operand(m_temp.b.l); + return; + +EIM: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_V; + m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l ^ m_temp_im); + @eat(1); // this is just a guess + @write_operand(m_temp.b.l); + return; + +TIM: + @m_temp.b.l = read_operand(); + m_cc &= ~CC_V; + m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l & m_temp_im); + @eat(2); // this is just a guess + return; + +TFM: + // The TFM instruction takes up 6 CPU cycles, plus 3 CPU cycles + // for each byte transferred. At least three of these are spent + // reading the opcodes (00010001 001110xx xxxxxxxx). + // + // The old (pre-0.149) core allowed interrupts to interrupt + // execution of the transfer by implementing a transfer as an + // operation that executed one transfer, and bumped the program + // counter back. However, some documentation suggests that TFM + // was abortable, so we now have a get_pending_interrupt() call + // here. + // + // Lastly, I have no information on the precise sub-instruction timing + // here; the timings of the reads and writes are really just a guess. + @m_temp.b.l = read_opcode_arg(); + + while (m_q.r.w != 0x0000) + { + // TFM is abortable - we need to check for a pending interrupt + if (get_pending_interrupt() != 0) + { + m_pc.w -= 3; + return; + } + + if (!tfr_read(m_opcode, m_temp.b.l, m_temp.b.h)) + goto ILLEGAL; + @eat(0); + + if (!tfr_write(m_opcode, m_temp.b.l, m_temp.b.h)) + goto ILLEGAL; + @eat(1); + + m_q.r.w--; + } + + // Not sure if this sub instruction timing is accurate either + @eat(3); + return; + +COM16: + m_temp.b.h = read_operand(0); + m_temp.b.l = read_operand(1); + m_cc &= ~CC_V; + m_cc |= CC_C; + m_temp.w = set_flags(CC_NZ, (uint16_t) ~m_temp.w); + eat(hd6309_native_mode() ? 0 : 1); + write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ADC16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w + (m_cc & CC_C ? 1 : 0)); + eat(hd6309_native_mode() ? 0 : 1); + return; + +SBC16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w - (m_cc & CC_C ? 1 : 0)); + eat(hd6309_native_mode() ? 0 : 1); + return; + +AND16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_V; + regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w & m_temp.w); + return; + +BIT16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_V; + set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w & m_temp.w); + return; + +OR16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_V; + regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w | m_temp.w); + return; + +EOR16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_cc &= ~CC_V; + regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w ^ m_temp.w); + return; + +PSHSW: + m_temp.w = 0x300; + eat(2); + set_regop16(m_s); + goto PUSH_REGISTERS; + +PULSW: + m_temp.w = 0x300; + eat(2); + set_regop16(m_s); + goto PULL_REGISTERS; + +PSHUW: + m_temp.w = 0x300; + eat(2); + set_regop16(m_u); + goto PUSH_REGISTERS; + +PULUW: + m_temp.w = 0x300; + eat(2); + set_regop16(m_u); + goto PULL_REGISTERS; + +BAND: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() && bittest_source()); + return; + +BIAND: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() && !bittest_source()); + return; + +BOR: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() || bittest_source()); + return; + +BIOR: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() || !bittest_source()); + return; + +BEOR: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() != bittest_source()); + return; + +BIEOR: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_dest() != !bittest_source()); + return; + +LDBT: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + bittest_set(bittest_source()); + return; + +STBT: + %IMM_IM; + %DIRECT; + @m_temp.b.l = read_operand(); + if (bittest_source()) + m_temp.b.l |= (1 << ((m_temp_im >> 0) & 0x07)); + else + m_temp.b.l &= ~(1 << ((m_temp_im >> 0) & 0x07)); + @eat(2); + write_operand(m_temp.b.l); + return; + +MULD: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + muld(); + return; + +DIVQ: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + if (!divq()) + goto DIVIDE_BY_ZERO; + return; + +DIVD: + @m_temp.b.l = read_operand(); + if (!divd()) + goto DIVIDE_BY_ZERO; + return; + +SEXW: + m_q.r.d = set_flags(CC_N, (m_q.r.w & 0x8000) ? 0xFFFF : 0x0000); + if ((m_q.r.d == 0x0000) && (m_q.r.w == 0x0000)) + m_cc |= CC_Z; + else + m_cc &= ~CC_Z; + return; diff --git a/src/devices/cpu/m6809/hd6309.ops b/src/devices/cpu/m6809/hd6309.ops deleted file mode 100644 index 531828c1c46..00000000000 --- a/src/devices/cpu/m6809/hd6309.ops +++ /dev/null @@ -1,1086 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Nathan Woods -MAIN: - // check interrupt lines - switch(get_pending_interrupt()) - { - case VECTOR_NMI: goto NMI; - case VECTOR_FIRQ: goto FIRQ; - case VECTOR_IRQ: goto IRQ; - } - - // debugger hook - m_ppc = m_pc; - debugger_instruction_hook(m_pc.w); - - // opcode fetch - @m_opcode = read_opcode(); - - // dispatch opcode - switch(m_opcode) - { - case 0x00: %DIRECT; %NEG8; return; - case 0x01: %IMM_IM; %DIRECT; %OIM; return; - case 0x02: %IMM_IM; %DIRECT; %AIM; return; - case 0x03: %DIRECT; %COM8; return; - case 0x04: %DIRECT; %LSR8; return; - case 0x05: %IMM_IM; %DIRECT; %EIM; return; - case 0x06: %DIRECT; %ROR8; return; - case 0x07: %DIRECT; %ASR8; return; - case 0x08: %DIRECT; %ASL8; return; - case 0x09: %DIRECT; %ROL8; return; - case 0x0A: %DIRECT; %DEC8; return; - case 0x0B: %IMM_IM; %DIRECT; %TIM; return; - case 0x0C: %DIRECT; %INC8; return; - case 0x0D: %DIRECT; %TST8; return; - case 0x0E: %DIRECT; %JMP; return; - case 0x0F: %DIRECT; %CLR8; return; - - case 0x10: %DISPATCH10; return; - case 0x11: %DISPATCH11; return; - case 0x12: %NOP; return; - case 0x13: %SYNC; return; - case 0x14: %SEXW; return; - case 0x16: set_cond(true); %LBRANCH; return; - case 0x17: %LBSR; return; - case 0x19: %DAA; return; - case 0x1A: set_imm(); %ORCC; return; - case 0x1C: set_imm(); %ANDCC; return; - case 0x1D: %SEX; return; - case 0x1E: %EXG; return; - case 0x1F: %TFR; return; - - case 0x20: set_cond(true); %BRANCH; return; - case 0x21: set_cond(false); %BRANCH; return; - case 0x22: set_cond(cond_hi()); %BRANCH; return; - case 0x23: set_cond(!cond_hi()); %BRANCH; return; - case 0x24: set_cond(cond_cc()); %BRANCH; return; - case 0x25: set_cond(!cond_cc()); %BRANCH; return; - case 0x26: set_cond(cond_ne()); %BRANCH; return; - case 0x27: set_cond(!cond_ne()); %BRANCH; return; - case 0x28: set_cond(cond_vc()); %BRANCH; return; - case 0x29: set_cond(!cond_vc()); %BRANCH; return; - case 0x2A: set_cond(cond_pl()); %BRANCH; return; - case 0x2B: set_cond(!cond_pl()); %BRANCH; return; - case 0x2C: set_cond(cond_ge()); %BRANCH; return; - case 0x2D: set_cond(!cond_ge()); %BRANCH; return; - case 0x2E: set_cond(cond_gt()); %BRANCH; return; - case 0x2F: set_cond(!cond_gt()); %BRANCH; return; - - case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return; - case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return; - case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return; - case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return; - case 0x34: %PSHS; return; - case 0x35: %PULS; return; - case 0x36: %PSHU; return; - case 0x37: %PULU; return; - case 0x39: %RTS; return; - case 0x3A: %ABX; return; - case 0x3B: %RTI; return; - case 0x3C: %CWAI; return; - case 0x3D: %MUL; return; - case 0x3F: %SWI; return; - - case 0x40: set_a(); %NEG8; return; - case 0x43: set_a(); %COM8; return; - case 0x44: set_a(); %LSR8; return; - case 0x46: set_a(); %ROR8; return; - case 0x47: set_a(); %ASR8; return; - case 0x48: set_a(); %ASL8; return; - case 0x49: set_a(); %ROL8; return; - case 0x4A: set_a(); %DEC8; return; - case 0x4C: set_a(); %INC8; return; - case 0x4D: set_a(); %TST8; return; - case 0x4F: set_a(); %CLR8; return; - - case 0x50: set_b(); %NEG8; return; - case 0x53: set_b(); %COM8; return; - case 0x54: set_b(); %LSR8; return; - case 0x56: set_b(); %ROR8; return; - case 0x57: set_b(); %ASR8; return; - case 0x58: set_b(); %ASL8; return; - case 0x59: set_b(); %ROL8; return; - case 0x5A: set_b(); %DEC8; return; - case 0x5C: set_b(); %INC8; return; - case 0x5D: set_b(); %TST8; return; - case 0x5F: set_b(); %CLR8; return; - - case 0x60: %INDEXED; %NEG8; return; - case 0x61: %IMM_IM; %INDEXED; %OIM; return; - case 0x62: %IMM_IM; %INDEXED; %AIM; return; - case 0x63: %INDEXED; %COM8; return; - case 0x64: %INDEXED; %LSR8; return; - case 0x65: %IMM_IM; %INDEXED; %EIM; return; - case 0x66: %INDEXED; %ROR8; return; - case 0x67: %INDEXED; %ASR8; return; - case 0x68: %INDEXED; %ASL8; return; - case 0x69: %INDEXED; %ROL8; return; - case 0x6A: %INDEXED; %DEC8; return; - case 0x6B: %IMM_IM; %INDEXED; %TIM; return; - case 0x6C: %INDEXED; %INC8; return; - case 0x6D: %INDEXED; %TST8; return; - case 0x6E: %INDEXED; %JMP; return; - case 0x6F: %INDEXED; %CLR8; return; - - case 0x70: %EXTENDED; %NEG8; return; - case 0x71: %IMM_IM; %EXTENDED; %OIM; return; - case 0x72: %IMM_IM; %EXTENDED; %AIM; return; - case 0x73: %EXTENDED; %COM8; return; - case 0x74: %EXTENDED; %LSR8; return; - case 0x75: %IMM_IM; %EXTENDED; %EIM; return; - case 0x76: %EXTENDED; %ROR8; return; - case 0x77: %EXTENDED; %ASR8; return; - case 0x78: %EXTENDED; %ASL8; return; - case 0x79: %EXTENDED; %ROL8; return; - case 0x7A: %EXTENDED; %DEC8; return; - case 0x7B: %IMM_IM; %EXTENDED; %TIM; return; - case 0x7C: %EXTENDED; %INC8; return; - case 0x7D: %EXTENDED; %TST8; return; - case 0x7E: %EXTENDED; %JMP; return; - case 0x7F: %EXTENDED; %CLR8; return; - - case 0x80: set_regop8(m_q.r.a); set_imm(); %SUB8; return; - case 0x81: set_regop8(m_q.r.a); set_imm(); %CMP8; return; - case 0x82: set_regop8(m_q.r.a); set_imm(); %SBC8; return; - case 0x83: set_regop16(m_q.p.d); set_imm(); %SUB16; return; - case 0x84: set_regop8(m_q.r.a); set_imm(); %AND8; return; - case 0x85: set_regop8(m_q.r.a); set_imm(); %BIT8; return; - case 0x86: set_regop8(m_q.r.a); set_imm(); %LD8; return; - case 0x88: set_regop8(m_q.r.a); set_imm(); %EOR8; return; - case 0x89: set_regop8(m_q.r.a); set_imm(); %ADC8; return; - case 0x8A: set_regop8(m_q.r.a); set_imm(); %OR8; return; - case 0x8B: set_regop8(m_q.r.a); set_imm(); %ADD8; return; - case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return; - case 0x8D: %BSR; return; - case 0x8E: set_regop16(m_x); set_imm(); %LD16; return; - - case 0x90: set_regop8(m_q.r.a); %DIRECT; %SUB8; return; - case 0x91: set_regop8(m_q.r.a); %DIRECT; %CMP8; return; - case 0x92: set_regop8(m_q.r.a); %DIRECT; %SBC8; return; - case 0x93: set_regop16(m_q.p.d); %DIRECT; %SUB16; return; - case 0x94: set_regop8(m_q.r.a); %DIRECT; %AND8; return; - case 0x95: set_regop8(m_q.r.a); %DIRECT; %BIT8; return; - case 0x96: set_regop8(m_q.r.a); %DIRECT; %LD8; return; - case 0x97: set_regop8(m_q.r.a); %DIRECT; %ST8; return; - case 0x98: set_regop8(m_q.r.a); %DIRECT; %EOR8; return; - case 0x99: set_regop8(m_q.r.a); %DIRECT; %ADC8; return; - case 0x9A: set_regop8(m_q.r.a); %DIRECT; %OR8; return; - case 0x9B: set_regop8(m_q.r.a); %DIRECT; %ADD8; return; - case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return; - case 0x9D: %DIRECT; %JSR; return; - case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return; - case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return; - - case 0xA0: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; - case 0xA1: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; - case 0xA2: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; - case 0xA3: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; - case 0xA4: set_regop8(m_q.r.a); %INDEXED; %AND8; return; - case 0xA5: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; - case 0xA6: set_regop8(m_q.r.a); %INDEXED; %LD8; return; - case 0xA7: set_regop8(m_q.r.a); %INDEXED; %ST8; return; - case 0xA8: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; - case 0xA9: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; - case 0xAA: set_regop8(m_q.r.a); %INDEXED; %OR8; return; - case 0xAB: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; - case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return; - case 0xAD: %INDEXED; %JSR_ind; return; - case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return; - case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return; - - case 0xB0: set_regop8(m_q.r.a); %EXTENDED; %SUB8; return; - case 0xB1: set_regop8(m_q.r.a); %EXTENDED; %CMP8; return; - case 0xB2: set_regop8(m_q.r.a); %EXTENDED; %SBC8; return; - case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %SUB16; return; - case 0xB4: set_regop8(m_q.r.a); %EXTENDED; %AND8; return; - case 0xB5: set_regop8(m_q.r.a); %EXTENDED; %BIT8; return; - case 0xB6: set_regop8(m_q.r.a); %EXTENDED; %LD8; return; - case 0xB7: set_regop8(m_q.r.a); %EXTENDED; %ST8; return; - case 0xB8: set_regop8(m_q.r.a); %EXTENDED; %EOR8; return; - case 0xB9: set_regop8(m_q.r.a); %EXTENDED; %ADC8; return; - case 0xBA: set_regop8(m_q.r.a); %EXTENDED; %OR8; return; - case 0xBB: set_regop8(m_q.r.a); %EXTENDED; %ADD8; return; - case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return; - case 0xBD: %EXTENDED; %JSR; return; - case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return; - case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return; - - case 0xC0: set_regop8(m_q.r.b); set_imm(); %SUB8; return; - case 0xC1: set_regop8(m_q.r.b); set_imm(); %CMP8; return; - case 0xC2: set_regop8(m_q.r.b); set_imm(); %SBC8; return; - case 0xC3: set_regop16(m_q.p.d); set_imm(); %ADD16; return; - case 0xC4: set_regop8(m_q.r.b); set_imm(); %AND8; return; - case 0xC5: set_regop8(m_q.r.b); set_imm(); %BIT8; return; - case 0xC6: set_regop8(m_q.r.b); set_imm(); %LD8; return; - case 0xC8: set_regop8(m_q.r.b); set_imm(); %EOR8; return; - case 0xC9: set_regop8(m_q.r.b); set_imm(); %ADC8; return; - case 0xCA: set_regop8(m_q.r.b); set_imm(); %OR8; return; - case 0xCB: set_regop8(m_q.r.b); set_imm(); %ADD8; return; - case 0xCC: set_regop16(m_q.p.d); set_imm(); %LD16; return; - case 0xCD: set_imm(); %LDQ; return; - case 0xCE: set_regop16(m_u); set_imm(); %LD16; return; - - case 0xD0: set_regop8(m_q.r.b); %DIRECT; %SUB8; return; - case 0xD1: set_regop8(m_q.r.b); %DIRECT; %CMP8; return; - case 0xD2: set_regop8(m_q.r.b); %DIRECT; %SBC8; return; - case 0xD3: set_regop16(m_q.p.d); %DIRECT; %ADD16; return; - case 0xD4: set_regop8(m_q.r.b); %DIRECT; %AND8; return; - case 0xD5: set_regop8(m_q.r.b); %DIRECT; %BIT8; return; - case 0xD6: set_regop8(m_q.r.b); %DIRECT; %LD8; return; - case 0xD7: set_regop8(m_q.r.b); %DIRECT; %ST8; return; - case 0xD8: set_regop8(m_q.r.b); %DIRECT; %EOR8; return; - case 0xD9: set_regop8(m_q.r.b); %DIRECT; %ADC8; return; - case 0xDA: set_regop8(m_q.r.b); %DIRECT; %OR8; return; - case 0xDB: set_regop8(m_q.r.b); %DIRECT; %ADD8; return; - case 0xDC: set_regop16(m_q.p.d); %DIRECT; %LD16; return; - case 0xDD: set_regop16(m_q.p.d); %DIRECT; %ST16; return; - case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return; - case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return; - - case 0xE0: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; - case 0xE1: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; - case 0xE2: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; - case 0xE3: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; - case 0xE4: set_regop8(m_q.r.b); %INDEXED; %AND8; return; - case 0xE5: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; - case 0xE6: set_regop8(m_q.r.b); %INDEXED; %LD8; return; - case 0xE7: set_regop8(m_q.r.b); %INDEXED; %ST8; return; - case 0xE8: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; - case 0xE9: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; - case 0xEA: set_regop8(m_q.r.b); %INDEXED; %OR8; return; - case 0xEB: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; - case 0xEC: set_regop16(m_q.p.d); %INDEXED; %LD16; return; - case 0xED: set_regop16(m_q.p.d); %INDEXED; %ST16; return; - case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return; - case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return; - - case 0xF0: set_regop8(m_q.r.b); %EXTENDED; %SUB8; return; - case 0xF1: set_regop8(m_q.r.b); %EXTENDED; %CMP8; return; - case 0xF2: set_regop8(m_q.r.b); %EXTENDED; %SBC8; return; - case 0xF3: set_regop16(m_q.p.d); %EXTENDED; %ADD16; return; - case 0xF4: set_regop8(m_q.r.b); %EXTENDED; %AND8; return; - case 0xF5: set_regop8(m_q.r.b); %EXTENDED; %BIT8; return; - case 0xF6: set_regop8(m_q.r.b); %EXTENDED; %LD8; return; - case 0xF7: set_regop8(m_q.r.b); %EXTENDED; %ST8; return; - case 0xF8: set_regop8(m_q.r.b); %EXTENDED; %EOR8; return; - case 0xF9: set_regop8(m_q.r.b); %EXTENDED; %ADC8; return; - case 0xFA: set_regop8(m_q.r.b); %EXTENDED; %OR8; return; - case 0xFB: set_regop8(m_q.r.b); %EXTENDED; %ADD8; return; - case 0xFC: set_regop16(m_q.p.d); %EXTENDED; %LD16; return; - case 0xFD: set_regop16(m_q.p.d); %EXTENDED; %ST16; return; - case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return; - case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return; - default: %ILLEGAL; return; - } - return; - -DISPATCH10: - @m_opcode = read_opcode(); - switch(m_opcode) - { - case 0x21: set_cond(false); %LBRANCH; return; - case 0x22: set_cond(cond_hi()); %LBRANCH; return; - case 0x23: set_cond(!cond_hi()); %LBRANCH; return; - case 0x24: set_cond(cond_cc()); %LBRANCH; return; - case 0x25: set_cond(!cond_cc()); %LBRANCH; return; - case 0x26: set_cond(cond_ne()); %LBRANCH; return; - case 0x27: set_cond(!cond_ne()); %LBRANCH; return; - case 0x28: set_cond(cond_vc()); %LBRANCH; return; - case 0x29: set_cond(!cond_vc()); %LBRANCH; return; - case 0x2A: set_cond(cond_pl()); %LBRANCH; return; - case 0x2B: set_cond(!cond_pl()); %LBRANCH; return; - case 0x2C: set_cond(cond_ge()); %LBRANCH; return; - case 0x2D: set_cond(!cond_ge()); %LBRANCH; return; - case 0x2E: set_cond(cond_gt()); %LBRANCH; return; - case 0x2F: set_cond(!cond_gt()); %LBRANCH; return; - - case 0x30: register_register_op(); %ADD*; return; - case 0x31: register_register_op(); %ADC*; return; - case 0x32: register_register_op(); %SUB*; return; - case 0x33: register_register_op(); %SBC*; return; - case 0x34: register_register_op(); %AND*; return; - case 0x35: register_register_op(); %OR*; return; - case 0x36: register_register_op(); %EOR*; return; - case 0x37: register_register_op(); %CMP*; return; - case 0x38: %PSHSW; return; - case 0x39: %PULSW; return; - case 0x3A: %PSHUW; return; - case 0x3B: %PULUW; return; - case 0x3F: %SWI2; return; - - case 0x40: set_d(); %NEG16; return; - case 0x43: set_d(); %COM16; return; - case 0x44: set_d(); %LSR16; return; - case 0x46: set_d(); %ROR16; return; - case 0x47: set_d(); %ASR16; return; - case 0x48: set_d(); %ASL16; return; - case 0x49: set_d(); %ROL16; return; - case 0x4A: set_d(); %DEC16; return; - case 0x4C: set_d(); %INC16; return; - case 0x4D: set_d(); %TST16; return; - case 0x4F: set_d(); %CLR16; return; - - case 0x50: set_w(); %NEG16; return; - case 0x53: set_w(); %COM16; return; - case 0x54: set_w(); %LSR16; return; - case 0x56: set_w(); %ROR16; return; - case 0x57: set_w(); %ASR16; return; - case 0x58: set_w(); %ASL16; return; - case 0x59: set_w(); %ROL16; return; - case 0x5A: set_w(); %DEC16; return; - case 0x5C: set_w(); %INC16; return; - case 0x5D: set_w(); %TST16; return; - case 0x5F: set_w(); %CLR16; return; - - case 0x80: set_regop16(m_q.p.w); set_imm(); %SUB16; return; - case 0x81: set_regop16(m_q.p.w); set_imm(); %CMP16; return; - case 0x82: set_regop16(m_q.p.d); set_imm(); %SBC16; return; - case 0x83: set_regop16(m_q.p.d); set_imm(); %CMP16; return; - case 0x84: set_regop16(m_q.p.d); set_imm(); %AND16; return; - case 0x85: set_regop16(m_q.p.d); set_imm(); %BIT16; return; - case 0x86: set_regop16(m_q.p.w); set_imm(); %LD16; return; - case 0x88: set_regop16(m_q.p.d); set_imm(); %EOR16; return; - case 0x89: set_regop16(m_q.p.d); set_imm(); %ADC16; return; - case 0x8A: set_regop16(m_q.p.d); set_imm(); %OR16; return; - case 0x8B: set_regop16(m_q.p.w); set_imm(); %ADD16; return; - case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return; - case 0x8E: set_regop16(m_y); set_imm(); %LD16; return; - - case 0x90: set_regop16(m_q.p.w); %DIRECT; %SUB16; return; - case 0x91: set_regop16(m_q.p.w); %DIRECT; %CMP16; return; - case 0x92: set_regop16(m_q.p.d); %DIRECT; %SBC16; return; - case 0x93: set_regop16(m_q.p.d); %DIRECT; %CMP16; return; - case 0x94: set_regop16(m_q.p.d); %DIRECT; %AND16; return; - case 0x95: set_regop16(m_q.p.d); %DIRECT; %BIT16; return; - case 0x96: set_regop16(m_q.p.w); %DIRECT; %LD16; return; - case 0x97: set_regop16(m_q.p.w); %DIRECT; %ST16; return; - case 0x98: set_regop16(m_q.p.d); %DIRECT; %EOR16; return; - case 0x99: set_regop16(m_q.p.d); %DIRECT; %ADC16; return; - case 0x9A: set_regop16(m_q.p.d); %DIRECT; %OR16; return; - case 0x9B: set_regop16(m_q.p.w); %DIRECT; %ADD16; return; - case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return; - case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return; - case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return; - - case 0xA0: set_regop16(m_q.p.w); %INDEXED; %SUB16; return; - case 0xA1: set_regop16(m_q.p.w); %INDEXED; %CMP16; return; - case 0xA2: set_regop16(m_q.p.d); %INDEXED; %SBC16; return; - case 0xA3: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; - case 0xA4: set_regop16(m_q.p.d); %INDEXED; %AND16; return; - case 0xA5: set_regop16(m_q.p.d); %INDEXED; %BIT16; return; - case 0xA6: set_regop16(m_q.p.w); %INDEXED; %LD16; return; - case 0xA7: set_regop16(m_q.p.w); %INDEXED; %ST16; return; - case 0xA8: set_regop16(m_q.p.d); %INDEXED; %EOR16; return; - case 0xA9: set_regop16(m_q.p.d); %INDEXED; %ADC16; return; - case 0xAA: set_regop16(m_q.p.d); %INDEXED; %OR16; return; - case 0xAB: set_regop16(m_q.p.w); %INDEXED; %ADD16; return; - case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return; - case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return; - case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return; - - case 0xB0: set_regop16(m_q.p.w); %EXTENDED; %SUB16; return; - case 0xB1: set_regop16(m_q.p.w); %EXTENDED; %CMP16; return; - case 0xB2: set_regop16(m_q.p.d); %EXTENDED; %SBC16; return; - case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %CMP16; return; - case 0xB4: set_regop16(m_q.p.d); %EXTENDED; %AND16; return; - case 0xB5: set_regop16(m_q.p.d); %EXTENDED; %BIT16; return; - case 0xB6: set_regop16(m_q.p.w); %EXTENDED; %LD16; return; - case 0xB7: set_regop16(m_q.p.w); %EXTENDED; %ST16; return; - case 0xB8: set_regop16(m_q.p.d); %EXTENDED; %EOR16; return; - case 0xB9: set_regop16(m_q.p.d); %EXTENDED; %ADC16; return; - case 0xBA: set_regop16(m_q.p.d); %EXTENDED; %OR16; return; - case 0xBB: set_regop16(m_q.p.w); %EXTENDED; %ADD16; return; - case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return; - case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return; - case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return; - - case 0xCE: set_regop16(m_s); set_imm(); %LD16; return; - case 0xDC: %DIRECT; %LDQ; return; - case 0xDD: %DIRECT; %STQ; return; - case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return; - case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return; - case 0xEC: %INDEXED; %LDQ; return; - case 0xED: %INDEXED; %STQ; return; - case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return; - case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return; - case 0xFC: %EXTENDED; %LDQ; return; - case 0xFD: %EXTENDED; %STQ; return; - case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return; - case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return; - - default: %ILLEGAL; return; - } - return; - -DISPATCH11: - @m_opcode = read_opcode(); - switch(m_opcode) - { - case 0x30: %BAND; return; - case 0x31: %BIAND; return; - case 0x32: %BOR; return; - case 0x33: %BIOR; return; - case 0x34: %BEOR; return; - case 0x35: %BIEOR; return; - case 0x36: %LDBT; return; - case 0x37: %STBT; return; - case 0x38: %TFM; return; - case 0x39: %TFM; return; - case 0x3A: %TFM; return; - case 0x3B: %TFM; return; - case 0x3C: set_regop8(m_md); set_imm(); %BIT8; return; - case 0x3D: set_regop8(m_md); set_imm(); %LD8; return; - case 0x3F: %SWI3; return; - - case 0x43: set_e(); %COM8; return; - case 0x4A: set_e(); %DEC8; return; - case 0x4C: set_e(); %INC8; return; - case 0x4D: set_e(); %TST8; return; - case 0x4F: set_e(); %CLR8; return; - - case 0x53: set_f(); %COM8; return; - case 0x5A: set_f(); %DEC8; return; - case 0x5C: set_f(); %INC8; return; - case 0x5D: set_f(); %TST8; return; - case 0x5F: set_f(); %CLR8; return; - - case 0x80: set_regop8(m_q.r.e); set_imm(); %SUB8; return; - case 0x81: set_regop8(m_q.r.e); set_imm(); %CMP8; return; - case 0x83: set_regop16(m_u); set_imm(); %CMP16; return; - case 0x86: set_regop8(m_q.r.e); set_imm(); %LD8; return; - case 0x8B: set_regop8(m_q.r.e); set_imm(); %ADD8; return; - case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return; - case 0x8D: set_imm(); %DIVD; return; - case 0x8E: set_imm(); %DIVQ; return; - case 0x8F: set_imm(); %MULD; return; - - case 0x90: set_regop8(m_q.r.e); %DIRECT; %SUB8; return; - case 0x91: set_regop8(m_q.r.e); %DIRECT; %CMP8; return; - case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return; - case 0x96: set_regop8(m_q.r.e); %DIRECT; %LD8; return; - case 0x97: set_regop8(m_q.r.e); %DIRECT; %ST8; return; - case 0x9B: set_regop8(m_q.r.e); %DIRECT; %ADD8; return; - case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return; - case 0x9D: %DIRECT; %DIVD; return; - case 0x9E: %DIRECT; %DIVQ; return; - case 0x9F: %DIRECT; %MULD; return; - - case 0xA0: set_regop8(m_q.r.e); %INDEXED; %SUB8; return; - case 0xA1: set_regop8(m_q.r.e); %INDEXED; %CMP8; return; - case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return; - case 0xA6: set_regop8(m_q.r.e); %INDEXED; %LD8; return; - case 0xA7: set_regop8(m_q.r.e); %INDEXED; %ST8; return; - case 0xAB: set_regop8(m_q.r.e); %INDEXED; %ADD8; return; - case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return; - case 0xAD: %INDEXED; %DIVD; return; - case 0xAE: %INDEXED; %DIVQ; return; - case 0xAF: %INDEXED; %MULD; return; - - case 0xB0: set_regop8(m_q.r.e); %EXTENDED; %SUB8; return; - case 0xB1: set_regop8(m_q.r.e); %EXTENDED; %CMP8; return; - case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return; - case 0xB6: set_regop8(m_q.r.e); %EXTENDED; %LD8; return; - case 0xB7: set_regop8(m_q.r.e); %EXTENDED; %ST8; return; - case 0xBB: set_regop8(m_q.r.e); %EXTENDED; %ADD8; return; - case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return; - case 0xBD: %EXTENDED; %DIVD; return; - case 0xBE: %EXTENDED; %DIVQ; return; - case 0xBF: %EXTENDED; %MULD; return; - - case 0xC0: set_regop8(m_q.r.f); set_imm(); %SUB8; return; - case 0xC1: set_regop8(m_q.r.f); set_imm(); %CMP8; return; - case 0xC6: set_regop8(m_q.r.f); set_imm(); %LD8; return; - case 0xCB: set_regop8(m_q.r.f); set_imm(); %ADD8; return; - - case 0xD0: set_regop8(m_q.r.f); %DIRECT; %SUB8; return; - case 0xD1: set_regop8(m_q.r.f); %DIRECT; %CMP8; return; - case 0xD6: set_regop8(m_q.r.f); %DIRECT; %LD8; return; - case 0xD7: set_regop8(m_q.r.f); %DIRECT; %ST8; return; - case 0xDB: set_regop8(m_q.r.f); %DIRECT; %ADD8; return; - - case 0xE0: set_regop8(m_q.r.f); %INDEXED; %SUB8; return; - case 0xE1: set_regop8(m_q.r.f); %INDEXED; %CMP8; return; - case 0xE6: set_regop8(m_q.r.f); %INDEXED; %LD8; return; - case 0xE7: set_regop8(m_q.r.f); %INDEXED; %ST8; return; - case 0xEB: set_regop8(m_q.r.f); %INDEXED; %ADD8; return; - - case 0xF0: set_regop8(m_q.r.f); %EXTENDED; %SUB8; return; - case 0xF1: set_regop8(m_q.r.f); %EXTENDED; %CMP8; return; - case 0xF6: set_regop8(m_q.r.f); %EXTENDED; %LD8; return; - case 0xF7: set_regop8(m_q.r.f); %EXTENDED; %ST8; return; - case 0xFB: set_regop8(m_q.r.f); %EXTENDED; %ADD8; return; - - default: %ILLEGAL; return; - } - return; - -#include "base6x09.ops" - -PUSH_REGISTERS: - if (m_temp.w & 0x80) - { - @write_memory(--regop16().w, m_pc.b.l); - @write_memory(--regop16().w, m_pc.b.h); - nop(); - } - if (m_temp.w & 0x40) - { - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); - nop(); - } - if (m_temp.w & 0x20) - { - @write_memory(--regop16().w, m_y.b.l); - @write_memory(--regop16().w, m_y.b.h); - nop(); - } - if (m_temp.w & 0x10) - { - @write_memory(--regop16().w, m_x.b.l); - @write_memory(--regop16().w, m_x.b.h); - nop(); - } - if (m_temp.w & 0x08) - { - @write_memory(--regop16().w, m_dp); - nop(); - } - if (m_temp.w & 0x200) - { - @write_memory(--regop16().w, m_q.r.f); - nop(); - } - if (m_temp.w & 0x100) - { - @write_memory(--regop16().w, m_q.r.e); - nop(); - } - if (m_temp.w & 0x04) - { - @write_memory(--regop16().w, m_q.r.b); - nop(); - } - if (m_temp.w & 0x02) - { - @write_memory(--regop16().w, m_q.r.a); - nop(); - } - if (m_temp.w & 0x01) - { - @write_memory(--regop16().w, m_cc); - nop(); - } - return; - -PULL_REGISTERS: - if (m_temp.w & 0x01) - { - @m_cc = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x02) - { - @m_q.r.a = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x04) - { - @m_q.r.b = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x100) - { - @m_q.r.e = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x200) - { - @m_q.r.f = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x08) - { - @m_dp = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x10) - { - @m_x.b.h = read_memory(regop16().w++); - @m_x.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x20) - { - @m_y.b.h = read_memory(regop16().w++); - @m_y.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x40) - { - @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); - @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x80) - { - @m_pc.b.h = read_memory(regop16().w++); - @m_pc.b.l = read_memory(regop16().w++); - nop(); - } - @eat(1); - return; - -INDEXED: - @m_opcode = read_opcode_arg(); - if (m_opcode & 0x80) - { - switch(m_opcode & 0x7F) - { - case 0x00: case 0x20: case 0x40: case 0x60: - m_temp.w = ireg(); - ireg()++; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3); - break; - - case 0x01: case 0x21: case 0x41: case 0x61: - case 0x11: case 0x31: case 0x51: case 0x71: - m_temp.w = ireg(); - ireg() += 2; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4); - break; - - case 0x02: case 0x22: case 0x42: case 0x62: - ireg()--; - m_temp.w = ireg(); - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3); - break; - - case 0x03: case 0x23: case 0x43: case 0x63: - case 0x13: case 0x33: case 0x53: case 0x73: - ireg() -= 2; - m_temp.w = ireg(); - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4); - break; - - case 0x04: case 0x24: case 0x44: case 0x64: - case 0x14: case 0x34: case 0x54: case 0x74: - m_temp.w = ireg(); - eat(1); - break; - - case 0x05: case 0x25: case 0x45: case 0x65: - case 0x15: case 0x35: case 0x55: case 0x75: - m_temp.w = ireg() + (int8_t) m_q.r.b; - eat(2); - break; - - case 0x06: case 0x26: case 0x46: case 0x66: - case 0x16: case 0x36: case 0x56: case 0x76: - m_temp.w = ireg() + (int8_t) m_q.r.a; - eat(2); - break; - - case 0x08: case 0x28: case 0x48: case 0x68: - case 0x18: case 0x38: case 0x58: case 0x78: - @m_temp.w = ireg() + (int8_t) read_opcode_arg(); - eat(1); - break; - - case 0x09: case 0x29: case 0x49: case 0x69: - case 0x19: case 0x39: case 0x59: case 0x79: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = ireg() + m_temp.w; - eat(hd6309_native_mode() ? 2 : 3); - break; - - case 0x0B: case 0x2B: case 0x4B: case 0x6B: - case 0x1B: case 0x3B: case 0x5B: case 0x7B: - m_temp.w = ireg() + m_q.r.d; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 5); - break; - - case 0x0C: case 0x2C: case 0x4C: case 0x6C: - case 0x1C: case 0x3C: case 0x5C: case 0x7C: - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_pc.w + (int8_t) m_temp.b.l; - eat(1); - break; - - case 0x0D: case 0x2D: case 0x4D: case 0x6D: - case 0x1D: case 0x3D: case 0x5D: case 0x7D: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_pc.w + (int16_t) m_temp.w; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); - break; - - case 0x1F: case 0x3F: case 0x5F: case 0x7F: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - eat(1); - break; - - case 0x07: case 0x27: case 0x47: case 0x67: - case 0x17: case 0x37: case 0x57: case 0x77: - // 6309 specific mode - m_temp.w = ireg() + (int8_t) m_q.r.e; - eat(2); - break; - - case 0x0A: case 0x2A: case 0x4A: case 0x6A: - case 0x1A: case 0x3A: case 0x5A: case 0x7A: - // 6309 specific mode - m_temp.w = ireg() + (int8_t) m_q.r.f; - eat(2); - break; - - case 0x0E: case 0x2E: case 0x4E: case 0x6E: - case 0x1E: case 0x3E: case 0x5E: case 0x7E: - // 6309 specific mode - m_temp.w = ireg() + m_q.r.w; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 5); - break; - - case 0x0F: - // 6309 specific mode - m_temp.w = m_q.r.w; - eat(1); - break; - - case 0x2F: - // 6309 specific mode - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_q.r.w + m_temp.w; - eat(hd6309_native_mode() ? 1 : 5); - break; - - case 0x4F: - // 6309 specific mode - m_temp.w = m_q.r.w; - m_q.r.w += 2; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); - break; - - case 0x6F: - // 6309 specific mode - m_q.r.w -= 2; - m_temp.w = m_q.r.w; - eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4); - break; - - default: - goto ILLEGAL; - } - - // indirect mode - if (m_opcode & 0x10) - { - set_ea(m_temp.w); - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - eat(1); - } - } - else - { - // 5-bit offset - m_temp.w = ireg() + (int8_t) ((m_opcode & 0x0F) | (m_opcode & 0x10 ? 0xF0 : 0x00)); - eat(2); - } - @set_ea(m_temp.w); - return; - -EXG: - { - uint8_t param = read_opcode_arg(); - uint16_t reg1 = read_exgtfr_register(param >> 4); - uint16_t reg2 = read_exgtfr_register(param >> 0); - write_exgtfr_register(param >> 4, reg2); - write_exgtfr_register(param >> 0, reg1); - } - eat(hd6309_native_mode() ? 3 : 6); - return; - -TFR: - { - uint8_t param = read_opcode_arg(); - uint16_t reg = read_exgtfr_register(param >> 4); - write_exgtfr_register(param >> 0, reg); - } - eat(hd6309_native_mode() ? 2 : 4); - return; - -ILLEGAL: - m_md |= 0x40; // illegal op flag - set_ea(VECTOR_ILLEGAL); - goto SOFTWARE_INTERRUPT; - -DIVIDE_BY_ZERO: - m_md |= 0x80; // divide by zero flag - set_ea(VECTOR_ILLEGAL); - goto SOFTWARE_INTERRUPT; - -IMM_IM: - @m_temp_im = read_opcode_arg(); - return; - -JSR_ind: - // this is dubious, but the old core did this - eat(hd6309_native_mode() ? -1 : 0); - goto JSR; - -LDQ: - @m_q.r.a = read_operand(0); - @m_q.r.b = read_operand(1); - @m_q.r.e = read_operand(2); - @m_q.r.f = read_operand(3); - set_flags(CC_NZV, m_q.q); - return; - -STQ: - @write_operand(0, m_q.r.a); - @write_operand(1, m_q.r.b); - @write_operand(2, m_q.r.e); - @write_operand(3, m_q.r.f); - set_flags(CC_NZV, m_q.q); - return; - -OIM: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_V; - m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l | m_temp_im); - @eat(1); // this is just a guess - @write_operand(m_temp.b.l); - return; - -AIM: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_V; - m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l & m_temp_im); - @eat(1); // this is just a guess - @write_operand(m_temp.b.l); - return; - -EIM: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_V; - m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l ^ m_temp_im); - @eat(1); // this is just a guess - @write_operand(m_temp.b.l); - return; - -TIM: - @m_temp.b.l = read_operand(); - m_cc &= ~CC_V; - m_temp.b.l = set_flags(CC_NZ, (uint8_t)0, m_temp.b.l, m_temp.b.l & m_temp_im); - @eat(2); // this is just a guess - return; - -TFM: - // The TFM instruction takes up 6 CPU cycles, plus 3 CPU cycles - // for each byte transferred. At least three of these are spent - // reading the opcodes (00010001 001110xx xxxxxxxx). - // - // The old (pre-0.149) core allowed interrupts to interrupt - // execution of the transfer by implementing a transfer as an - // operation that executed one transfer, and bumped the program - // counter back. However, some documentation suggests that TFM - // was abortable, so we now have a get_pending_interrupt() call - // here. - // - // Lastly, I have no information on the precise sub-instruction timing - // here; the timings of the reads and writes are really just a guess. - @m_temp.b.l = read_opcode_arg(); - - while (m_q.r.w != 0x0000) - { - // TFM is abortable - we need to check for a pending interrupt - if (get_pending_interrupt() != 0) - { - m_pc.w -= 3; - return; - } - - if (!tfr_read(m_opcode, m_temp.b.l, m_temp.b.h)) - goto ILLEGAL; - @eat(0); - - if (!tfr_write(m_opcode, m_temp.b.l, m_temp.b.h)) - goto ILLEGAL; - @eat(1); - - m_q.r.w--; - } - - // Not sure if this sub instruction timing is accurate either - @eat(3); - return; - -COM16: - m_temp.b.h = read_operand(0); - m_temp.b.l = read_operand(1); - m_cc &= ~CC_V; - m_cc |= CC_C; - m_temp.w = set_flags(CC_NZ, (uint16_t) ~m_temp.w); - eat(hd6309_native_mode() ? 0 : 1); - write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ADC16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w + (m_cc & CC_C ? 1 : 0)); - eat(hd6309_native_mode() ? 0 : 1); - return; - -SBC16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w - (m_cc & CC_C ? 1 : 0)); - eat(hd6309_native_mode() ? 0 : 1); - return; - -AND16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_V; - regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w & m_temp.w); - return; - -BIT16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_V; - set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w & m_temp.w); - return; - -OR16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_V; - regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w | m_temp.w); - return; - -EOR16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_cc &= ~CC_V; - regop16().w = set_flags(CC_NZ, (uint16_t)0, regop16().w, regop16().w ^ m_temp.w); - return; - -PSHSW: - m_temp.w = 0x300; - eat(2); - set_regop16(m_s); - goto PUSH_REGISTERS; - -PULSW: - m_temp.w = 0x300; - eat(2); - set_regop16(m_s); - goto PULL_REGISTERS; - -PSHUW: - m_temp.w = 0x300; - eat(2); - set_regop16(m_u); - goto PUSH_REGISTERS; - -PULUW: - m_temp.w = 0x300; - eat(2); - set_regop16(m_u); - goto PULL_REGISTERS; - -BAND: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() && bittest_source()); - return; - -BIAND: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() && !bittest_source()); - return; - -BOR: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() || bittest_source()); - return; - -BIOR: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() || !bittest_source()); - return; - -BEOR: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() != bittest_source()); - return; - -BIEOR: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_dest() != !bittest_source()); - return; - -LDBT: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - bittest_set(bittest_source()); - return; - -STBT: - %IMM_IM; - %DIRECT; - @m_temp.b.l = read_operand(); - if (bittest_source()) - m_temp.b.l |= (1 << ((m_temp_im >> 0) & 0x07)); - else - m_temp.b.l &= ~(1 << ((m_temp_im >> 0) & 0x07)); - @eat(2); - write_operand(m_temp.b.l); - return; - -MULD: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - muld(); - return; - -DIVQ: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - if (!divq()) - goto DIVIDE_BY_ZERO; - return; - -DIVD: - @m_temp.b.l = read_operand(); - if (!divd()) - goto DIVIDE_BY_ZERO; - return; - -SEXW: - m_q.r.d = set_flags(CC_N, (m_q.r.w & 0x8000) ? 0xFFFF : 0x0000); - if ((m_q.r.d == 0x0000) && (m_q.r.w == 0x0000)) - m_cc |= CC_Z; - else - m_cc &= ~CC_Z; - return; diff --git a/src/devices/cpu/m6809/konami.lst b/src/devices/cpu/m6809/konami.lst new file mode 100644 index 00000000000..f2f47089cdd --- /dev/null +++ b/src/devices/cpu/m6809/konami.lst @@ -0,0 +1,628 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods +MAIN: + // check interrupt lines + switch(get_pending_interrupt()) + { + case VECTOR_NMI: goto NMI; + case VECTOR_FIRQ: goto FIRQ; + case VECTOR_IRQ: goto IRQ; + } + + // debugger hook + m_ppc = m_pc; + debugger_instruction_hook(m_pc.w); + + // opcode fetch + @m_opcode = read_opcode(); + + // dispatch opcode + switch(m_opcode) + { + case 0x08: set_regop16(m_x); %INDEXED; %LEA_xy; return; + case 0x09: set_regop16(m_y); %INDEXED; %LEA_xy; return; + case 0x0A: set_regop16(m_u); %INDEXED; %LEA_us; return; + case 0x0B: set_regop16(m_s); %INDEXED; %LEA_us; return; + case 0x0C: %PSHS; return; + case 0x0D: %PSHU; return; + case 0x0E: %PULS; return; + case 0x0F: %PULU; return; + + case 0x10: set_regop8(m_q.r.a); set_imm(); %LD8; return; + case 0x11: set_regop8(m_q.r.b); set_imm(); %LD8; return; + case 0x12: set_regop8(m_q.r.a); %INDEXED; %LD8; return; + case 0x13: set_regop8(m_q.r.b); %INDEXED; %LD8; return; + case 0x14: set_regop8(m_q.r.a); set_imm(); %ADD8; return; + case 0x15: set_regop8(m_q.r.b); set_imm(); %ADD8; return; + case 0x16: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; + case 0x17: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; + case 0x18: set_regop8(m_q.r.a); set_imm(); %ADC8; return; + case 0x19: set_regop8(m_q.r.b); set_imm(); %ADC8; return; + case 0x1A: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; + case 0x1B: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; + case 0x1C: set_regop8(m_q.r.a); set_imm(); %SUB8; return; + case 0x1D: set_regop8(m_q.r.b); set_imm(); %SUB8; return; + case 0x1E: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; + case 0x1F: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; + + case 0x20: set_regop8(m_q.r.a); set_imm(); %SBC8; return; + case 0x21: set_regop8(m_q.r.b); set_imm(); %SBC8; return; + case 0x22: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; + case 0x23: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; + case 0x24: set_regop8(m_q.r.a); set_imm(); %AND8; return; + case 0x25: set_regop8(m_q.r.b); set_imm(); %AND8; return; + case 0x26: set_regop8(m_q.r.a); %INDEXED; %AND8; return; + case 0x27: set_regop8(m_q.r.b); %INDEXED; %AND8; return; + case 0x28: set_regop8(m_q.r.a); set_imm(); %BIT8; return; + case 0x29: set_regop8(m_q.r.b); set_imm(); %BIT8; return; + case 0x2A: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; + case 0x2B: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; + case 0x2C: set_regop8(m_q.r.a); set_imm(); %EOR8; return; + case 0x2D: set_regop8(m_q.r.b); set_imm(); %EOR8; return; + case 0x2E: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; + case 0x2F: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; + + case 0x30: set_regop8(m_q.r.a); set_imm(); %OR8; return; + case 0x31: set_regop8(m_q.r.b); set_imm(); %OR8; return; + case 0x32: set_regop8(m_q.r.a); %INDEXED; %OR8; return; + case 0x33: set_regop8(m_q.r.b); %INDEXED; %OR8; return; + case 0x34: set_regop8(m_q.r.a); set_imm(); %CMP8; return; + case 0x35: set_regop8(m_q.r.b); set_imm(); %CMP8; return; + case 0x36: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; + case 0x37: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; + case 0x38: set_imm(); %SETLINE; return; + case 0x39: %INDEXED; %SETLINE; return; + case 0x3A: set_regop8(m_q.r.a); %INDEXED; %ST8; return; + case 0x3B: set_regop8(m_q.r.b); %INDEXED; %ST8; return; + case 0x3C: set_imm(); %ANDCC; return; + case 0x3D: set_imm(); %ORCC; return; + case 0x3E: %EXG; return; + case 0x3F: %TFR; return; + + case 0x40: set_regop16(m_q.p.d); set_imm(); %LD16; return; + case 0x41: set_regop16(m_q.p.d); %INDEXED; %LD16; return; + case 0x42: set_regop16(m_x); set_imm(); %LD16; return; + case 0x43: set_regop16(m_x); %INDEXED; %LD16; return; + case 0x44: set_regop16(m_y); set_imm(); %LD16; return; + case 0x45: set_regop16(m_y); %INDEXED; %LD16; return; + case 0x46: set_regop16(m_u); set_imm(); %LD16; return; + case 0x47: set_regop16(m_u); %INDEXED; %LD16; return; + case 0x48: set_regop16(m_s); set_imm(); %LD16; return; + case 0x49: set_regop16(m_s); %INDEXED; %LD16; return; + case 0x4A: set_regop16(m_q.p.d); set_imm(); %CMP16; return; + case 0x4B: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; + case 0x4C: set_regop16(m_x); set_imm(); %CMP16; return; + case 0x4D: set_regop16(m_x); %INDEXED; %CMP16; return; + case 0x4E: set_regop16(m_y); set_imm(); %CMP16; return; + case 0x4F: set_regop16(m_y); %INDEXED; %CMP16; return; + + case 0x50: set_regop16(m_u); set_imm(); %CMP16; return; + case 0x51: set_regop16(m_u); %INDEXED; %CMP16; return; + case 0x52: set_regop16(m_s); set_imm(); %CMP16; return; + case 0x53: set_regop16(m_s); %INDEXED; %CMP16; return; + case 0x54: set_regop16(m_q.p.d); set_imm(); %ADD16; return; + case 0x55: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; + case 0x56: set_regop16(m_q.p.d); set_imm(); %SUB16; return; + case 0x57: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; + case 0x58: set_regop16(m_q.p.d); %INDEXED; %ST16; return; + case 0x59: set_regop16(m_x); %INDEXED; %ST16; return; + case 0x5A: set_regop16(m_y); %INDEXED; %ST16; return; + case 0x5B: set_regop16(m_u); %INDEXED; %ST16; return; + case 0x5C: set_regop16(m_s); %INDEXED; %ST16; return; + + case 0x60: set_cond(true); %BRANCH; return; + case 0x61: set_cond(cond_hi()); %BRANCH; return; + case 0x62: set_cond(cond_cc()); %BRANCH; return; + case 0x63: set_cond(cond_ne()); %BRANCH; return; + case 0x64: set_cond(cond_vc()); %BRANCH; return; + case 0x65: set_cond(cond_pl()); %BRANCH; return; + case 0x66: set_cond(cond_ge()); %BRANCH; return; + case 0x67: set_cond(cond_gt()); %BRANCH; return; + case 0x68: set_cond(true); %LBRANCH; return; + case 0x69: set_cond(cond_hi()); %LBRANCH; return; + case 0x6A: set_cond(cond_cc()); %LBRANCH; return; + case 0x6B: set_cond(cond_ne()); %LBRANCH; return; + case 0x6C: set_cond(cond_vc()); %LBRANCH; return; + case 0x6D: set_cond(cond_pl()); %LBRANCH; return; + case 0x6E: set_cond(cond_ge()); %LBRANCH; return; + case 0x6F: set_cond(cond_gt()); %LBRANCH; return; + + case 0x70: set_cond(false); %BRANCH; return; + case 0x71: set_cond(!cond_hi()); %BRANCH; return; + case 0x72: set_cond(!cond_cc()); %BRANCH; return; + case 0x73: set_cond(!cond_ne()); %BRANCH; return; + case 0x74: set_cond(!cond_vc()); %BRANCH; return; + case 0x75: set_cond(!cond_pl()); %BRANCH; return; + case 0x76: set_cond(!cond_ge()); %BRANCH; return; + case 0x77: set_cond(!cond_gt()); %BRANCH; return; + case 0x78: set_cond(false); %LBRANCH; return; + case 0x79: set_cond(!cond_hi()); %LBRANCH; return; + case 0x7A: set_cond(!cond_cc()); %LBRANCH; return; + case 0x7B: set_cond(!cond_ne()); %LBRANCH; return; + case 0x7C: set_cond(!cond_vc()); %LBRANCH; return; + case 0x7D: set_cond(!cond_pl()); %LBRANCH; return; + case 0x7E: set_cond(!cond_ge()); %LBRANCH; return; + case 0x7F: set_cond(!cond_gt()); %LBRANCH; return; + + case 0x80: set_a(); %CLR8; return; + case 0x81: set_b(); %CLR8; return; + case 0x82: %INDEXED; %CLR8; return; + case 0x83: set_a(); %COM8; return; + case 0x84: set_b(); %COM8; return; + case 0x85: %INDEXED; %COM8; return; + case 0x86: set_a(); %NEG8; return; + case 0x87: set_b(); %NEG8; return; + case 0x88: %INDEXED; %NEG8; return; + case 0x89: set_a(); %INC8; return; + case 0x8A: set_b(); %INC8; return; + case 0x8B: %INDEXED; %INC8; return; + case 0x8C: set_a(); %DEC8; return; + case 0x8D: set_b(); %DEC8; return; + case 0x8E: %INDEXED; %DEC8; return; + case 0x8F: %RTS; return; + + case 0x90: set_a(); %TST8; return; + case 0x91: set_b(); %TST8; return; + case 0x92: %INDEXED; %TST8; return; + case 0x93: set_a(); %LSR8; return; + case 0x94: set_b(); %LSR8; return; + case 0x95: %INDEXED; %LSR8; return; + case 0x96: set_a(); %ROR8; return; + case 0x97: set_b(); %ROR8; return; + case 0x98: %INDEXED; %ROR8; return; + case 0x99: set_a(); %ASR8; return; + case 0x9A: set_b(); %ASR8; return; + case 0x9B: %INDEXED; %ASR8; return; + case 0x9C: set_a(); %ASL8; return; + case 0x9D: set_b(); %ASL8; return; + case 0x9E: %INDEXED; %ASL8; return; + case 0x9F: %RTI; return; + + case 0xA0: set_a(); %ROL8; return; + case 0xA1: set_b(); %ROL8; return; + case 0xA2: %INDEXED; %ROL8; return; + case 0xA3: %INDEXED; %LSR16; return; + case 0xA4: %INDEXED; %ROR16; return; + case 0xA5: %INDEXED; %ASR16; return; + case 0xA6: %INDEXED; %ASL16; return; + case 0xA7: %INDEXED; %ROL16; return; + case 0xA8: %INDEXED; %JMP; return; + case 0xA9: %INDEXED; %JSR; return; + case 0xAA: %BSR; return; + case 0xAB: %LBSR; return; + case 0xAC: %DECBJNZ; return; + case 0xAD: %DECXJNZ; return; + case 0xAE: %NOP; return; + + case 0xB0: %ABX; return; + case 0xB1: %DAA; return; + case 0xB2: %SEX; return; + case 0xB3: %MUL; return; + case 0xB4: %LMUL; return; + case 0xB5: %DIVX; return; + case 0xB6: %BMOVE; return; + case 0xB7: %MOVE; return; + case 0xB8: %IMM_IM; set_d(); %LSRD; return; + case 0xB9: %INDEXED; %LSRD; return; + case 0xBA: %IMM_IM; set_d(); %RORD; return; + case 0xBB: %INDEXED; %RORD; return; + case 0xBC: %IMM_IM; set_d(); %ASRD; return; + case 0xBD: %INDEXED; %ASRD; return; + case 0xBE: %IMM_IM; set_d(); %ASLD; return; + case 0xBF: %INDEXED; %ASLD; return; + + case 0xC0: %IMM_IM; set_d(); %ROLD; return; + case 0xC1: %INDEXED; %ROLD; return; + case 0xC2: set_d(); %CLR16; return; + case 0xC3: %INDEXED; %CLR16; return; + case 0xC4: set_d(); %NEG16; return; + case 0xC5: %INDEXED; %NEG16; return; + case 0xC6: set_d(); %INC16; return; + case 0xC7: %INDEXED; %INC16; return; + case 0xC8: set_d(); %DEC16; return; + case 0xC9: %INDEXED; %DEC16; return; + case 0xCA: set_d(); %TST16; return; + case 0xCB: %INDEXED; %TST16; return; + case 0xCC: set_a(); %ABS8; return; + case 0xCD: set_b(); %ABS8; return; + case 0xCE: set_d(); %ABS16; return; + case 0xCF: %BSET; return; + + case 0xD0: %BSET2; return; + default: %ILLEGAL; return; + } + return; + +#include "base6x09.lst" + +PUSH_REGISTERS: + if (m_temp.w & 0x80) + { + @write_memory(--regop16().w, m_pc.b.l); + @write_memory(--regop16().w, m_pc.b.h); + nop(); + } + if (m_temp.w & 0x40) + { + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); + nop(); + } + if (m_temp.w & 0x20) + { + @write_memory(--regop16().w, m_y.b.l); + @write_memory(--regop16().w, m_y.b.h); + nop(); + } + if (m_temp.w & 0x10) + { + @write_memory(--regop16().w, m_x.b.l); + @write_memory(--regop16().w, m_x.b.h); + nop(); + } + if (m_temp.w & 0x08) + { + @write_memory(--regop16().w, m_dp); + nop(); + } + if (m_temp.w & 0x04) + { + @write_memory(--regop16().w, m_q.r.b); + nop(); + } + if (m_temp.w & 0x02) + { + @write_memory(--regop16().w, m_q.r.a); + nop(); + } + if (m_temp.w & 0x01) + { + @write_memory(--regop16().w, m_cc); + nop(); + } + return; + +PULL_REGISTERS: + if (m_temp.w & 0x01) + { + @m_cc = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x02) + { + @m_q.r.a = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x04) + { + @m_q.r.b = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x08) + { + @m_dp = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x10) + { + @m_x.b.h = read_memory(regop16().w++); + @m_x.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x20) + { + @m_y.b.h = read_memory(regop16().w++); + @m_y.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x40) + { + @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); + @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x80) + { + @m_pc.b.h = read_memory(regop16().w++); + @m_pc.b.l = read_memory(regop16().w++); + nop(); + } + @eat(1); + return; + +INDEXED: + @m_opcode = read_opcode_arg(); + switch(m_opcode & 0xF7) + { + case 0x07: + // extended addressing mode + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + eat(1); + break; + + case 0x20: case 0x30: case 0x50: case 0x60: case 0x70: + // auto increment + m_temp.w = ireg(); + ireg()++; + eat(2); + break; + + case 0x21: case 0x31: case 0x51: case 0x61: case 0x71: + // double auto increment + m_temp.w = ireg(); + ireg() += 2; + eat(3); + break; + + case 0x22: case 0x32: case 0x52: case 0x62: case 0x72: + // auto decrement + ireg()--; + m_temp.w = ireg(); + eat(2); + break; + + case 0x23: case 0x33: case 0x53: case 0x63: case 0x73: + // double auto decrement + ireg() -= 2; + m_temp.w = ireg(); + eat(3); + break; + + case 0x24: case 0x34: case 0x54: case 0x64: case 0x74: + // postbyte offset + m_ea.w = ireg(); // need to do this now because ireg() might be PC + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_ea.w + (int8_t) m_temp.b.l; + eat(2); + break; + + case 0x25: case 0x35: case 0x55: case 0x65: case 0x75: + // postword offset + m_ea.w = ireg(); // need to do this now because ireg() might be PC + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_ea.w + (int16_t) m_temp.w; + eat(2); + break; + + case 0x26: case 0x36: case 0x56: case 0x66: case 0x76: + m_temp.w = ireg(); + eat(1); + break; + + case 0xC4: + // direct addressing mode + m_temp.b.h = m_dp; + @m_temp.b.l = read_opcode_arg(); + eat(1); + break; + + case 0xA0: case 0xB0: case 0xD0: case 0xE0: case 0xF0: + // relative to register A + m_temp.w = ireg() + (int8_t) m_q.r.a; + eat(2); + break; + + case 0xA1: case 0xB1: case 0xD1: case 0xE1: case 0xF1: + // relative to register B + m_temp.w = ireg() + (int8_t) m_q.r.b; + eat(2); + break; + + case 0xA7: case 0xB7: case 0xD7: case 0xE7: case 0xF7: + // relative to register D + m_temp.w = ireg() + (int16_t) m_q.r.d; + eat(2); + break; + + default: + logerror("KONAMI: Unknown/Invalid postbyte at PC = %04x\n", m_pc.w - 1); + m_temp.w = 0; + break; + } + + if (m_opcode & 0x08) + { + // indirect mode + set_ea(m_temp.w); + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + eat(1); + } + + set_ea(m_temp.w); + return; + +EXG: + { + // konami's EXG instruction differs enough from 6809 to fork the code + uint8_t param = read_opcode_arg(); + uint16_t reg1 = read_exgtfr_register(param >> 0); + uint16_t reg2 = read_exgtfr_register(param >> 4); + write_exgtfr_register(param >> 0, reg2); + write_exgtfr_register(param >> 4, reg1); + } + eat(3); + return; + +TFR: + { + // konami's TFR instruction differs enough from 6809 to fork the code + uint8_t param = read_opcode_arg(); + uint16_t reg = read_exgtfr_register(param >> 0); + write_exgtfr_register(param >> 4, reg); + } + eat(2); + return; + +SETLINE: + @set_lines(read_operand()); + return; + +IMM_IM: + @m_temp_im = read_opcode_arg(); + return; + +MOVE: + @m_temp.b.l = read_memory(m_y.w++); + @write_memory(m_x.w++, m_temp.b.l); + m_u.w--; + return; + +BMOVE: + // BMOVE does not appear to be interruptable, at least judging from the old implementation + while(m_u.w != 0) + { + @m_temp.b.l = read_memory(m_y.w++); + @write_memory(m_x.w++, m_temp.b.l); + m_u.w--; + } + return; + +BSET: + // BSET does not appear to be interruptable, at least judging from the old implementation + while(m_u.w != 0) + { + @eat(1); + @write_memory(m_x.w++, m_q.r.a); + m_u.w--; + } + return; + +BSET2: + // BSET2 does not appear to be interruptable, at least judging from the old implementation + while(m_u.w != 0) + { + @eat(1); + @write_memory(m_x.w++, m_q.r.a); + @write_memory(m_x.w++, m_q.r.b); + m_u.w--; + } + return; + +DECXJNZ: + // not sure if this affects V? + m_x.w = set_flags(CC_NZV, m_x.w, 1, m_x.w - 1); + @eat(1); + set_cond(cond_ne()); + goto BRANCH; + +DECBJNZ: + // not sure if this affects V? + m_q.r.b = set_flags(CC_NZV, m_q.r.b, 1, m_q.r.b - 1); + @eat(1); + set_cond(cond_ne()); + goto BRANCH; + +LSRD: + // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A + m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; + + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + + while(m_bcount--) + { + @eat(1); + m_cc &= ~CC_C; + m_cc |= (m_temp.w & 1) ? CC_C : 0; + m_temp.w = set_flags(CC_NZ, m_temp.w >> 1); + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ASLD: + // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A + m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; + + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + + while(m_bcount--) + { + @eat(1); + m_temp.w = set_flags(CC_NZVC, m_temp.w, m_temp.w, m_temp.w << 1); + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ASRD: + // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A + m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; + + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + + while(m_bcount--) + { + @eat(1); + m_cc &= ~CC_C; + m_cc |= (m_temp.w & 1) ? CC_C : 0; + m_temp.w = set_flags(CC_NZ, ((int16_t) m_temp.w) >> 1); + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ROLD: + // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A + m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; + + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + + while(m_bcount--) + { + @eat(1); + m_temp.w = set_flags(CC_NZV, rotate_left(m_temp.w)); + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +RORD: + // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A + m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; + + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + + while(m_bcount--) + { + @eat(1); + m_temp.w = set_flags(CC_NZ, rotate_right(m_temp.w)); + } + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +ABS8: + @m_temp.b.l = read_operand(); + m_temp.b.l = set_flags(CC_NZVC, 0, m_temp.b.l, ((int8_t) m_temp.b.l) >= 0 ? m_temp.b.l : -m_temp.b.l); + write_operand(m_temp.b.l); + return; + +ABS16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + m_temp.w = set_flags(CC_NZVC, 0, m_temp.w, ((int16_t) m_temp.w) >= 0 ? m_temp.w : -m_temp.w); + @write_operand(0, m_temp.b.h); + write_operand(1, m_temp.b.l); + return; + +LMUL: + lmul(); + eat(21); + return; + +DIVX: + divx(); + eat(10); + return; + +ILLEGAL: + log_illegal(); + return; diff --git a/src/devices/cpu/m6809/konami.ops b/src/devices/cpu/m6809/konami.ops deleted file mode 100644 index 00e1d910a86..00000000000 --- a/src/devices/cpu/m6809/konami.ops +++ /dev/null @@ -1,628 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Nathan Woods -MAIN: - // check interrupt lines - switch(get_pending_interrupt()) - { - case VECTOR_NMI: goto NMI; - case VECTOR_FIRQ: goto FIRQ; - case VECTOR_IRQ: goto IRQ; - } - - // debugger hook - m_ppc = m_pc; - debugger_instruction_hook(m_pc.w); - - // opcode fetch - @m_opcode = read_opcode(); - - // dispatch opcode - switch(m_opcode) - { - case 0x08: set_regop16(m_x); %INDEXED; %LEA_xy; return; - case 0x09: set_regop16(m_y); %INDEXED; %LEA_xy; return; - case 0x0A: set_regop16(m_u); %INDEXED; %LEA_us; return; - case 0x0B: set_regop16(m_s); %INDEXED; %LEA_us; return; - case 0x0C: %PSHS; return; - case 0x0D: %PSHU; return; - case 0x0E: %PULS; return; - case 0x0F: %PULU; return; - - case 0x10: set_regop8(m_q.r.a); set_imm(); %LD8; return; - case 0x11: set_regop8(m_q.r.b); set_imm(); %LD8; return; - case 0x12: set_regop8(m_q.r.a); %INDEXED; %LD8; return; - case 0x13: set_regop8(m_q.r.b); %INDEXED; %LD8; return; - case 0x14: set_regop8(m_q.r.a); set_imm(); %ADD8; return; - case 0x15: set_regop8(m_q.r.b); set_imm(); %ADD8; return; - case 0x16: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; - case 0x17: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; - case 0x18: set_regop8(m_q.r.a); set_imm(); %ADC8; return; - case 0x19: set_regop8(m_q.r.b); set_imm(); %ADC8; return; - case 0x1A: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; - case 0x1B: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; - case 0x1C: set_regop8(m_q.r.a); set_imm(); %SUB8; return; - case 0x1D: set_regop8(m_q.r.b); set_imm(); %SUB8; return; - case 0x1E: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; - case 0x1F: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; - - case 0x20: set_regop8(m_q.r.a); set_imm(); %SBC8; return; - case 0x21: set_regop8(m_q.r.b); set_imm(); %SBC8; return; - case 0x22: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; - case 0x23: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; - case 0x24: set_regop8(m_q.r.a); set_imm(); %AND8; return; - case 0x25: set_regop8(m_q.r.b); set_imm(); %AND8; return; - case 0x26: set_regop8(m_q.r.a); %INDEXED; %AND8; return; - case 0x27: set_regop8(m_q.r.b); %INDEXED; %AND8; return; - case 0x28: set_regop8(m_q.r.a); set_imm(); %BIT8; return; - case 0x29: set_regop8(m_q.r.b); set_imm(); %BIT8; return; - case 0x2A: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; - case 0x2B: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; - case 0x2C: set_regop8(m_q.r.a); set_imm(); %EOR8; return; - case 0x2D: set_regop8(m_q.r.b); set_imm(); %EOR8; return; - case 0x2E: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; - case 0x2F: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; - - case 0x30: set_regop8(m_q.r.a); set_imm(); %OR8; return; - case 0x31: set_regop8(m_q.r.b); set_imm(); %OR8; return; - case 0x32: set_regop8(m_q.r.a); %INDEXED; %OR8; return; - case 0x33: set_regop8(m_q.r.b); %INDEXED; %OR8; return; - case 0x34: set_regop8(m_q.r.a); set_imm(); %CMP8; return; - case 0x35: set_regop8(m_q.r.b); set_imm(); %CMP8; return; - case 0x36: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; - case 0x37: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; - case 0x38: set_imm(); %SETLINE; return; - case 0x39: %INDEXED; %SETLINE; return; - case 0x3A: set_regop8(m_q.r.a); %INDEXED; %ST8; return; - case 0x3B: set_regop8(m_q.r.b); %INDEXED; %ST8; return; - case 0x3C: set_imm(); %ANDCC; return; - case 0x3D: set_imm(); %ORCC; return; - case 0x3E: %EXG; return; - case 0x3F: %TFR; return; - - case 0x40: set_regop16(m_q.p.d); set_imm(); %LD16; return; - case 0x41: set_regop16(m_q.p.d); %INDEXED; %LD16; return; - case 0x42: set_regop16(m_x); set_imm(); %LD16; return; - case 0x43: set_regop16(m_x); %INDEXED; %LD16; return; - case 0x44: set_regop16(m_y); set_imm(); %LD16; return; - case 0x45: set_regop16(m_y); %INDEXED; %LD16; return; - case 0x46: set_regop16(m_u); set_imm(); %LD16; return; - case 0x47: set_regop16(m_u); %INDEXED; %LD16; return; - case 0x48: set_regop16(m_s); set_imm(); %LD16; return; - case 0x49: set_regop16(m_s); %INDEXED; %LD16; return; - case 0x4A: set_regop16(m_q.p.d); set_imm(); %CMP16; return; - case 0x4B: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; - case 0x4C: set_regop16(m_x); set_imm(); %CMP16; return; - case 0x4D: set_regop16(m_x); %INDEXED; %CMP16; return; - case 0x4E: set_regop16(m_y); set_imm(); %CMP16; return; - case 0x4F: set_regop16(m_y); %INDEXED; %CMP16; return; - - case 0x50: set_regop16(m_u); set_imm(); %CMP16; return; - case 0x51: set_regop16(m_u); %INDEXED; %CMP16; return; - case 0x52: set_regop16(m_s); set_imm(); %CMP16; return; - case 0x53: set_regop16(m_s); %INDEXED; %CMP16; return; - case 0x54: set_regop16(m_q.p.d); set_imm(); %ADD16; return; - case 0x55: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; - case 0x56: set_regop16(m_q.p.d); set_imm(); %SUB16; return; - case 0x57: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; - case 0x58: set_regop16(m_q.p.d); %INDEXED; %ST16; return; - case 0x59: set_regop16(m_x); %INDEXED; %ST16; return; - case 0x5A: set_regop16(m_y); %INDEXED; %ST16; return; - case 0x5B: set_regop16(m_u); %INDEXED; %ST16; return; - case 0x5C: set_regop16(m_s); %INDEXED; %ST16; return; - - case 0x60: set_cond(true); %BRANCH; return; - case 0x61: set_cond(cond_hi()); %BRANCH; return; - case 0x62: set_cond(cond_cc()); %BRANCH; return; - case 0x63: set_cond(cond_ne()); %BRANCH; return; - case 0x64: set_cond(cond_vc()); %BRANCH; return; - case 0x65: set_cond(cond_pl()); %BRANCH; return; - case 0x66: set_cond(cond_ge()); %BRANCH; return; - case 0x67: set_cond(cond_gt()); %BRANCH; return; - case 0x68: set_cond(true); %LBRANCH; return; - case 0x69: set_cond(cond_hi()); %LBRANCH; return; - case 0x6A: set_cond(cond_cc()); %LBRANCH; return; - case 0x6B: set_cond(cond_ne()); %LBRANCH; return; - case 0x6C: set_cond(cond_vc()); %LBRANCH; return; - case 0x6D: set_cond(cond_pl()); %LBRANCH; return; - case 0x6E: set_cond(cond_ge()); %LBRANCH; return; - case 0x6F: set_cond(cond_gt()); %LBRANCH; return; - - case 0x70: set_cond(false); %BRANCH; return; - case 0x71: set_cond(!cond_hi()); %BRANCH; return; - case 0x72: set_cond(!cond_cc()); %BRANCH; return; - case 0x73: set_cond(!cond_ne()); %BRANCH; return; - case 0x74: set_cond(!cond_vc()); %BRANCH; return; - case 0x75: set_cond(!cond_pl()); %BRANCH; return; - case 0x76: set_cond(!cond_ge()); %BRANCH; return; - case 0x77: set_cond(!cond_gt()); %BRANCH; return; - case 0x78: set_cond(false); %LBRANCH; return; - case 0x79: set_cond(!cond_hi()); %LBRANCH; return; - case 0x7A: set_cond(!cond_cc()); %LBRANCH; return; - case 0x7B: set_cond(!cond_ne()); %LBRANCH; return; - case 0x7C: set_cond(!cond_vc()); %LBRANCH; return; - case 0x7D: set_cond(!cond_pl()); %LBRANCH; return; - case 0x7E: set_cond(!cond_ge()); %LBRANCH; return; - case 0x7F: set_cond(!cond_gt()); %LBRANCH; return; - - case 0x80: set_a(); %CLR8; return; - case 0x81: set_b(); %CLR8; return; - case 0x82: %INDEXED; %CLR8; return; - case 0x83: set_a(); %COM8; return; - case 0x84: set_b(); %COM8; return; - case 0x85: %INDEXED; %COM8; return; - case 0x86: set_a(); %NEG8; return; - case 0x87: set_b(); %NEG8; return; - case 0x88: %INDEXED; %NEG8; return; - case 0x89: set_a(); %INC8; return; - case 0x8A: set_b(); %INC8; return; - case 0x8B: %INDEXED; %INC8; return; - case 0x8C: set_a(); %DEC8; return; - case 0x8D: set_b(); %DEC8; return; - case 0x8E: %INDEXED; %DEC8; return; - case 0x8F: %RTS; return; - - case 0x90: set_a(); %TST8; return; - case 0x91: set_b(); %TST8; return; - case 0x92: %INDEXED; %TST8; return; - case 0x93: set_a(); %LSR8; return; - case 0x94: set_b(); %LSR8; return; - case 0x95: %INDEXED; %LSR8; return; - case 0x96: set_a(); %ROR8; return; - case 0x97: set_b(); %ROR8; return; - case 0x98: %INDEXED; %ROR8; return; - case 0x99: set_a(); %ASR8; return; - case 0x9A: set_b(); %ASR8; return; - case 0x9B: %INDEXED; %ASR8; return; - case 0x9C: set_a(); %ASL8; return; - case 0x9D: set_b(); %ASL8; return; - case 0x9E: %INDEXED; %ASL8; return; - case 0x9F: %RTI; return; - - case 0xA0: set_a(); %ROL8; return; - case 0xA1: set_b(); %ROL8; return; - case 0xA2: %INDEXED; %ROL8; return; - case 0xA3: %INDEXED; %LSR16; return; - case 0xA4: %INDEXED; %ROR16; return; - case 0xA5: %INDEXED; %ASR16; return; - case 0xA6: %INDEXED; %ASL16; return; - case 0xA7: %INDEXED; %ROL16; return; - case 0xA8: %INDEXED; %JMP; return; - case 0xA9: %INDEXED; %JSR; return; - case 0xAA: %BSR; return; - case 0xAB: %LBSR; return; - case 0xAC: %DECBJNZ; return; - case 0xAD: %DECXJNZ; return; - case 0xAE: %NOP; return; - - case 0xB0: %ABX; return; - case 0xB1: %DAA; return; - case 0xB2: %SEX; return; - case 0xB3: %MUL; return; - case 0xB4: %LMUL; return; - case 0xB5: %DIVX; return; - case 0xB6: %BMOVE; return; - case 0xB7: %MOVE; return; - case 0xB8: %IMM_IM; set_d(); %LSRD; return; - case 0xB9: %INDEXED; %LSRD; return; - case 0xBA: %IMM_IM; set_d(); %RORD; return; - case 0xBB: %INDEXED; %RORD; return; - case 0xBC: %IMM_IM; set_d(); %ASRD; return; - case 0xBD: %INDEXED; %ASRD; return; - case 0xBE: %IMM_IM; set_d(); %ASLD; return; - case 0xBF: %INDEXED; %ASLD; return; - - case 0xC0: %IMM_IM; set_d(); %ROLD; return; - case 0xC1: %INDEXED; %ROLD; return; - case 0xC2: set_d(); %CLR16; return; - case 0xC3: %INDEXED; %CLR16; return; - case 0xC4: set_d(); %NEG16; return; - case 0xC5: %INDEXED; %NEG16; return; - case 0xC6: set_d(); %INC16; return; - case 0xC7: %INDEXED; %INC16; return; - case 0xC8: set_d(); %DEC16; return; - case 0xC9: %INDEXED; %DEC16; return; - case 0xCA: set_d(); %TST16; return; - case 0xCB: %INDEXED; %TST16; return; - case 0xCC: set_a(); %ABS8; return; - case 0xCD: set_b(); %ABS8; return; - case 0xCE: set_d(); %ABS16; return; - case 0xCF: %BSET; return; - - case 0xD0: %BSET2; return; - default: %ILLEGAL; return; - } - return; - -#include "base6x09.ops" - -PUSH_REGISTERS: - if (m_temp.w & 0x80) - { - @write_memory(--regop16().w, m_pc.b.l); - @write_memory(--regop16().w, m_pc.b.h); - nop(); - } - if (m_temp.w & 0x40) - { - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); - nop(); - } - if (m_temp.w & 0x20) - { - @write_memory(--regop16().w, m_y.b.l); - @write_memory(--regop16().w, m_y.b.h); - nop(); - } - if (m_temp.w & 0x10) - { - @write_memory(--regop16().w, m_x.b.l); - @write_memory(--regop16().w, m_x.b.h); - nop(); - } - if (m_temp.w & 0x08) - { - @write_memory(--regop16().w, m_dp); - nop(); - } - if (m_temp.w & 0x04) - { - @write_memory(--regop16().w, m_q.r.b); - nop(); - } - if (m_temp.w & 0x02) - { - @write_memory(--regop16().w, m_q.r.a); - nop(); - } - if (m_temp.w & 0x01) - { - @write_memory(--regop16().w, m_cc); - nop(); - } - return; - -PULL_REGISTERS: - if (m_temp.w & 0x01) - { - @m_cc = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x02) - { - @m_q.r.a = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x04) - { - @m_q.r.b = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x08) - { - @m_dp = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x10) - { - @m_x.b.h = read_memory(regop16().w++); - @m_x.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x20) - { - @m_y.b.h = read_memory(regop16().w++); - @m_y.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x40) - { - @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); - @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x80) - { - @m_pc.b.h = read_memory(regop16().w++); - @m_pc.b.l = read_memory(regop16().w++); - nop(); - } - @eat(1); - return; - -INDEXED: - @m_opcode = read_opcode_arg(); - switch(m_opcode & 0xF7) - { - case 0x07: - // extended addressing mode - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - eat(1); - break; - - case 0x20: case 0x30: case 0x50: case 0x60: case 0x70: - // auto increment - m_temp.w = ireg(); - ireg()++; - eat(2); - break; - - case 0x21: case 0x31: case 0x51: case 0x61: case 0x71: - // double auto increment - m_temp.w = ireg(); - ireg() += 2; - eat(3); - break; - - case 0x22: case 0x32: case 0x52: case 0x62: case 0x72: - // auto decrement - ireg()--; - m_temp.w = ireg(); - eat(2); - break; - - case 0x23: case 0x33: case 0x53: case 0x63: case 0x73: - // double auto decrement - ireg() -= 2; - m_temp.w = ireg(); - eat(3); - break; - - case 0x24: case 0x34: case 0x54: case 0x64: case 0x74: - // postbyte offset - m_ea.w = ireg(); // need to do this now because ireg() might be PC - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_ea.w + (int8_t) m_temp.b.l; - eat(2); - break; - - case 0x25: case 0x35: case 0x55: case 0x65: case 0x75: - // postword offset - m_ea.w = ireg(); // need to do this now because ireg() might be PC - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_ea.w + (int16_t) m_temp.w; - eat(2); - break; - - case 0x26: case 0x36: case 0x56: case 0x66: case 0x76: - m_temp.w = ireg(); - eat(1); - break; - - case 0xC4: - // direct addressing mode - m_temp.b.h = m_dp; - @m_temp.b.l = read_opcode_arg(); - eat(1); - break; - - case 0xA0: case 0xB0: case 0xD0: case 0xE0: case 0xF0: - // relative to register A - m_temp.w = ireg() + (int8_t) m_q.r.a; - eat(2); - break; - - case 0xA1: case 0xB1: case 0xD1: case 0xE1: case 0xF1: - // relative to register B - m_temp.w = ireg() + (int8_t) m_q.r.b; - eat(2); - break; - - case 0xA7: case 0xB7: case 0xD7: case 0xE7: case 0xF7: - // relative to register D - m_temp.w = ireg() + (int16_t) m_q.r.d; - eat(2); - break; - - default: - logerror("KONAMI: Unknown/Invalid postbyte at PC = %04x\n", m_pc.w - 1); - m_temp.w = 0; - break; - } - - if (m_opcode & 0x08) - { - // indirect mode - set_ea(m_temp.w); - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - eat(1); - } - - set_ea(m_temp.w); - return; - -EXG: - { - // konami's EXG instruction differs enough from 6809 to fork the code - uint8_t param = read_opcode_arg(); - uint16_t reg1 = read_exgtfr_register(param >> 0); - uint16_t reg2 = read_exgtfr_register(param >> 4); - write_exgtfr_register(param >> 0, reg2); - write_exgtfr_register(param >> 4, reg1); - } - eat(3); - return; - -TFR: - { - // konami's TFR instruction differs enough from 6809 to fork the code - uint8_t param = read_opcode_arg(); - uint16_t reg = read_exgtfr_register(param >> 0); - write_exgtfr_register(param >> 4, reg); - } - eat(2); - return; - -SETLINE: - @set_lines(read_operand()); - return; - -IMM_IM: - @m_temp_im = read_opcode_arg(); - return; - -MOVE: - @m_temp.b.l = read_memory(m_y.w++); - @write_memory(m_x.w++, m_temp.b.l); - m_u.w--; - return; - -BMOVE: - // BMOVE does not appear to be interruptable, at least judging from the old implementation - while(m_u.w != 0) - { - @m_temp.b.l = read_memory(m_y.w++); - @write_memory(m_x.w++, m_temp.b.l); - m_u.w--; - } - return; - -BSET: - // BSET does not appear to be interruptable, at least judging from the old implementation - while(m_u.w != 0) - { - @eat(1); - @write_memory(m_x.w++, m_q.r.a); - m_u.w--; - } - return; - -BSET2: - // BSET2 does not appear to be interruptable, at least judging from the old implementation - while(m_u.w != 0) - { - @eat(1); - @write_memory(m_x.w++, m_q.r.a); - @write_memory(m_x.w++, m_q.r.b); - m_u.w--; - } - return; - -DECXJNZ: - // not sure if this affects V? - m_x.w = set_flags(CC_NZV, m_x.w, 1, m_x.w - 1); - @eat(1); - set_cond(cond_ne()); - goto BRANCH; - -DECBJNZ: - // not sure if this affects V? - m_q.r.b = set_flags(CC_NZV, m_q.r.b, 1, m_q.r.b - 1); - @eat(1); - set_cond(cond_ne()); - goto BRANCH; - -LSRD: - // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A - m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; - - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - - while(m_bcount--) - { - @eat(1); - m_cc &= ~CC_C; - m_cc |= (m_temp.w & 1) ? CC_C : 0; - m_temp.w = set_flags(CC_NZ, m_temp.w >> 1); - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ASLD: - // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A - m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; - - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - - while(m_bcount--) - { - @eat(1); - m_temp.w = set_flags(CC_NZVC, m_temp.w, m_temp.w, m_temp.w << 1); - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ASRD: - // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A - m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; - - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - - while(m_bcount--) - { - @eat(1); - m_cc &= ~CC_C; - m_cc |= (m_temp.w & 1) ? CC_C : 0; - m_temp.w = set_flags(CC_NZ, ((int16_t) m_temp.w) >> 1); - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ROLD: - // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A - m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; - - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - - while(m_bcount--) - { - @eat(1); - m_temp.w = set_flags(CC_NZV, rotate_left(m_temp.w)); - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -RORD: - // register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A - m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a; - - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - - while(m_bcount--) - { - @eat(1); - m_temp.w = set_flags(CC_NZ, rotate_right(m_temp.w)); - } - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -ABS8: - @m_temp.b.l = read_operand(); - m_temp.b.l = set_flags(CC_NZVC, 0, m_temp.b.l, ((int8_t) m_temp.b.l) >= 0 ? m_temp.b.l : -m_temp.b.l); - write_operand(m_temp.b.l); - return; - -ABS16: - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - m_temp.w = set_flags(CC_NZVC, 0, m_temp.w, ((int16_t) m_temp.w) >= 0 ? m_temp.w : -m_temp.w); - @write_operand(0, m_temp.b.h); - write_operand(1, m_temp.b.l); - return; - -LMUL: - lmul(); - eat(21); - return; - -DIVX: - divx(); - eat(10); - return; - -ILLEGAL: - log_illegal(); - return; diff --git a/src/devices/cpu/m6809/m6809.lst b/src/devices/cpu/m6809/m6809.lst new file mode 100644 index 00000000000..18527afac31 --- /dev/null +++ b/src/devices/cpu/m6809/m6809.lst @@ -0,0 +1,605 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods +MAIN: + // check interrupt lines + switch(get_pending_interrupt()) + { + case VECTOR_NMI: goto NMI; + case VECTOR_FIRQ: goto FIRQ; + case VECTOR_IRQ: goto IRQ; + } + + // debugger hook + m_ppc = m_pc; + debugger_instruction_hook(m_pc.w); + + // opcode fetch + m_lic_func(ASSERT_LINE); + @m_opcode = read_opcode(); + m_lic_func(CLEAR_LINE); + + // dispatch opcode + switch(m_opcode) + { + case 0x00: case 0x01: %DIRECT; %NEG8; return; + case 0x03: case 0x02: %DIRECT; %COM8; return; + case 0x04: case 0x05: %DIRECT; %LSR8; return; + case 0x06: %DIRECT; %ROR8; return; + case 0x07: %DIRECT; %ASR8; return; + case 0x08: %DIRECT; %ASL8; return; + case 0x09: %DIRECT; %ROL8; return; + case 0x0A: case 0x0B: %DIRECT; %DEC8; return; + case 0x0C: %DIRECT; %INC8; return; + case 0x0D: %DIRECT; %TST8; return; + case 0x0E: %DIRECT; %JMP; return; + case 0x0F: %DIRECT; %CLR8; return; + + case 0x10: %DISPATCH10; return; + case 0x11: %DISPATCH11; return; + case 0x12: %NOP; return; + case 0x13: %SYNC; return; + case 0x16: set_cond(true); %LBRANCH; return; + case 0x17: %LBSR; return; + case 0x19: %DAA; return; + case 0x1A: set_imm(); %ORCC; return; + case 0x1C: set_imm(); %ANDCC; return; + case 0x1D: %SEX; return; + case 0x1E: %EXG; return; + case 0x1F: %TFR; return; + + case 0x20: set_cond(true); %BRANCH; return; + case 0x21: set_cond(false); %BRANCH; return; + case 0x22: set_cond(cond_hi()); %BRANCH; return; + case 0x23: set_cond(!cond_hi()); %BRANCH; return; + case 0x24: set_cond(cond_cc()); %BRANCH; return; + case 0x25: set_cond(!cond_cc()); %BRANCH; return; + case 0x26: set_cond(cond_ne()); %BRANCH; return; + case 0x27: set_cond(!cond_ne()); %BRANCH; return; + case 0x28: set_cond(cond_vc()); %BRANCH; return; + case 0x29: set_cond(!cond_vc()); %BRANCH; return; + case 0x2A: set_cond(cond_pl()); %BRANCH; return; + case 0x2B: set_cond(!cond_pl()); %BRANCH; return; + case 0x2C: set_cond(cond_ge()); %BRANCH; return; + case 0x2D: set_cond(!cond_ge()); %BRANCH; return; + case 0x2E: set_cond(cond_gt()); %BRANCH; return; + case 0x2F: set_cond(!cond_gt()); %BRANCH; return; + + case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return; + case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return; + case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return; + case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return; + case 0x34: %PSHS; return; + case 0x35: %PULS; return; + case 0x36: %PSHU; return; + case 0x37: %PULU; return; + case 0x39: %RTS; return; + case 0x3A: %ABX; return; + case 0x3B: %RTI; return; + case 0x3C: %CWAI; return; + case 0x3D: %MUL; return; + case 0x3F: %SWI; return; + + case 0x40: case 0x41: set_a(); %NEG8; return; + case 0x43: case 0x42: set_a(); %COM8; return; + case 0x44: case 0x45: set_a(); %LSR8; return; + case 0x46: set_a(); %ROR8; return; + case 0x47: set_a(); %ASR8; return; + case 0x48: set_a(); %ASL8; return; + case 0x49: set_a(); %ROL8; return; + case 0x4A: case 0x4B: set_a(); %DEC8; return; + case 0x4C: set_a(); %INC8; return; + case 0x4D: set_a(); %TST8; return; + case 0x4E: set_a(); %JMP; return; + case 0x4F: set_a(); %CLR8; return; + + case 0x50: case 0x51: set_b(); %NEG8; return; + case 0x53: case 0x52: set_b(); %COM8; return; + case 0x54: case 0x55: set_b(); %LSR8; return; + case 0x56: set_b(); %ROR8; return; + case 0x57: set_b(); %ASR8; return; + case 0x58: set_b(); %ASL8; return; + case 0x59: set_b(); %ROL8; return; + case 0x5A: case 0x5B: set_b(); %DEC8; return; + case 0x5C: set_b(); %INC8; return; + case 0x5D: set_b(); %TST8; return; + case 0x5E: set_b(); %JMP; return; + case 0x5F: set_b(); %CLR8; return; + + case 0x60: case 0x61: %INDEXED; %NEG8; return; + case 0x63: case 0x62: %INDEXED; %COM8; return; + case 0x64: case 0x65: %INDEXED; %LSR8; return; + case 0x66: %INDEXED; %ROR8; return; + case 0x67: %INDEXED; %ASR8; return; + case 0x68: %INDEXED; %ASL8; return; + case 0x69: %INDEXED; %ROL8; return; + case 0x6A: case 0x6B: %INDEXED; %DEC8; return; + case 0x6C: %INDEXED; %INC8; return; + case 0x6D: %INDEXED; %TST8; return; + case 0x6E: %INDEXED; %JMP; return; + case 0x6F: %INDEXED; %CLR8; return; + + case 0x70: case 0x71: %EXTENDED; %NEG8; return; + case 0x73: case 0x72: %EXTENDED; %COM8; return; + case 0x74: case 0x75: %EXTENDED; %LSR8; return; + case 0x76: %EXTENDED; %ROR8; return; + case 0x77: %EXTENDED; %ASR8; return; + case 0x78: %EXTENDED; %ASL8; return; + case 0x79: %EXTENDED; %ROL8; return; + case 0x7A: case 0x7B: %EXTENDED; %DEC8; return; + case 0x7C: %EXTENDED; %INC8; return; + case 0x7D: %EXTENDED; %TST8; return; + case 0x7E: %EXTENDED; %JMP; return; + case 0x7F: %EXTENDED; %CLR8; return; + + case 0x80: set_regop8(m_q.r.a); set_imm(); %SUB8; return; + case 0x81: set_regop8(m_q.r.a); set_imm(); %CMP8; return; + case 0x82: set_regop8(m_q.r.a); set_imm(); %SBC8; return; + case 0x83: set_regop16(m_q.p.d); set_imm(); %SUB16; return; + case 0x84: set_regop8(m_q.r.a); set_imm(); %AND8; return; + case 0x85: set_regop8(m_q.r.a); set_imm(); %BIT8; return; + case 0x86: set_regop8(m_q.r.a); set_imm(); %LD8; return; + case 0x87: set_regop8(m_q.r.a); set_imm(); %ST8; return; + case 0x88: set_regop8(m_q.r.a); set_imm(); %EOR8; return; + case 0x89: set_regop8(m_q.r.a); set_imm(); %ADC8; return; + case 0x8A: set_regop8(m_q.r.a); set_imm(); %OR8; return; + case 0x8B: set_regop8(m_q.r.a); set_imm(); %ADD8; return; + case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return; + case 0x8D: %BSR; return; + case 0x8E: set_regop16(m_x); set_imm(); %LD16; return; + case 0x8F: set_regop16(m_x); set_imm(); %ST16; return; + + case 0x90: set_regop8(m_q.r.a); %DIRECT; %SUB8; return; + case 0x91: set_regop8(m_q.r.a); %DIRECT; %CMP8; return; + case 0x92: set_regop8(m_q.r.a); %DIRECT; %SBC8; return; + case 0x93: set_regop16(m_q.p.d); %DIRECT; %SUB16; return; + case 0x94: set_regop8(m_q.r.a); %DIRECT; %AND8; return; + case 0x95: set_regop8(m_q.r.a); %DIRECT; %BIT8; return; + case 0x96: set_regop8(m_q.r.a); %DIRECT; %LD8; return; + case 0x97: set_regop8(m_q.r.a); %DIRECT; %ST8; return; + case 0x98: set_regop8(m_q.r.a); %DIRECT; %EOR8; return; + case 0x99: set_regop8(m_q.r.a); %DIRECT; %ADC8; return; + case 0x9A: set_regop8(m_q.r.a); %DIRECT; %OR8; return; + case 0x9B: set_regop8(m_q.r.a); %DIRECT; %ADD8; return; + case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return; + case 0x9D: %DIRECT; %JSR; return; + case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return; + case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return; + + case 0xA0: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; + case 0xA1: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; + case 0xA2: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; + case 0xA3: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; + case 0xA4: set_regop8(m_q.r.a); %INDEXED; %AND8; return; + case 0xA5: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; + case 0xA6: set_regop8(m_q.r.a); %INDEXED; %LD8; return; + case 0xA7: set_regop8(m_q.r.a); %INDEXED; %ST8; return; + case 0xA8: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; + case 0xA9: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; + case 0xAA: set_regop8(m_q.r.a); %INDEXED; %OR8; return; + case 0xAB: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; + case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return; + case 0xAD: %INDEXED; %JSR; return; + case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return; + case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return; + + case 0xB0: set_regop8(m_q.r.a); %EXTENDED; %SUB8; return; + case 0xB1: set_regop8(m_q.r.a); %EXTENDED; %CMP8; return; + case 0xB2: set_regop8(m_q.r.a); %EXTENDED; %SBC8; return; + case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %SUB16; return; + case 0xB4: set_regop8(m_q.r.a); %EXTENDED; %AND8; return; + case 0xB5: set_regop8(m_q.r.a); %EXTENDED; %BIT8; return; + case 0xB6: set_regop8(m_q.r.a); %EXTENDED; %LD8; return; + case 0xB7: set_regop8(m_q.r.a); %EXTENDED; %ST8; return; + case 0xB8: set_regop8(m_q.r.a); %EXTENDED; %EOR8; return; + case 0xB9: set_regop8(m_q.r.a); %EXTENDED; %ADC8; return; + case 0xBA: set_regop8(m_q.r.a); %EXTENDED; %OR8; return; + case 0xBB: set_regop8(m_q.r.a); %EXTENDED; %ADD8; return; + case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return; + case 0xBD: %EXTENDED; %JSR; return; + case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return; + case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return; + + case 0xC0: set_regop8(m_q.r.b); set_imm(); %SUB8; return; + case 0xC1: set_regop8(m_q.r.b); set_imm(); %CMP8; return; + case 0xC2: set_regop8(m_q.r.b); set_imm(); %SBC8; return; + case 0xC3: set_regop16(m_q.p.d); set_imm(); %ADD16; return; + case 0xC4: set_regop8(m_q.r.b); set_imm(); %AND8; return; + case 0xC5: set_regop8(m_q.r.b); set_imm(); %BIT8; return; + case 0xC6: set_regop8(m_q.r.b); set_imm(); %LD8; return; + case 0xC7: set_regop8(m_q.r.b); set_imm(); %ST8; return; + case 0xC8: set_regop8(m_q.r.b); set_imm(); %EOR8; return; + case 0xC9: set_regop8(m_q.r.b); set_imm(); %ADC8; return; + case 0xCA: set_regop8(m_q.r.b); set_imm(); %OR8; return; + case 0xCB: set_regop8(m_q.r.b); set_imm(); %ADD8; return; + case 0xCC: set_regop16(m_q.p.d); set_imm(); %LD16; return; + case 0xCD: set_regop16(m_q.p.d); set_imm(); %ST16; return; + case 0xCE: set_regop16(m_u); set_imm(); %LD16; return; + case 0xCF: set_regop16(m_u); set_imm(); %ST16; return; + + case 0xD0: set_regop8(m_q.r.b); %DIRECT; %SUB8; return; + case 0xD1: set_regop8(m_q.r.b); %DIRECT; %CMP8; return; + case 0xD2: set_regop8(m_q.r.b); %DIRECT; %SBC8; return; + case 0xD3: set_regop16(m_q.p.d); %DIRECT; %ADD16; return; + case 0xD4: set_regop8(m_q.r.b); %DIRECT; %AND8; return; + case 0xD5: set_regop8(m_q.r.b); %DIRECT; %BIT8; return; + case 0xD6: set_regop8(m_q.r.b); %DIRECT; %LD8; return; + case 0xD7: set_regop8(m_q.r.b); %DIRECT; %ST8; return; + case 0xD8: set_regop8(m_q.r.b); %DIRECT; %EOR8; return; + case 0xD9: set_regop8(m_q.r.b); %DIRECT; %ADC8; return; + case 0xDA: set_regop8(m_q.r.b); %DIRECT; %OR8; return; + case 0xDB: set_regop8(m_q.r.b); %DIRECT; %ADD8; return; + case 0xDC: set_regop16(m_q.p.d); %DIRECT; %LD16; return; + case 0xDD: set_regop16(m_q.p.d); %DIRECT; %ST16; return; + case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return; + case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return; + + case 0xE0: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; + case 0xE1: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; + case 0xE2: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; + case 0xE3: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; + case 0xE4: set_regop8(m_q.r.b); %INDEXED; %AND8; return; + case 0xE5: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; + case 0xE6: set_regop8(m_q.r.b); %INDEXED; %LD8; return; + case 0xE7: set_regop8(m_q.r.b); %INDEXED; %ST8; return; + case 0xE8: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; + case 0xE9: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; + case 0xEA: set_regop8(m_q.r.b); %INDEXED; %OR8; return; + case 0xEB: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; + case 0xEC: set_regop16(m_q.p.d); %INDEXED; %LD16; return; + case 0xED: set_regop16(m_q.p.d); %INDEXED; %ST16; return; + case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return; + case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return; + + case 0xF0: set_regop8(m_q.r.b); %EXTENDED; %SUB8; return; + case 0xF1: set_regop8(m_q.r.b); %EXTENDED; %CMP8; return; + case 0xF2: set_regop8(m_q.r.b); %EXTENDED; %SBC8; return; + case 0xF3: set_regop16(m_q.p.d); %EXTENDED; %ADD16; return; + case 0xF4: set_regop8(m_q.r.b); %EXTENDED; %AND8; return; + case 0xF5: set_regop8(m_q.r.b); %EXTENDED; %BIT8; return; + case 0xF6: set_regop8(m_q.r.b); %EXTENDED; %LD8; return; + case 0xF7: set_regop8(m_q.r.b); %EXTENDED; %ST8; return; + case 0xF8: set_regop8(m_q.r.b); %EXTENDED; %EOR8; return; + case 0xF9: set_regop8(m_q.r.b); %EXTENDED; %ADC8; return; + case 0xFA: set_regop8(m_q.r.b); %EXTENDED; %OR8; return; + case 0xFB: set_regop8(m_q.r.b); %EXTENDED; %ADD8; return; + case 0xFC: set_regop16(m_q.p.d); %EXTENDED; %LD16; return; + case 0xFD: set_regop16(m_q.p.d); %EXTENDED; %ST16; return; + case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return; + case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return; + default: %ILLEGAL; return; + } + return; + +DISPATCH10: + @m_opcode = read_opcode(); + switch(m_opcode) + { + case 0x20: set_cond(true); %LBRANCH; return; + case 0x21: set_cond(false); %LBRANCH; return; + case 0x22: set_cond(cond_hi()); %LBRANCH; return; + case 0x23: set_cond(!cond_hi()); %LBRANCH; return; + case 0x24: set_cond(cond_cc()); %LBRANCH; return; + case 0x25: set_cond(!cond_cc()); %LBRANCH; return; + case 0x26: set_cond(cond_ne()); %LBRANCH; return; + case 0x27: set_cond(!cond_ne()); %LBRANCH; return; + case 0x28: set_cond(cond_vc()); %LBRANCH; return; + case 0x29: set_cond(!cond_vc()); %LBRANCH; return; + case 0x2A: set_cond(cond_pl()); %LBRANCH; return; + case 0x2B: set_cond(!cond_pl()); %LBRANCH; return; + case 0x2C: set_cond(cond_ge()); %LBRANCH; return; + case 0x2D: set_cond(!cond_ge()); %LBRANCH; return; + case 0x2E: set_cond(cond_gt()); %LBRANCH; return; + case 0x2F: set_cond(!cond_gt()); %LBRANCH; return; + + case 0x3F: %SWI2; return; + + case 0x83: set_regop16(m_q.p.d); set_imm(); %CMP16; return; + case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return; + case 0x8E: set_regop16(m_y); set_imm(); %LD16; return; + case 0x8F: set_regop16(m_y); set_imm(); %ST16; return; + case 0x93: set_regop16(m_q.p.d); %DIRECT; %CMP16; return; + case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return; + case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return; + case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return; + case 0xA3: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; + case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return; + case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return; + case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return; + case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %CMP16; return; + case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return; + case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return; + case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return; + + case 0xCE: set_regop16(m_s); set_imm(); %LD16; return; + case 0xCF: set_regop16(m_s); set_imm(); %ST16; return; + case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return; + case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return; + case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return; + case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return; + case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return; + case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return; + + default: %ILLEGAL; return; + } + return; + +DISPATCH11: + @m_opcode = read_opcode(); + switch(m_opcode) + { + case 0x3F: %SWI3; return; + case 0x83: set_regop16(m_u); set_imm(); %CMP16; return; + case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return; + case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return; + case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return; + case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return; + case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return; + case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return; + case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return; + default: %ILLEGAL; return; + } + return; + +#include "base6x09.lst" + +PUSH_REGISTERS: + if (m_temp.w & 0x80) + { + @write_memory(--regop16().w, m_pc.b.l); + @write_memory(--regop16().w, m_pc.b.h); + nop(); + } + if (m_temp.w & 0x40) + { + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); + @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); + nop(); + } + if (m_temp.w & 0x20) + { + @write_memory(--regop16().w, m_y.b.l); + @write_memory(--regop16().w, m_y.b.h); + nop(); + } + if (m_temp.w & 0x10) + { + @write_memory(--regop16().w, m_x.b.l); + @write_memory(--regop16().w, m_x.b.h); + nop(); + } + if (m_temp.w & 0x08) + { + @write_memory(--regop16().w, m_dp); + nop(); + } + if (m_temp.w & 0x04) + { + @write_memory(--regop16().w, m_q.r.b); + nop(); + } + if (m_temp.w & 0x02) + { + @write_memory(--regop16().w, m_q.r.a); + nop(); + } + if (m_temp.w & 0x01) + { + @write_memory(--regop16().w, m_cc); + nop(); + } + return; + +PULL_REGISTERS: + if (m_temp.w & 0x01) + { + @m_cc = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x02) + { + @m_q.r.a = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x04) + { + @m_q.r.b = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x08) + { + @m_dp = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x10) + { + @m_x.b.h = read_memory(regop16().w++); + @m_x.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x20) + { + @m_y.b.h = read_memory(regop16().w++); + @m_y.b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x40) + { + @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); + @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); + nop(); + } + if (m_temp.w & 0x80) + { + @m_pc.b.h = read_memory(regop16().w++); + @m_pc.b.l = read_memory(regop16().w++); + nop(); + } + @(void)read_memory(regop16().w); + return; + +INDEXED: + @m_opcode = read_opcode_arg(); + if (m_opcode & 0x80) + { + switch(m_opcode & 0x7F) + { + case 0x00: case 0x20: case 0x40: case 0x60: + case 0x10: case 0x30: case 0x50: case 0x70: + m_temp.w = ireg(); + ireg()++; + @dummy_read_opcode_arg(0); + @dummy_vma(2); + break; + + case 0x01: case 0x21: case 0x41: case 0x61: + case 0x11: case 0x31: case 0x51: case 0x71: + m_temp.w = ireg(); + ireg() += 2; + @dummy_read_opcode_arg(0); + @dummy_vma(3); + break; + + case 0x02: case 0x22: case 0x42: case 0x62: + case 0x12: case 0x32: case 0x52: case 0x72: + ireg()--; + m_temp.w = ireg(); + @dummy_read_opcode_arg(0); + @dummy_vma(2); + break; + + case 0x03: case 0x23: case 0x43: case 0x63: + case 0x13: case 0x33: case 0x53: case 0x73: + ireg() -= 2; + m_temp.w = ireg(); + @dummy_read_opcode_arg(0); + @dummy_vma(3); + break; + + case 0x04: case 0x24: case 0x44: case 0x64: + case 0x14: case 0x34: case 0x54: case 0x74: + m_temp.w = ireg(); + @dummy_read_opcode_arg(0); + break; + + case 0x05: case 0x25: case 0x45: case 0x65: + case 0x15: case 0x35: case 0x55: case 0x75: + m_temp.w = ireg() + (int8_t) m_q.r.b; + @dummy_read_opcode_arg(0); + @dummy_vma(1); + break; + + case 0x06: case 0x26: case 0x46: case 0x66: + case 0x16: case 0x36: case 0x56: case 0x76: + m_temp.w = ireg() + (int8_t) m_q.r.a; + @dummy_read_opcode_arg(0); + @dummy_vma(1); + break; + + case 0x08: case 0x28: case 0x48: case 0x68: + case 0x18: case 0x38: case 0x58: case 0x78: + @m_temp.w = ireg() + (int8_t) read_opcode_arg(); + @dummy_read_opcode_arg(0); + break; + + case 0x09: case 0x29: case 0x49: case 0x69: + case 0x19: case 0x39: case 0x59: case 0x79: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = ireg() + m_temp.w; + @dummy_vma(3); + break; + + case 0x0B: case 0x2B: case 0x4B: case 0x6B: + case 0x1B: case 0x3B: case 0x5B: case 0x7B: + m_temp.w = ireg() + m_q.r.d; + @dummy_read_opcode_arg(0); + @dummy_read_opcode_arg(1); + @dummy_vma(3); + break; + + case 0x0C: case 0x2C: case 0x4C: case 0x6C: + case 0x1C: case 0x3C: case 0x5C: case 0x7C: + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_pc.w + (int8_t) m_temp.b.l; + @dummy_vma(1); + break; + + case 0x0D: case 0x2D: case 0x4D: case 0x6D: + case 0x1D: case 0x3D: case 0x5D: case 0x7D: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + m_temp.w = m_pc.w + (int16_t) m_temp.w; + @dummy_vma(4); + break; + + case 0x0F: case 0x2F: case 0x4F: case 0x6F: + case 0x1F: case 0x3F: case 0x5F: case 0x7F: + @m_temp.b.h = read_opcode_arg(); + @m_temp.b.l = read_opcode_arg(); + @dummy_vma(1); + break; + + default: + m_temp.w = 0x0000; + break; + } + + // indirect mode + if (m_opcode & 0x10) + { + set_ea(m_temp.w); + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + @dummy_vma(1); + ; + } + } + else + { + // 5-bit offset + m_temp.w = ireg() + (int8_t) ((m_opcode & 0x0F) | (m_opcode & 0x10 ? 0xF0 : 0x00)); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + ; + } + @set_ea(m_temp.w); + return; + +EXG: + { + uint8_t param = read_opcode_arg(); + uint16_t reg1, reg2; + + // Exchange differs if 16 bit register or 8 bit register is first + if (BIT(param, 7)) + { + reg1 = read_tfr_exg_816_register(param >> 4); + reg2 = read_tfr_exg_816_register(param >> 0); + } + else + { + reg1 = read_exg_168_register(param >> 4); + reg2 = read_exg_168_register(param >> 0); + } + write_exgtfr_register(param >> 0, reg1); + write_exgtfr_register(param >> 4, reg2); + } + @dummy_vma(hd6309_native_mode() ? 3 : 6); + return; + +TFR: + { + uint8_t param = read_opcode_arg(); + uint16_t reg = read_tfr_exg_816_register(param >> 4); + write_exgtfr_register(param >> 0, reg); + if ((param & 0x0F) == 4) + { + m_lds_encountered = true; + } + } + @dummy_vma(hd6309_native_mode() ? 2 : 4); + return; + +ILLEGAL: + log_illegal(); + return; diff --git a/src/devices/cpu/m6809/m6809.ops b/src/devices/cpu/m6809/m6809.ops deleted file mode 100644 index b6e40530880..00000000000 --- a/src/devices/cpu/m6809/m6809.ops +++ /dev/null @@ -1,605 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Nathan Woods -MAIN: - // check interrupt lines - switch(get_pending_interrupt()) - { - case VECTOR_NMI: goto NMI; - case VECTOR_FIRQ: goto FIRQ; - case VECTOR_IRQ: goto IRQ; - } - - // debugger hook - m_ppc = m_pc; - debugger_instruction_hook(m_pc.w); - - // opcode fetch - m_lic_func(ASSERT_LINE); - @m_opcode = read_opcode(); - m_lic_func(CLEAR_LINE); - - // dispatch opcode - switch(m_opcode) - { - case 0x00: case 0x01: %DIRECT; %NEG8; return; - case 0x03: case 0x02: %DIRECT; %COM8; return; - case 0x04: case 0x05: %DIRECT; %LSR8; return; - case 0x06: %DIRECT; %ROR8; return; - case 0x07: %DIRECT; %ASR8; return; - case 0x08: %DIRECT; %ASL8; return; - case 0x09: %DIRECT; %ROL8; return; - case 0x0A: case 0x0B: %DIRECT; %DEC8; return; - case 0x0C: %DIRECT; %INC8; return; - case 0x0D: %DIRECT; %TST8; return; - case 0x0E: %DIRECT; %JMP; return; - case 0x0F: %DIRECT; %CLR8; return; - - case 0x10: %DISPATCH10; return; - case 0x11: %DISPATCH11; return; - case 0x12: %NOP; return; - case 0x13: %SYNC; return; - case 0x16: set_cond(true); %LBRANCH; return; - case 0x17: %LBSR; return; - case 0x19: %DAA; return; - case 0x1A: set_imm(); %ORCC; return; - case 0x1C: set_imm(); %ANDCC; return; - case 0x1D: %SEX; return; - case 0x1E: %EXG; return; - case 0x1F: %TFR; return; - - case 0x20: set_cond(true); %BRANCH; return; - case 0x21: set_cond(false); %BRANCH; return; - case 0x22: set_cond(cond_hi()); %BRANCH; return; - case 0x23: set_cond(!cond_hi()); %BRANCH; return; - case 0x24: set_cond(cond_cc()); %BRANCH; return; - case 0x25: set_cond(!cond_cc()); %BRANCH; return; - case 0x26: set_cond(cond_ne()); %BRANCH; return; - case 0x27: set_cond(!cond_ne()); %BRANCH; return; - case 0x28: set_cond(cond_vc()); %BRANCH; return; - case 0x29: set_cond(!cond_vc()); %BRANCH; return; - case 0x2A: set_cond(cond_pl()); %BRANCH; return; - case 0x2B: set_cond(!cond_pl()); %BRANCH; return; - case 0x2C: set_cond(cond_ge()); %BRANCH; return; - case 0x2D: set_cond(!cond_ge()); %BRANCH; return; - case 0x2E: set_cond(cond_gt()); %BRANCH; return; - case 0x2F: set_cond(!cond_gt()); %BRANCH; return; - - case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return; - case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return; - case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return; - case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return; - case 0x34: %PSHS; return; - case 0x35: %PULS; return; - case 0x36: %PSHU; return; - case 0x37: %PULU; return; - case 0x39: %RTS; return; - case 0x3A: %ABX; return; - case 0x3B: %RTI; return; - case 0x3C: %CWAI; return; - case 0x3D: %MUL; return; - case 0x3F: %SWI; return; - - case 0x40: case 0x41: set_a(); %NEG8; return; - case 0x43: case 0x42: set_a(); %COM8; return; - case 0x44: case 0x45: set_a(); %LSR8; return; - case 0x46: set_a(); %ROR8; return; - case 0x47: set_a(); %ASR8; return; - case 0x48: set_a(); %ASL8; return; - case 0x49: set_a(); %ROL8; return; - case 0x4A: case 0x4B: set_a(); %DEC8; return; - case 0x4C: set_a(); %INC8; return; - case 0x4D: set_a(); %TST8; return; - case 0x4E: set_a(); %JMP; return; - case 0x4F: set_a(); %CLR8; return; - - case 0x50: case 0x51: set_b(); %NEG8; return; - case 0x53: case 0x52: set_b(); %COM8; return; - case 0x54: case 0x55: set_b(); %LSR8; return; - case 0x56: set_b(); %ROR8; return; - case 0x57: set_b(); %ASR8; return; - case 0x58: set_b(); %ASL8; return; - case 0x59: set_b(); %ROL8; return; - case 0x5A: case 0x5B: set_b(); %DEC8; return; - case 0x5C: set_b(); %INC8; return; - case 0x5D: set_b(); %TST8; return; - case 0x5E: set_b(); %JMP; return; - case 0x5F: set_b(); %CLR8; return; - - case 0x60: case 0x61: %INDEXED; %NEG8; return; - case 0x63: case 0x62: %INDEXED; %COM8; return; - case 0x64: case 0x65: %INDEXED; %LSR8; return; - case 0x66: %INDEXED; %ROR8; return; - case 0x67: %INDEXED; %ASR8; return; - case 0x68: %INDEXED; %ASL8; return; - case 0x69: %INDEXED; %ROL8; return; - case 0x6A: case 0x6B: %INDEXED; %DEC8; return; - case 0x6C: %INDEXED; %INC8; return; - case 0x6D: %INDEXED; %TST8; return; - case 0x6E: %INDEXED; %JMP; return; - case 0x6F: %INDEXED; %CLR8; return; - - case 0x70: case 0x71: %EXTENDED; %NEG8; return; - case 0x73: case 0x72: %EXTENDED; %COM8; return; - case 0x74: case 0x75: %EXTENDED; %LSR8; return; - case 0x76: %EXTENDED; %ROR8; return; - case 0x77: %EXTENDED; %ASR8; return; - case 0x78: %EXTENDED; %ASL8; return; - case 0x79: %EXTENDED; %ROL8; return; - case 0x7A: case 0x7B: %EXTENDED; %DEC8; return; - case 0x7C: %EXTENDED; %INC8; return; - case 0x7D: %EXTENDED; %TST8; return; - case 0x7E: %EXTENDED; %JMP; return; - case 0x7F: %EXTENDED; %CLR8; return; - - case 0x80: set_regop8(m_q.r.a); set_imm(); %SUB8; return; - case 0x81: set_regop8(m_q.r.a); set_imm(); %CMP8; return; - case 0x82: set_regop8(m_q.r.a); set_imm(); %SBC8; return; - case 0x83: set_regop16(m_q.p.d); set_imm(); %SUB16; return; - case 0x84: set_regop8(m_q.r.a); set_imm(); %AND8; return; - case 0x85: set_regop8(m_q.r.a); set_imm(); %BIT8; return; - case 0x86: set_regop8(m_q.r.a); set_imm(); %LD8; return; - case 0x87: set_regop8(m_q.r.a); set_imm(); %ST8; return; - case 0x88: set_regop8(m_q.r.a); set_imm(); %EOR8; return; - case 0x89: set_regop8(m_q.r.a); set_imm(); %ADC8; return; - case 0x8A: set_regop8(m_q.r.a); set_imm(); %OR8; return; - case 0x8B: set_regop8(m_q.r.a); set_imm(); %ADD8; return; - case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return; - case 0x8D: %BSR; return; - case 0x8E: set_regop16(m_x); set_imm(); %LD16; return; - case 0x8F: set_regop16(m_x); set_imm(); %ST16; return; - - case 0x90: set_regop8(m_q.r.a); %DIRECT; %SUB8; return; - case 0x91: set_regop8(m_q.r.a); %DIRECT; %CMP8; return; - case 0x92: set_regop8(m_q.r.a); %DIRECT; %SBC8; return; - case 0x93: set_regop16(m_q.p.d); %DIRECT; %SUB16; return; - case 0x94: set_regop8(m_q.r.a); %DIRECT; %AND8; return; - case 0x95: set_regop8(m_q.r.a); %DIRECT; %BIT8; return; - case 0x96: set_regop8(m_q.r.a); %DIRECT; %LD8; return; - case 0x97: set_regop8(m_q.r.a); %DIRECT; %ST8; return; - case 0x98: set_regop8(m_q.r.a); %DIRECT; %EOR8; return; - case 0x99: set_regop8(m_q.r.a); %DIRECT; %ADC8; return; - case 0x9A: set_regop8(m_q.r.a); %DIRECT; %OR8; return; - case 0x9B: set_regop8(m_q.r.a); %DIRECT; %ADD8; return; - case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return; - case 0x9D: %DIRECT; %JSR; return; - case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return; - case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return; - - case 0xA0: set_regop8(m_q.r.a); %INDEXED; %SUB8; return; - case 0xA1: set_regop8(m_q.r.a); %INDEXED; %CMP8; return; - case 0xA2: set_regop8(m_q.r.a); %INDEXED; %SBC8; return; - case 0xA3: set_regop16(m_q.p.d); %INDEXED; %SUB16; return; - case 0xA4: set_regop8(m_q.r.a); %INDEXED; %AND8; return; - case 0xA5: set_regop8(m_q.r.a); %INDEXED; %BIT8; return; - case 0xA6: set_regop8(m_q.r.a); %INDEXED; %LD8; return; - case 0xA7: set_regop8(m_q.r.a); %INDEXED; %ST8; return; - case 0xA8: set_regop8(m_q.r.a); %INDEXED; %EOR8; return; - case 0xA9: set_regop8(m_q.r.a); %INDEXED; %ADC8; return; - case 0xAA: set_regop8(m_q.r.a); %INDEXED; %OR8; return; - case 0xAB: set_regop8(m_q.r.a); %INDEXED; %ADD8; return; - case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return; - case 0xAD: %INDEXED; %JSR; return; - case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return; - case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return; - - case 0xB0: set_regop8(m_q.r.a); %EXTENDED; %SUB8; return; - case 0xB1: set_regop8(m_q.r.a); %EXTENDED; %CMP8; return; - case 0xB2: set_regop8(m_q.r.a); %EXTENDED; %SBC8; return; - case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %SUB16; return; - case 0xB4: set_regop8(m_q.r.a); %EXTENDED; %AND8; return; - case 0xB5: set_regop8(m_q.r.a); %EXTENDED; %BIT8; return; - case 0xB6: set_regop8(m_q.r.a); %EXTENDED; %LD8; return; - case 0xB7: set_regop8(m_q.r.a); %EXTENDED; %ST8; return; - case 0xB8: set_regop8(m_q.r.a); %EXTENDED; %EOR8; return; - case 0xB9: set_regop8(m_q.r.a); %EXTENDED; %ADC8; return; - case 0xBA: set_regop8(m_q.r.a); %EXTENDED; %OR8; return; - case 0xBB: set_regop8(m_q.r.a); %EXTENDED; %ADD8; return; - case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return; - case 0xBD: %EXTENDED; %JSR; return; - case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return; - case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return; - - case 0xC0: set_regop8(m_q.r.b); set_imm(); %SUB8; return; - case 0xC1: set_regop8(m_q.r.b); set_imm(); %CMP8; return; - case 0xC2: set_regop8(m_q.r.b); set_imm(); %SBC8; return; - case 0xC3: set_regop16(m_q.p.d); set_imm(); %ADD16; return; - case 0xC4: set_regop8(m_q.r.b); set_imm(); %AND8; return; - case 0xC5: set_regop8(m_q.r.b); set_imm(); %BIT8; return; - case 0xC6: set_regop8(m_q.r.b); set_imm(); %LD8; return; - case 0xC7: set_regop8(m_q.r.b); set_imm(); %ST8; return; - case 0xC8: set_regop8(m_q.r.b); set_imm(); %EOR8; return; - case 0xC9: set_regop8(m_q.r.b); set_imm(); %ADC8; return; - case 0xCA: set_regop8(m_q.r.b); set_imm(); %OR8; return; - case 0xCB: set_regop8(m_q.r.b); set_imm(); %ADD8; return; - case 0xCC: set_regop16(m_q.p.d); set_imm(); %LD16; return; - case 0xCD: set_regop16(m_q.p.d); set_imm(); %ST16; return; - case 0xCE: set_regop16(m_u); set_imm(); %LD16; return; - case 0xCF: set_regop16(m_u); set_imm(); %ST16; return; - - case 0xD0: set_regop8(m_q.r.b); %DIRECT; %SUB8; return; - case 0xD1: set_regop8(m_q.r.b); %DIRECT; %CMP8; return; - case 0xD2: set_regop8(m_q.r.b); %DIRECT; %SBC8; return; - case 0xD3: set_regop16(m_q.p.d); %DIRECT; %ADD16; return; - case 0xD4: set_regop8(m_q.r.b); %DIRECT; %AND8; return; - case 0xD5: set_regop8(m_q.r.b); %DIRECT; %BIT8; return; - case 0xD6: set_regop8(m_q.r.b); %DIRECT; %LD8; return; - case 0xD7: set_regop8(m_q.r.b); %DIRECT; %ST8; return; - case 0xD8: set_regop8(m_q.r.b); %DIRECT; %EOR8; return; - case 0xD9: set_regop8(m_q.r.b); %DIRECT; %ADC8; return; - case 0xDA: set_regop8(m_q.r.b); %DIRECT; %OR8; return; - case 0xDB: set_regop8(m_q.r.b); %DIRECT; %ADD8; return; - case 0xDC: set_regop16(m_q.p.d); %DIRECT; %LD16; return; - case 0xDD: set_regop16(m_q.p.d); %DIRECT; %ST16; return; - case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return; - case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return; - - case 0xE0: set_regop8(m_q.r.b); %INDEXED; %SUB8; return; - case 0xE1: set_regop8(m_q.r.b); %INDEXED; %CMP8; return; - case 0xE2: set_regop8(m_q.r.b); %INDEXED; %SBC8; return; - case 0xE3: set_regop16(m_q.p.d); %INDEXED; %ADD16; return; - case 0xE4: set_regop8(m_q.r.b); %INDEXED; %AND8; return; - case 0xE5: set_regop8(m_q.r.b); %INDEXED; %BIT8; return; - case 0xE6: set_regop8(m_q.r.b); %INDEXED; %LD8; return; - case 0xE7: set_regop8(m_q.r.b); %INDEXED; %ST8; return; - case 0xE8: set_regop8(m_q.r.b); %INDEXED; %EOR8; return; - case 0xE9: set_regop8(m_q.r.b); %INDEXED; %ADC8; return; - case 0xEA: set_regop8(m_q.r.b); %INDEXED; %OR8; return; - case 0xEB: set_regop8(m_q.r.b); %INDEXED; %ADD8; return; - case 0xEC: set_regop16(m_q.p.d); %INDEXED; %LD16; return; - case 0xED: set_regop16(m_q.p.d); %INDEXED; %ST16; return; - case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return; - case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return; - - case 0xF0: set_regop8(m_q.r.b); %EXTENDED; %SUB8; return; - case 0xF1: set_regop8(m_q.r.b); %EXTENDED; %CMP8; return; - case 0xF2: set_regop8(m_q.r.b); %EXTENDED; %SBC8; return; - case 0xF3: set_regop16(m_q.p.d); %EXTENDED; %ADD16; return; - case 0xF4: set_regop8(m_q.r.b); %EXTENDED; %AND8; return; - case 0xF5: set_regop8(m_q.r.b); %EXTENDED; %BIT8; return; - case 0xF6: set_regop8(m_q.r.b); %EXTENDED; %LD8; return; - case 0xF7: set_regop8(m_q.r.b); %EXTENDED; %ST8; return; - case 0xF8: set_regop8(m_q.r.b); %EXTENDED; %EOR8; return; - case 0xF9: set_regop8(m_q.r.b); %EXTENDED; %ADC8; return; - case 0xFA: set_regop8(m_q.r.b); %EXTENDED; %OR8; return; - case 0xFB: set_regop8(m_q.r.b); %EXTENDED; %ADD8; return; - case 0xFC: set_regop16(m_q.p.d); %EXTENDED; %LD16; return; - case 0xFD: set_regop16(m_q.p.d); %EXTENDED; %ST16; return; - case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return; - case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return; - default: %ILLEGAL; return; - } - return; - -DISPATCH10: - @m_opcode = read_opcode(); - switch(m_opcode) - { - case 0x20: set_cond(true); %LBRANCH; return; - case 0x21: set_cond(false); %LBRANCH; return; - case 0x22: set_cond(cond_hi()); %LBRANCH; return; - case 0x23: set_cond(!cond_hi()); %LBRANCH; return; - case 0x24: set_cond(cond_cc()); %LBRANCH; return; - case 0x25: set_cond(!cond_cc()); %LBRANCH; return; - case 0x26: set_cond(cond_ne()); %LBRANCH; return; - case 0x27: set_cond(!cond_ne()); %LBRANCH; return; - case 0x28: set_cond(cond_vc()); %LBRANCH; return; - case 0x29: set_cond(!cond_vc()); %LBRANCH; return; - case 0x2A: set_cond(cond_pl()); %LBRANCH; return; - case 0x2B: set_cond(!cond_pl()); %LBRANCH; return; - case 0x2C: set_cond(cond_ge()); %LBRANCH; return; - case 0x2D: set_cond(!cond_ge()); %LBRANCH; return; - case 0x2E: set_cond(cond_gt()); %LBRANCH; return; - case 0x2F: set_cond(!cond_gt()); %LBRANCH; return; - - case 0x3F: %SWI2; return; - - case 0x83: set_regop16(m_q.p.d); set_imm(); %CMP16; return; - case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return; - case 0x8E: set_regop16(m_y); set_imm(); %LD16; return; - case 0x8F: set_regop16(m_y); set_imm(); %ST16; return; - case 0x93: set_regop16(m_q.p.d); %DIRECT; %CMP16; return; - case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return; - case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return; - case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return; - case 0xA3: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; - case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return; - case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return; - case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return; - case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %CMP16; return; - case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return; - case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return; - case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return; - - case 0xCE: set_regop16(m_s); set_imm(); %LD16; return; - case 0xCF: set_regop16(m_s); set_imm(); %ST16; return; - case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return; - case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return; - case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return; - case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return; - case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return; - case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return; - - default: %ILLEGAL; return; - } - return; - -DISPATCH11: - @m_opcode = read_opcode(); - switch(m_opcode) - { - case 0x3F: %SWI3; return; - case 0x83: set_regop16(m_u); set_imm(); %CMP16; return; - case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return; - case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return; - case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return; - case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return; - case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return; - case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return; - case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return; - default: %ILLEGAL; return; - } - return; - -#include "base6x09.ops" - -PUSH_REGISTERS: - if (m_temp.w & 0x80) - { - @write_memory(--regop16().w, m_pc.b.l); - @write_memory(--regop16().w, m_pc.b.h); - nop(); - } - if (m_temp.w & 0x40) - { - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.l : m_s.b.l); - @write_memory(--regop16().w, (®op16() == &m_s) ? m_u.b.h : m_s.b.h); - nop(); - } - if (m_temp.w & 0x20) - { - @write_memory(--regop16().w, m_y.b.l); - @write_memory(--regop16().w, m_y.b.h); - nop(); - } - if (m_temp.w & 0x10) - { - @write_memory(--regop16().w, m_x.b.l); - @write_memory(--regop16().w, m_x.b.h); - nop(); - } - if (m_temp.w & 0x08) - { - @write_memory(--regop16().w, m_dp); - nop(); - } - if (m_temp.w & 0x04) - { - @write_memory(--regop16().w, m_q.r.b); - nop(); - } - if (m_temp.w & 0x02) - { - @write_memory(--regop16().w, m_q.r.a); - nop(); - } - if (m_temp.w & 0x01) - { - @write_memory(--regop16().w, m_cc); - nop(); - } - return; - -PULL_REGISTERS: - if (m_temp.w & 0x01) - { - @m_cc = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x02) - { - @m_q.r.a = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x04) - { - @m_q.r.b = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x08) - { - @m_dp = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x10) - { - @m_x.b.h = read_memory(regop16().w++); - @m_x.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x20) - { - @m_y.b.h = read_memory(regop16().w++); - @m_y.b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x40) - { - @(®op16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++); - @(®op16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++); - nop(); - } - if (m_temp.w & 0x80) - { - @m_pc.b.h = read_memory(regop16().w++); - @m_pc.b.l = read_memory(regop16().w++); - nop(); - } - @(void)read_memory(regop16().w); - return; - -INDEXED: - @m_opcode = read_opcode_arg(); - if (m_opcode & 0x80) - { - switch(m_opcode & 0x7F) - { - case 0x00: case 0x20: case 0x40: case 0x60: - case 0x10: case 0x30: case 0x50: case 0x70: - m_temp.w = ireg(); - ireg()++; - @dummy_read_opcode_arg(0); - @dummy_vma(2); - break; - - case 0x01: case 0x21: case 0x41: case 0x61: - case 0x11: case 0x31: case 0x51: case 0x71: - m_temp.w = ireg(); - ireg() += 2; - @dummy_read_opcode_arg(0); - @dummy_vma(3); - break; - - case 0x02: case 0x22: case 0x42: case 0x62: - case 0x12: case 0x32: case 0x52: case 0x72: - ireg()--; - m_temp.w = ireg(); - @dummy_read_opcode_arg(0); - @dummy_vma(2); - break; - - case 0x03: case 0x23: case 0x43: case 0x63: - case 0x13: case 0x33: case 0x53: case 0x73: - ireg() -= 2; - m_temp.w = ireg(); - @dummy_read_opcode_arg(0); - @dummy_vma(3); - break; - - case 0x04: case 0x24: case 0x44: case 0x64: - case 0x14: case 0x34: case 0x54: case 0x74: - m_temp.w = ireg(); - @dummy_read_opcode_arg(0); - break; - - case 0x05: case 0x25: case 0x45: case 0x65: - case 0x15: case 0x35: case 0x55: case 0x75: - m_temp.w = ireg() + (int8_t) m_q.r.b; - @dummy_read_opcode_arg(0); - @dummy_vma(1); - break; - - case 0x06: case 0x26: case 0x46: case 0x66: - case 0x16: case 0x36: case 0x56: case 0x76: - m_temp.w = ireg() + (int8_t) m_q.r.a; - @dummy_read_opcode_arg(0); - @dummy_vma(1); - break; - - case 0x08: case 0x28: case 0x48: case 0x68: - case 0x18: case 0x38: case 0x58: case 0x78: - @m_temp.w = ireg() + (int8_t) read_opcode_arg(); - @dummy_read_opcode_arg(0); - break; - - case 0x09: case 0x29: case 0x49: case 0x69: - case 0x19: case 0x39: case 0x59: case 0x79: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = ireg() + m_temp.w; - @dummy_vma(3); - break; - - case 0x0B: case 0x2B: case 0x4B: case 0x6B: - case 0x1B: case 0x3B: case 0x5B: case 0x7B: - m_temp.w = ireg() + m_q.r.d; - @dummy_read_opcode_arg(0); - @dummy_read_opcode_arg(1); - @dummy_vma(3); - break; - - case 0x0C: case 0x2C: case 0x4C: case 0x6C: - case 0x1C: case 0x3C: case 0x5C: case 0x7C: - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_pc.w + (int8_t) m_temp.b.l; - @dummy_vma(1); - break; - - case 0x0D: case 0x2D: case 0x4D: case 0x6D: - case 0x1D: case 0x3D: case 0x5D: case 0x7D: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - m_temp.w = m_pc.w + (int16_t) m_temp.w; - @dummy_vma(4); - break; - - case 0x0F: case 0x2F: case 0x4F: case 0x6F: - case 0x1F: case 0x3F: case 0x5F: case 0x7F: - @m_temp.b.h = read_opcode_arg(); - @m_temp.b.l = read_opcode_arg(); - @dummy_vma(1); - break; - - default: - m_temp.w = 0x0000; - break; - } - - // indirect mode - if (m_opcode & 0x10) - { - set_ea(m_temp.w); - @m_temp.b.h = read_operand(0); - @m_temp.b.l = read_operand(1); - @dummy_vma(1); - ; - } - } - else - { - // 5-bit offset - m_temp.w = ireg() + (int8_t) ((m_opcode & 0x0F) | (m_opcode & 0x10 ? 0xF0 : 0x00)); - @dummy_read_opcode_arg(0); - @dummy_vma(1); - ; - } - @set_ea(m_temp.w); - return; - -EXG: - { - uint8_t param = read_opcode_arg(); - uint16_t reg1, reg2; - - // Exchange differs if 16 bit register or 8 bit register is first - if (BIT(param, 7)) - { - reg1 = read_tfr_exg_816_register(param >> 4); - reg2 = read_tfr_exg_816_register(param >> 0); - } - else - { - reg1 = read_exg_168_register(param >> 4); - reg2 = read_exg_168_register(param >> 0); - } - write_exgtfr_register(param >> 0, reg1); - write_exgtfr_register(param >> 4, reg2); - } - @dummy_vma(hd6309_native_mode() ? 3 : 6); - return; - -TFR: - { - uint8_t param = read_opcode_arg(); - uint16_t reg = read_tfr_exg_816_register(param >> 4); - write_exgtfr_register(param >> 0, reg); - if ((param & 0x0F) == 4) - { - m_lds_encountered = true; - } - } - @dummy_vma(hd6309_native_mode() ? 2 : 4); - return; - -ILLEGAL: - log_illegal(); - return; -- cgit v1.2.3