From c144c79ee3437d0240a798e69a8089bddd031760 Mon Sep 17 00:00:00 2001 From: hap Date: Tue, 6 Feb 2024 18:08:36 +0100 Subject: h8: add preliminary h8/325 New systems marked not working ------------------------------ Kasparov Prisma [hap, Sean Riddle] --- scripts/src/cpu.lua | 2 + src/devices/cpu/h8/gt913.cpp | 1 + src/devices/cpu/h8/h8325.cpp | 210 +++++++++++++++++++++++++ src/devices/cpu/h8/h8325.h | 119 ++++++++++++++ src/devices/cpu/h8/h8_dma.cpp | 3 + src/devices/cpu/h8/h8_dtc.cpp | 3 + src/devices/cpu/h8/h8_intc.cpp | 4 +- src/devices/cpu/h8/h8_watchdog.cpp | 3 + src/devices/cpu/h8/h8_watchdog.h | 33 +--- src/devices/cpu/h8/h8d.cpp | 2 +- src/devices/cpu/h8/h8hd.cpp | 2 +- src/devices/cpu/h8/h8s2000d.cpp | 2 +- src/devices/cpu/h8/h8s2600d.cpp | 2 +- src/mame/mame.lst | 3 + src/mame/saitek/prisma.cpp | 312 +++++++++++++++++++++++++++++++++++++ 15 files changed, 664 insertions(+), 37 deletions(-) create mode 100644 src/devices/cpu/h8/h8325.cpp create mode 100644 src/devices/cpu/h8/h8325.h create mode 100644 src/mame/saitek/prisma.cpp diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index cad69070127..61f91225e57 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -699,6 +699,8 @@ if CPUS["H8"] then MAME_DIR .. "src/devices/cpu/h8/h8s2000.h", MAME_DIR .. "src/devices/cpu/h8/h8s2600.cpp", MAME_DIR .. "src/devices/cpu/h8/h8s2600.h", + MAME_DIR .. "src/devices/cpu/h8/h8325.cpp", + MAME_DIR .. "src/devices/cpu/h8/h8325.h", MAME_DIR .. "src/devices/cpu/h8/h83337.cpp", MAME_DIR .. "src/devices/cpu/h8/h83337.h", MAME_DIR .. "src/devices/cpu/h8/h83002.cpp", diff --git a/src/devices/cpu/h8/gt913.cpp b/src/devices/cpu/h8/gt913.cpp index dd7cf15df8d..bcefcd2f83c 100644 --- a/src/devices/cpu/h8/gt913.cpp +++ b/src/devices/cpu/h8/gt913.cpp @@ -1,6 +1,7 @@ // license:BSD-3-Clause // copyright-holders:Devin Acker /*************************************************************************** + Casio GT913 (uPD913) This chip powers several late-90s/early-2000s Casio keyboards. diff --git a/src/devices/cpu/h8/h8325.cpp b/src/devices/cpu/h8/h8325.cpp new file mode 100644 index 00000000000..d34716b3ec5 --- /dev/null +++ b/src/devices/cpu/h8/h8325.cpp @@ -0,0 +1,210 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +/*************************************************************************** + + h8325.cpp + + H8/325 family emulation + + TODO: + - 16-bit timer is very different, needs a new subdevice? + - IRQ controller is slightly different + - serial controllers are slightly different + +***************************************************************************/ + +#include "emu.h" +#include "h8325.h" + +DEFINE_DEVICE_TYPE(H83257, h83257_device, "h83257", "Hitachi H8/3257") +DEFINE_DEVICE_TYPE(H83256, h83256_device, "h83256", "Hitachi H8/3256") +DEFINE_DEVICE_TYPE(H8325, h8325_device, "h8325", "Hitachi H8/325") +DEFINE_DEVICE_TYPE(H8324, h8324_device, "h8324", "Hitachi H8/324") +DEFINE_DEVICE_TYPE(H8323, h8323_device, "h8322", "Hitachi H8/323") +DEFINE_DEVICE_TYPE(H8322, h8322_device, "h8322", "Hitachi H8/322") + + +h8325_device::h8325_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start) : + h8_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h8325_device::map), this)), + m_intc(*this, "intc"), + m_port1(*this, "port1"), + m_port2(*this, "port2"), + m_port3(*this, "port3"), + m_port4(*this, "port4"), + m_port5(*this, "port5"), + m_port6(*this, "port6"), + m_port7(*this, "port7"), + m_timer8_0(*this, "timer8_0"), + m_timer8_1(*this, "timer8_1"), + m_timer16(*this, "timer16"), + m_timer16_0(*this, "timer16:0"), + m_syscr(0), + m_ram_start(start) +{ +} + +h83257_device::h83257_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H83257, tag, owner, clock, 0xf780) +{ +} + +h83256_device::h83256_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H83256, tag, owner, clock, 0xf780) +{ +} + +h8325_device::h8325_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H8325, tag, owner, clock, 0xfb80) +{ +} + +h8324_device::h8324_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H8324, tag, owner, clock, 0xfb80) +{ +} + +h8323_device::h8323_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H8323, tag, owner, clock, 0xfd80) +{ +} + +h8322_device::h8322_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + h8325_device(mconfig, H8322, tag, owner, clock, 0xfe80) +{ +} + +void h8325_device::map(address_map &map) +{ + map(m_ram_start, 0xff7f).ram(); + +// map(0xff90, 0xff90).rw(m_timer16_0, FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w)); +// map(0xff91, 0xff91).rw(m_timer16_0, FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w)); +// map(0xff92, 0xff93).rw(m_timer16_0, FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w)); +// map(0xff94, 0xff95).rw(m_timer16_0, FUNC(h8_timer16_channel_device::ocr_r, FUNC(h8_timer16_channel_device:ocr_w)); +// map(0xff96, 0xff96).rw(m_timer16_0, FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w)); +// map(0xff97, 0xff97).rw(m_timer16_0, FUNC(h8_timer16_channel_device::tocr_r, FUNC(h8_timer16_channel_device:tocr_w)); +// map(0xff98, 0xff99).r(m_timer16_0, FUNC(h8_timer16_channel_device::tgr_r)); + + map(0xffb0, 0xffb0).w(m_port1, FUNC(h8_port_device::ddr_w)); + map(0xffb1, 0xffb1).w(m_port2, FUNC(h8_port_device::ddr_w)); + map(0xffb2, 0xffb2).rw(m_port1, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffb3, 0xffb3).rw(m_port2, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffb4, 0xffb4).w(m_port3, FUNC(h8_port_device::ddr_w)); + map(0xffb5, 0xffb5).w(m_port4, FUNC(h8_port_device::ddr_w)); + map(0xffb6, 0xffb6).rw(m_port3, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffb7, 0xffb7).rw(m_port4, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffb8, 0xffb8).w(m_port5, FUNC(h8_port_device::ddr_w)); + map(0xffb9, 0xffb9).w(m_port6, FUNC(h8_port_device::ddr_w)); + map(0xffba, 0xffba).rw(m_port5, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffbb, 0xffbb).rw(m_port6, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + map(0xffbc, 0xffbc).w(m_port7, FUNC(h8_port_device::ddr_w)); + map(0xffbe, 0xffbe).rw(m_port7, FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w)); + + map(0xffc4, 0xffc4).rw(FUNC(h8325_device::syscr_r), FUNC(h8325_device::syscr_w)); + map(0xffc5, 0xffc5).r(FUNC(h8325_device::mdcr_r)); + map(0xffc6, 0xffc6).rw(m_intc, FUNC(h8_intc_device::iscr_r), FUNC(h8_intc_device::iscr_w)); + map(0xffc7, 0xffc7).rw(m_intc, FUNC(h8_intc_device::ier_r), FUNC(h8_intc_device::ier_w)); + map(0xffc8, 0xffc8).rw(m_timer8_0, FUNC(h8_timer8_channel_device::tcr_r), FUNC(h8_timer8_channel_device::tcr_w)); + map(0xffc9, 0xffc9).rw(m_timer8_0, FUNC(h8_timer8_channel_device::tcsr_r), FUNC(h8_timer8_channel_device::tcsr_w)); + map(0xffca, 0xffcb).rw(m_timer8_0, FUNC(h8_timer8_channel_device::tcor_r), FUNC(h8_timer8_channel_device::tcor_w)); + map(0xffcc, 0xffcc).rw(m_timer8_0, FUNC(h8_timer8_channel_device::tcnt_r), FUNC(h8_timer8_channel_device::tcnt_w)); + map(0xffd0, 0xffd0).rw(m_timer8_1, FUNC(h8_timer8_channel_device::tcr_r), FUNC(h8_timer8_channel_device::tcr_w)); + map(0xffd1, 0xffd1).rw(m_timer8_1, FUNC(h8_timer8_channel_device::tcsr_r), FUNC(h8_timer8_channel_device::tcsr_w)); + map(0xffd2, 0xffd3).rw(m_timer8_1, FUNC(h8_timer8_channel_device::tcor_r), FUNC(h8_timer8_channel_device::tcor_w)); + map(0xffd4, 0xffd4).rw(m_timer8_1, FUNC(h8_timer8_channel_device::tcnt_r), FUNC(h8_timer8_channel_device::tcnt_w)); + + map(0xffd8, 0xffd8).rw(m_sci[0], FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w)); + map(0xffd9, 0xffd9).rw(m_sci[0], FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w)); + map(0xffda, 0xffda).rw(m_sci[0], FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w)); + map(0xffdb, 0xffdb).rw(m_sci[0], FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w)); + map(0xffdc, 0xffdc).rw(m_sci[0], FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w)); + map(0xffdd, 0xffdd).r(m_sci[0], FUNC(h8_sci_device::rdr_r)); + map(0xffe0, 0xffe0).rw(m_sci[1], FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w)); + map(0xffe1, 0xffe1).rw(m_sci[1], FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w)); + map(0xffe2, 0xffe2).rw(m_sci[1], FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w)); + map(0xffe3, 0xffe3).rw(m_sci[1], FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w)); + map(0xffe4, 0xffe4).rw(m_sci[1], FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w)); + map(0xffe5, 0xffe5).r(m_sci[1], FUNC(h8_sci_device::rdr_r)); +} + +void h8325_device::device_add_mconfig(machine_config &config) +{ + H8_INTC(config, m_intc, *this); + H8_PORT(config, m_port1, *this, h8_device::PORT_1, 0x00, 0x00); + H8_PORT(config, m_port2, *this, h8_device::PORT_2, 0x00, 0x00); + H8_PORT(config, m_port3, *this, h8_device::PORT_3, 0x00, 0x00); + H8_PORT(config, m_port4, *this, h8_device::PORT_4, 0x00, 0x00); + H8_PORT(config, m_port5, *this, h8_device::PORT_5, 0x00, 0xc0); + H8_PORT(config, m_port6, *this, h8_device::PORT_6, 0x00, 0x80); + H8_PORT(config, m_port7, *this, h8_device::PORT_7, 0x00, 0x00); + H8_TIMER8_CHANNEL(config, m_timer8_0, *this, m_intc, 12, 13, 14, 8, 8, 64, 64, 1024, 1024); + H8_TIMER8_CHANNEL(config, m_timer8_1, *this, m_intc, 15, 16, 17, 8, 8, 64, 64, 1024, 1024); + H8_TIMER16(config, m_timer16, *this, 1, 0xff); + H8_TIMER16_CHANNEL(config, m_timer16_0, *this, 2, 0, m_intc, 8); + H8_SCI(config, m_sci[0], 0, *this, m_intc, 18, 19, 20, 20); + H8_SCI(config, m_sci[1], 1, *this, m_intc, 21, 22, 23, 23); +} + +void h8325_device::execute_set_input(int inputnum, int state) +{ + m_intc->set_input(inputnum, state); +} + +void h8325_device::irq_setup() +{ + m_CCR |= F_I; +} + +void h8325_device::update_irq_filter() +{ + if(m_CCR & F_I) + m_intc->set_filter(2, -1); + else + m_intc->set_filter(0, -1); +} + +void h8325_device::interrupt_taken() +{ + standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC); +} + +void h8325_device::internal_update(uint64_t current_time) +{ + uint64_t event_time = 0; + + add_event(event_time, m_sci[0]->internal_update(current_time)); + add_event(event_time, m_sci[1]->internal_update(current_time)); + add_event(event_time, m_timer8_0->internal_update(current_time)); + add_event(event_time, m_timer8_1->internal_update(current_time)); + add_event(event_time, m_timer16_0->internal_update(current_time)); + + recompute_bcount(event_time); +} + +void h8325_device::device_start() +{ + h8_device::device_start(); +} + +void h8325_device::device_reset() +{ + h8_device::device_reset(); + m_syscr = 0x01; +} + +uint8_t h8325_device::syscr_r() +{ + return m_syscr | 0x0a; +} + +void h8325_device::syscr_w(uint8_t data) +{ + logerror("syscr = %02x\n", data); + m_syscr = data; +} + +uint8_t h8325_device::mdcr_r() +{ + logerror("mdcr_r\n"); + return 0xe7; +} diff --git a/src/devices/cpu/h8/h8325.h b/src/devices/cpu/h8/h8325.h new file mode 100644 index 00000000000..bc81961d25e --- /dev/null +++ b/src/devices/cpu/h8/h8325.h @@ -0,0 +1,119 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +/*************************************************************************** + + h8325.h + + H8/325 family emulation + + H8-300-based mcus. + + Variant ROM RAM + H8/3257 60K 2K + H8/3256 48K 2K + H8/325 32K 1K + H8/324 24K 1K + H8/323 16K 512B + H8/322 8K 256B + +***************************************************************************/ + +#ifndef MAME_CPU_H8_H8325_H +#define MAME_CPU_H8_H8325_H + +#pragma once + +#include "h8.h" +#include "h8_intc.h" +#include "h8_port.h" +#include "h8_timer8.h" +#include "h8_timer16.h" +#include "h8_sci.h" + +class h8325_device : public h8_device { +public: + h8325_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + auto read_port1() { return m_read_port [PORT_1].bind(); } + auto write_port1() { return m_write_port[PORT_1].bind(); } + auto read_port2() { return m_read_port [PORT_2].bind(); } + auto write_port2() { return m_write_port[PORT_2].bind(); } + auto read_port3() { return m_read_port [PORT_3].bind(); } + auto write_port3() { return m_write_port[PORT_3].bind(); } + auto read_port4() { return m_read_port [PORT_4].bind(); } + auto write_port4() { return m_write_port[PORT_4].bind(); } + auto read_port5() { return m_read_port [PORT_5].bind(); } + auto write_port5() { return m_write_port[PORT_5].bind(); } + auto read_port6() { return m_read_port [PORT_6].bind(); } + auto write_port6() { return m_write_port[PORT_6].bind(); } + auto read_port7() { return m_read_port [PORT_7].bind(); } + auto write_port7() { return m_write_port[PORT_7].bind(); } + + uint8_t syscr_r(); + void syscr_w(uint8_t data); + uint8_t mdcr_r(); + +protected: + h8325_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start); + + required_device m_intc; + required_device m_port1; + required_device m_port2; + required_device m_port3; + required_device m_port4; + required_device m_port5; + required_device m_port6; + required_device m_port7; + required_device m_timer8_0; + required_device m_timer8_1; + required_device m_timer16; + required_device m_timer16_0; + + uint8_t m_syscr; + uint32_t m_ram_start; + + virtual void update_irq_filter() override; + virtual void interrupt_taken() override; + virtual void irq_setup() override; + virtual void internal_update(uint64_t current_time) override; + virtual void device_add_mconfig(machine_config &config) override; + void map(address_map &map); + + virtual void device_start() override; + virtual void device_reset() override; + virtual void execute_set_input(int inputnum, int state) override; +}; + +class h83256_device : public h8325_device { +public: + h83256_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class h83257_device : public h8325_device { +public: + h83257_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class h8324_device : public h8325_device { +public: + h8324_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class h8323_device : public h8325_device { +public: + h8323_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class h8322_device : public h8325_device { +public: + h8322_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +DECLARE_DEVICE_TYPE(H83257, h83257_device) +DECLARE_DEVICE_TYPE(H83256, h83256_device) +DECLARE_DEVICE_TYPE(H8325, h8325_device) +DECLARE_DEVICE_TYPE(H8324, h8324_device) +DECLARE_DEVICE_TYPE(H8323, h8323_device) +DECLARE_DEVICE_TYPE(H8322, h8322_device) + +#endif // MAME_CPU_H8_H8325_H diff --git a/src/devices/cpu/h8/h8_dma.cpp b/src/devices/cpu/h8/h8_dma.cpp index 33b277c38e4..4dea329f968 100644 --- a/src/devices/cpu/h8/h8_dma.cpp +++ b/src/devices/cpu/h8/h8_dma.cpp @@ -1,3 +1,6 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert + #include "emu.h" #include "h8_dma.h" diff --git a/src/devices/cpu/h8/h8_dtc.cpp b/src/devices/cpu/h8/h8_dtc.cpp index 8d51c067843..a9e53734ce8 100644 --- a/src/devices/cpu/h8/h8_dtc.cpp +++ b/src/devices/cpu/h8/h8_dtc.cpp @@ -1,3 +1,6 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert + #include "emu.h" #include "h8_dtc.h" diff --git a/src/devices/cpu/h8/h8_intc.cpp b/src/devices/cpu/h8/h8_intc.cpp index a2fdcdd7cfc..71cddc628ba 100644 --- a/src/devices/cpu/h8/h8_intc.cpp +++ b/src/devices/cpu/h8/h8_intc.cpp @@ -389,8 +389,8 @@ void h8s_intc_device::iprk_w(uint8_t data) const int h8s_intc_device::vector_to_slot[92] = { -1, -1, -1, -1, -1, -1, -1, -1, // NMI at 7 -1, -1, -1, -1, -1, -1, -1, -1, - 0, 1, 2, 2, 3, 3, 4, 4, // IRQ 0-7 - 5, 6, 7, 8, 9, 9, 9, 9, // SWDTEND, WOVI, CMI, (reserved), ADI + 0, 1, 2, 2, 3, 3, 4, 4, // IRQ 0-7 + 5, 6, 7, 8, 9, 9, 9, 9, // SWDTEND, WOVI, CMI, (reserved), ADI 10, 10, 10, 10, 10, 10, 10, 10, // TGI0A, TGI0B, TGI0C, TGI0D, TGI0V 11, 11, 11, 11, 12, 12, 12, 12, // TGI1A, TGI1B, TGI1V, TGI1U, TGI2A, TGI2B, TGI2V, TGI2U 13, 13, 13, 13, 13, 13, 13, 13, // TGI3A, TGI3B, TGI3C, TGI3D, TGI3V diff --git a/src/devices/cpu/h8/h8_watchdog.cpp b/src/devices/cpu/h8/h8_watchdog.cpp index 0bab0b3267b..579b1fdb543 100644 --- a/src/devices/cpu/h8/h8_watchdog.cpp +++ b/src/devices/cpu/h8/h8_watchdog.cpp @@ -1,3 +1,6 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert + #include "emu.h" #include "h8_watchdog.h" diff --git a/src/devices/cpu/h8/h8_watchdog.h b/src/devices/cpu/h8/h8_watchdog.h index d227e31be87..c9d1ba39d6f 100644 --- a/src/devices/cpu/h8/h8_watchdog.h +++ b/src/devices/cpu/h8/h8_watchdog.h @@ -1,40 +1,11 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert /*************************************************************************** h8_watchdog.h H8 watchdog/timer -**************************************************************************** - - Copyright Olivier Galibert - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name 'MAME' nor the names of its contributors may be - used to endorse or promote products derived from this software - without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ***************************************************************************/ #ifndef MAME_CPU_H8_H8_WATCHDOG_H diff --git a/src/devices/cpu/h8/h8d.cpp b/src/devices/cpu/h8/h8d.cpp index a6d5bb503c0..76cd4501bcf 100644 --- a/src/devices/cpu/h8/h8d.cpp +++ b/src/devices/cpu/h8/h8d.cpp @@ -2,7 +2,7 @@ // copyright-holders:Olivier Galibert /*************************************************************************** - h8d.h + h8d.cpp H8-300 base cpu emulation, disassembler diff --git a/src/devices/cpu/h8/h8hd.cpp b/src/devices/cpu/h8/h8hd.cpp index ee3a1d4b4a2..acc0f307612 100644 --- a/src/devices/cpu/h8/h8hd.cpp +++ b/src/devices/cpu/h8/h8hd.cpp @@ -2,7 +2,7 @@ // copyright-holders:Olivier Galibert /*************************************************************************** - h8d.h + h8hd.cpp H8-300H base cpu emulation, disassembler diff --git a/src/devices/cpu/h8/h8s2000d.cpp b/src/devices/cpu/h8/h8s2000d.cpp index e85643b3cbe..62ddf49d8cc 100644 --- a/src/devices/cpu/h8/h8s2000d.cpp +++ b/src/devices/cpu/h8/h8s2000d.cpp @@ -2,7 +2,7 @@ // copyright-holders:Olivier Galibert /*************************************************************************** - h8d.h + h8s2000d.cpp H8S-2000 base cpu emulation, disassembler diff --git a/src/devices/cpu/h8/h8s2600d.cpp b/src/devices/cpu/h8/h8s2600d.cpp index 038d8525e3c..165f2c6e2e6 100644 --- a/src/devices/cpu/h8/h8s2600d.cpp +++ b/src/devices/cpu/h8/h8s2600d.cpp @@ -2,7 +2,7 @@ // copyright-holders:Olivier Galibert /*************************************************************************** - h8d.h + h8s2600d.h H8S-2600 base cpu emulation, disassembler diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 18bbc9f969c..52c8a53743e 100644 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -38538,6 +38538,9 @@ ccmk6 @source:saitek/minichess.cpp smchess +@source:saitek/prisma.cpp +prisma + @source:saitek/prschess.cpp prschess diff --git a/src/mame/saitek/prisma.cpp b/src/mame/saitek/prisma.cpp new file mode 100644 index 00000000000..649890ee94a --- /dev/null +++ b/src/mame/saitek/prisma.cpp @@ -0,0 +1,312 @@ +// license:BSD-3-Clause +// copyright-holders:hap +// thanks-to:Sean Riddle +/******************************************************************************* + +Saitek Kasparov Prisma + +Hardware notes: +- PCB label: ST9A-PE-001 +- Hitachi H8/325 MCU, 20MHz XTAL +- Epson SED1502F, LCD screen (same as simultano) +- piezo, 16+3 leds, button sensors chessboard + +It was also sold by Tandy as Chess Champion 2150L, with a slower CPU (16MHz XTAL). + +TODO: +- does not work, it's waiting for a 16-bit timer IRQ? +- everything else + +*******************************************************************************/ + +#include "emu.h" + +#include "cpu/h8/h8325.h" +#include "machine/sensorboard.h" +#include "sound/dac.h" +#include "video/pwm.h" + +#include "speaker.h" + +// internal artwork +//#include "saitek_prisma.lh" + + +namespace { + +class prisma_state : public driver_device +{ +public: + prisma_state(const machine_config &mconfig, device_type type, const char *tag) : + driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu"), + m_board(*this, "board"), + m_display(*this, "display"), + m_dac(*this, "dac"), + m_inputs(*this, "IN.%u", 0) + { } + + void prisma(machine_config &config); + +protected: + virtual void machine_start() override; + +private: + // devices/pointers + required_device m_maincpu; + required_device m_board; + required_device m_display; + required_device m_dac; + required_ioport_array<3> m_inputs; + + u8 m_lcd_data = 0; + u8 m_lcd_address = 0; + u8 m_inp_mux = 0; + + void main_map(address_map &map); + + // I/O handlers + u8 p1_r(); + void p1_w(u8 data); + u8 p2_r(); + void p2_w(u8 data); + u8 p3_r(); + void p3_w(u8 data); + u8 p4_r(); + void p4_w(u8 data); + u8 p5_r(); + void p5_w(u8 data); + u8 p6_r(); + void p6_w(u8 data); + u8 p7_r(); + void p7_w(u8 data); +}; + +void prisma_state::machine_start() +{ + // register for savestates + save_item(NAME(m_lcd_data)); + save_item(NAME(m_lcd_address)); + save_item(NAME(m_inp_mux)); +} + + + +/******************************************************************************* + I/O +*******************************************************************************/ + +//[:maincpu:port1] ddr_w ff +//[:maincpu:port2] ddr_w ff +//[:maincpu:port3] ddr_w ff +//[:maincpu:port4] ddr_w 7f +//[:maincpu:port5] ddr_w 30 +//[:maincpu:port6] ddr_w ff +//[:maincpu:port7] ddr_w 00 + +u8 prisma_state::p1_r() +{ + //printf("r1 "); + return 0xff; +} + +void prisma_state::p1_w(u8 data) +{ + //printf("w1_%X ",data); + // P14: speaker out + m_dac->write(BIT(data, 4)); +} + +u8 prisma_state::p2_r() +{ + //printf("r2 "); + return 0xff; +} + +void prisma_state::p2_w(u8 data) +{ + //printf("w2_%X ",data); + // P20-P27: input mux + m_inp_mux = bitswap<8>(~data,7,6,5,4,0,3,1,2); +} + +u8 prisma_state::p3_r() +{ + //printf("r3 "); + return 0xff; +} + +void prisma_state::p3_w(u8 data) +{ + //printf("w3_%X ",data); + // P30-P37: LCD data + m_lcd_data = bitswap<8>(data,3,4,5,6,7,0,1,2); +} + +u8 prisma_state::p4_r() +{ + //printf("r4 "); + return 0xff; +} + +void prisma_state::p4_w(u8 data) +{ + //printf("w4_%X ",data); + // P40: LCD CS + // P41: LCD RD + // P42: LCD WR +} + +u8 prisma_state::p5_r() +{ + //printf("r5 "); + + u8 data = 0; + + // P50,P52: read buttons + for (int i = 0; i < 3; i++) + if (m_inp_mux & m_inputs[i]->read()) + data |= 1 << i; + + return ~data; +} + +void prisma_state::p5_w(u8 data) +{ + //printf("w5_%X ",data); +} + +u8 prisma_state::p6_r() +{ + //printf("r6 "); + return 0xff; +} + +void prisma_state::p6_w(u8 data) +{ + //printf("w6_%X ",data); + // P60-P66: LCD address + m_lcd_address = data & 0x7f; +} + +u8 prisma_state::p7_r() +{ + //printf("r7 "); + // P70-P77: read chessboard + return 0xff; +} + +void prisma_state::p7_w(u8 data) +{ + //printf("w7_%X ",data); +} + + + +/******************************************************************************* + Address Maps +*******************************************************************************/ + +void prisma_state::main_map(address_map &map) +{ + map(0x0000, 0x7fff).rom(); +} + + + +/******************************************************************************* + Input Ports +*******************************************************************************/ + +static INPUT_PORTS_START( prisma ) + PORT_START("IN.0") + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_1) + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_2) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_3) // k + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_4) // b + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_5) // swap + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_6) // ng + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7) + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_8) + + PORT_START("IN.1") + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Q) // nor + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_W) // col + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_E) // n + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_R) // p + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_T) // stop + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Y) // ana + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_U) // info + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_I) // fun + + PORT_START("IN.2") + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_A) // level + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_S) // play + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_D) // q + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_F) // r + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_G) // sound + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_H) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_J) // setup + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_K) // + +INPUT_PORTS_END + + + +/******************************************************************************* + Machine Configs +*******************************************************************************/ + +void prisma_state::prisma(machine_config &config) +{ + // basic machine hardware + H8325(config, m_maincpu, 20_MHz_XTAL / 2); + m_maincpu->set_addrmap(AS_PROGRAM, &prisma_state::main_map); + m_maincpu->read_port1().set(FUNC(prisma_state::p1_r)); + m_maincpu->write_port1().set(FUNC(prisma_state::p1_w)); + m_maincpu->read_port2().set(FUNC(prisma_state::p2_r)); + m_maincpu->write_port2().set(FUNC(prisma_state::p2_w)); + m_maincpu->read_port3().set(FUNC(prisma_state::p3_r)); + m_maincpu->write_port3().set(FUNC(prisma_state::p3_w)); + m_maincpu->read_port4().set(FUNC(prisma_state::p4_r)); + m_maincpu->write_port4().set(FUNC(prisma_state::p4_w)); + m_maincpu->read_port5().set(FUNC(prisma_state::p5_r)); + m_maincpu->write_port5().set(FUNC(prisma_state::p5_w)); + m_maincpu->read_port6().set(FUNC(prisma_state::p6_r)); + m_maincpu->write_port6().set(FUNC(prisma_state::p6_w)); + m_maincpu->read_port7().set(FUNC(prisma_state::p7_r)); + m_maincpu->write_port7().set(FUNC(prisma_state::p7_w)); + + SENSORBOARD(config, m_board).set_type(sensorboard_device::BUTTONS); + m_board->init_cb().set(m_board, FUNC(sensorboard_device::preset_chess)); + m_board->set_delay(attotime::from_msec(150)); + + // video hardware + PWM_DISPLAY(config, m_display).set_size(2+3, 16); + //config.set_default_layout(layout_saitek_prisma); + + // sound hardware + SPEAKER(config, "speaker").front_center(); + DAC_1BIT(config, m_dac).add_route(ALL_OUTPUTS, "speaker", 0.25); +} + + + +/******************************************************************************* + ROM Definitions +*******************************************************************************/ + +ROM_START( prisma ) + ROM_REGION( 0x8000, "maincpu", 0 ) + ROM_LOAD("90_saitek_86051150st9_3258l02p.u1", 0x0000, 0x8000, CRC(b6f8384f) SHA1(a4e8a4a45009c15bda1778512a87dea756aae6d8) ) +ROM_END + +} // anonymous namespace + + + +/******************************************************************************* + Drivers +*******************************************************************************/ + +// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY, FULLNAME, FLAGS +SYST( 1990, prisma, 0, 0, prisma, prisma, prisma_state, empty_init, "Saitek", "Kasparov Prisma", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE | MACHINE_CLICKABLE_ARTWORK ) -- cgit v1.2.3