From baf36685475ed7ac7a95a9231b4e4b85ee11b107 Mon Sep 17 00:00:00 2001 From: Olivier Galibert Date: Wed, 18 Jan 2023 19:19:05 +0100 Subject: m68000: Correct over, it was losing the offset --- src/devices/cpu/m68000/m68000-sdf.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sdfm.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sdp.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sdpm.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sif.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sifm.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sip.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000-sipm.cpp | 52 +++++++++++++++++----------------- src/devices/cpu/m68000/m68000.h | 5 ++-- src/devices/cpu/m68000/m68000gen.py | 6 ++-- 10 files changed, 213 insertions(+), 214 deletions(-) diff --git a/src/devices/cpu/m68000/m68000-sdf.cpp b/src/devices/cpu/m68000/m68000-sdf.cpp index 14945554d1c..159ee1ba03d 100644 --- a/src/devices/cpu/m68000/m68000-sdf.cpp +++ b/src/devices/cpu/m68000/m68000-sdf.cpp @@ -127124,7 +127124,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127528,7 +127528,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127936,7 +127936,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128346,7 +128346,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128772,7 +128772,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128917,7 +128917,7 @@ void m68000_device::divu_w_dais_dd_df() // 80f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -129236,7 +129236,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -129661,7 +129661,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130107,7 +130107,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130532,7 +130532,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130676,7 +130676,7 @@ void m68000_device::divu_w_dpci_dd_df() // 80fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -130995,7 +130995,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -131398,7 +131398,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -134513,7 +134513,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135052,7 +135052,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135595,7 +135595,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136140,7 +136140,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136701,7 +136701,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136923,7 +136923,7 @@ void m68000_device::divs_w_dais_dd_df() // 81f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -137300,7 +137300,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -137860,7 +137860,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -138441,7 +138441,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139001,7 +139001,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139222,7 +139222,7 @@ void m68000_device::divs_w_dpci_dd_df() // 81fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -139599,7 +139599,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -140137,7 +140137,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sdfm.cpp b/src/devices/cpu/m68000/m68000-sdfm.cpp index 5d99a213649..ada095c2b11 100644 --- a/src/devices/cpu/m68000/m68000-sdfm.cpp +++ b/src/devices/cpu/m68000/m68000-sdfm.cpp @@ -127124,7 +127124,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127528,7 +127528,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127936,7 +127936,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128346,7 +128346,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128772,7 +128772,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128917,7 +128917,7 @@ void m68000_device::divu_w_dais_dd_dfm() // 80f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -129236,7 +129236,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -129661,7 +129661,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130107,7 +130107,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130532,7 +130532,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130676,7 +130676,7 @@ void m68000_device::divu_w_dpci_dd_dfm() // 80fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -130995,7 +130995,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -131398,7 +131398,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -134513,7 +134513,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135052,7 +135052,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135595,7 +135595,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136140,7 +136140,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136701,7 +136701,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136923,7 +136923,7 @@ void m68000_device::divs_w_dais_dd_dfm() // 81f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -137300,7 +137300,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -137860,7 +137860,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -138441,7 +138441,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139001,7 +139001,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139222,7 +139222,7 @@ void m68000_device::divs_w_dpci_dd_dfm() // 81fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -139599,7 +139599,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -140137,7 +140137,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sdp.cpp b/src/devices/cpu/m68000/m68000-sdp.cpp index 6b9fd997732..f4de2588d93 100644 --- a/src/devices/cpu/m68000/m68000-sdp.cpp +++ b/src/devices/cpu/m68000/m68000-sdp.cpp @@ -144458,7 +144458,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -144898,7 +144898,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145342,7 +145342,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145788,7 +145788,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146253,7 +146253,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146406,7 +146406,7 @@ void m68000_device::divu_w_dais_dd_dp() // 80f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -146759,7 +146759,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147223,7 +147223,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147711,7 +147711,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148175,7 +148175,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148327,7 +148327,7 @@ void m68000_device::divu_w_dpci_dd_dp() // 80fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -148680,7 +148680,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -149119,7 +149119,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -152642,7 +152642,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153217,7 +153217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153796,7 +153796,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154377,7 +154377,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154977,7 +154977,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -155207,7 +155207,7 @@ void m68000_device::divs_w_dais_dd_dp() // 81f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -155618,7 +155618,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156217,7 +156217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156840,7 +156840,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157439,7 +157439,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157668,7 +157668,7 @@ void m68000_device::divs_w_dpci_dd_dp() // 81fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -158079,7 +158079,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -158653,7 +158653,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sdpm.cpp b/src/devices/cpu/m68000/m68000-sdpm.cpp index c82b25f30a7..5388556efe3 100644 --- a/src/devices/cpu/m68000/m68000-sdpm.cpp +++ b/src/devices/cpu/m68000/m68000-sdpm.cpp @@ -144458,7 +144458,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -144898,7 +144898,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145342,7 +145342,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145788,7 +145788,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146253,7 +146253,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146406,7 +146406,7 @@ void m68000_device::divu_w_dais_dd_dpm() // 80f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -146759,7 +146759,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147223,7 +147223,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147711,7 +147711,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148175,7 +148175,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148327,7 +148327,7 @@ void m68000_device::divu_w_dpci_dd_dpm() // 80fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -148680,7 +148680,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -149119,7 +149119,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -152642,7 +152642,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153217,7 +153217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153796,7 +153796,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154377,7 +154377,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154977,7 +154977,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -155207,7 +155207,7 @@ void m68000_device::divs_w_dais_dd_dpm() // 81f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -155618,7 +155618,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156217,7 +156217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156840,7 +156840,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157439,7 +157439,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157668,7 +157668,7 @@ void m68000_device::divs_w_dpci_dd_dpm() // 81fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -158079,7 +158079,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -158653,7 +158653,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sif.cpp b/src/devices/cpu/m68000/m68000-sif.cpp index 78c8305ffeb..e757ead8f1f 100644 --- a/src/devices/cpu/m68000/m68000-sif.cpp +++ b/src/devices/cpu/m68000/m68000-sif.cpp @@ -127124,7 +127124,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127528,7 +127528,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127936,7 +127936,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128346,7 +128346,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128772,7 +128772,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128917,7 +128917,7 @@ void m68000_device::divu_w_dais_dd_if() // 80f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -129236,7 +129236,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -129661,7 +129661,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130107,7 +130107,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130532,7 +130532,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130676,7 +130676,7 @@ void m68000_device::divu_w_dpci_dd_if() // 80fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -130995,7 +130995,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -131398,7 +131398,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -134513,7 +134513,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135052,7 +135052,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135595,7 +135595,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136140,7 +136140,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136701,7 +136701,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136923,7 +136923,7 @@ void m68000_device::divs_w_dais_dd_if() // 81f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -137300,7 +137300,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -137860,7 +137860,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -138441,7 +138441,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139001,7 +139001,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139222,7 +139222,7 @@ void m68000_device::divs_w_dpci_dd_if() // 81fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -139599,7 +139599,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -140137,7 +140137,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sifm.cpp b/src/devices/cpu/m68000/m68000-sifm.cpp index a83b26b0388..227f287ae64 100644 --- a/src/devices/cpu/m68000/m68000-sifm.cpp +++ b/src/devices/cpu/m68000/m68000-sifm.cpp @@ -127124,7 +127124,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127528,7 +127528,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -127936,7 +127936,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128346,7 +128346,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128772,7 +128772,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -128917,7 +128917,7 @@ void m68000_device::divu_w_dais_dd_ifm() // 80f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -129236,7 +129236,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -129661,7 +129661,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130107,7 +130107,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130532,7 +130532,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -130676,7 +130676,7 @@ void m68000_device::divu_w_dpci_dd_ifm() // 80fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -130995,7 +130995,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -131398,7 +131398,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -134513,7 +134513,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135052,7 +135052,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -135595,7 +135595,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136140,7 +136140,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136701,7 +136701,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -136923,7 +136923,7 @@ void m68000_device::divs_w_dais_dd_ifm() // 81f0 f1f8 int ry = map_sp((m_irdi & 7) | 8); // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -137300,7 +137300,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -137860,7 +137860,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -138441,7 +138441,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139001,7 +139001,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -139222,7 +139222,7 @@ void m68000_device::divs_w_dpci_dd_ifm() // 81fb f1ff int rx = (m_irdi >> 9) & 7; // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -139599,7 +139599,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -140137,7 +140137,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sip.cpp b/src/devices/cpu/m68000/m68000-sip.cpp index d22d59b65bc..8be207b3208 100644 --- a/src/devices/cpu/m68000/m68000-sip.cpp +++ b/src/devices/cpu/m68000/m68000-sip.cpp @@ -144458,7 +144458,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -144898,7 +144898,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145342,7 +145342,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145788,7 +145788,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146253,7 +146253,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146406,7 +146406,7 @@ void m68000_device::divu_w_dais_dd_ip() // 80f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -146759,7 +146759,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147223,7 +147223,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147711,7 +147711,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148175,7 +148175,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148327,7 +148327,7 @@ void m68000_device::divu_w_dpci_dd_ip() // 80fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -148680,7 +148680,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -149119,7 +149119,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -152642,7 +152642,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153217,7 +153217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153796,7 +153796,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154377,7 +154377,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154977,7 +154977,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -155207,7 +155207,7 @@ void m68000_device::divs_w_dais_dd_ip() // 81f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -155618,7 +155618,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156217,7 +156217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156840,7 +156840,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157439,7 +157439,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157668,7 +157668,7 @@ void m68000_device::divs_w_dpci_dd_ip() // 81fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -158079,7 +158079,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -158653,7 +158653,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000-sipm.cpp b/src/devices/cpu/m68000/m68000-sipm.cpp index 9d81d5ec0b9..0a17c6ac1ca 100644 --- a/src/devices/cpu/m68000/m68000-sipm.cpp +++ b/src/devices/cpu/m68000/m68000-sipm.cpp @@ -144458,7 +144458,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -144898,7 +144898,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145342,7 +145342,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -145788,7 +145788,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146253,7 +146253,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -146406,7 +146406,7 @@ void m68000_device::divu_w_dais_dd_ipm() // 80f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -146759,7 +146759,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147223,7 +147223,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -147711,7 +147711,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148175,7 +148175,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -148327,7 +148327,7 @@ void m68000_device::divu_w_dpci_dd_ipm() // 80fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -148680,7 +148680,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -149119,7 +149119,7 @@ dvum4: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -152642,7 +152642,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153217,7 +153217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -153796,7 +153796,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154377,7 +154377,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -154977,7 +154977,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -155207,7 +155207,7 @@ void m68000_device::divs_w_dais_dd_ipm() // 81f0 f1f8 case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -155618,7 +155618,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156217,7 +156217,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -156840,7 +156840,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157439,7 +157439,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -157668,7 +157668,7 @@ void m68000_device::divs_w_dpci_dd_ipm() // 81fb f1ff case 0: // 1e3 aixl0 // alu r=1 c=5 m=..... i=.l.d... ALU.over a=R.dbin:m_dbin d=0 - alu_over(); + alu_over(m_dbin); m_icount -= 2; // 3e2 aixl1 m_aob = m_au; @@ -158079,7 +158079,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; @@ -158653,7 +158653,7 @@ dvuma: m_irc = m_edb; m_dbin = m_edb; // alu r=1 c=5 m=.nzvc i=.l.d.i. ALU.over a=none d=none - alu_over(); + alu_over(0x0000); sr_nzvc(); set_ftu_const(); m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird]; diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h index 808e704201f..2d02c14e41a 100644 --- a/src/devices/cpu/m68000/m68000.h +++ b/src/devices/cpu/m68000/m68000.h @@ -559,9 +559,10 @@ protected: m_aluo = r >> 16; } - inline void alu_over() { + // ext with fixed flags result + inline void alu_over(u16 a) { m_isr = SR_V|SR_N; - m_aluo = 0; + m_aluo = s8(a); } inline void alu_asl(u16 a) { diff --git a/src/devices/cpu/m68000/m68000gen.py b/src/devices/cpu/m68000/m68000gen.py index 3f1fd1e9ffd..6fb6bed066d 100755 --- a/src/devices/cpu/m68000/m68000gen.py +++ b/src/devices/cpu/m68000/m68000gen.py @@ -1708,7 +1708,7 @@ def generate_base_code_for_microcode(ir, irmask, madr, tvn, group01): "alub" if alu_actrl else "%s:%s" % (abd, regname[abd]) if abd != None else "none", \ ("%s:%s" % (dbd, regname[dbd]) if dbd != None else "none") if alu_dctrl == 0 else "0" if alu_dctrl == 2 else "-1" if alu_dctrl == 3 else "?")]) if (alu_actrl or abd != None or alu_op == ALU.over) and alu_single_param[alu_op]: - code_to_sort.append(["alu", alu_op, alu_mask, alu_info, None if alu_op == ALU.over else R.alub if alu_actrl else abd]) + code_to_sort.append(["alu", alu_op, alu_mask, alu_info, (abd if abd else ["c", 0]) if alu_op == ALU.over else R.alub if alu_actrl else abd]) elif (alu_actrl or abd != None) and (alu_dctrl == 2 or alu_dctrl == 3 or (alu_dctrl == 0 and dbd != None)): code_to_sort.append(["alu", alu_op, alu_mask, alu_info, R.alub if alu_actrl else abd, dbd if alu_dctrl == 0 else ["c", 0] if alu_dctrl == 2 else ["c", 0xffff]]) elif alu_op == ALU.and_ and alu_dctrl == 2: @@ -2184,9 +2184,7 @@ def generate_source_from_code(code, gen_mode): source.append("\tset_8xh(%s, %s);" % (regname[ci[1]], make_expression(ci[2:]))) elif ci[0] == "alu": aname, aflags = aluname(ci[1], ci[2], ci[3]) - if ci[1] == ALU.over: - source.append("\t%s();" % (aname)) - elif len(ci) == 5: + if len(ci) == 5: source.append("\t%s(%s);" % (aname, make_expression(ci[4]))) else: sec = make_expression(ci[5]) -- cgit v1.2.3