From b84318b506df3c5e3b37b3cb48acc516d7f6f805 Mon Sep 17 00:00:00 2001 From: angelosa Date: Tue, 20 Jun 2023 21:23:03 +0200 Subject: machine/pc87306.cpp: add keyboard enable mechanism --- src/devices/machine/pc87306.cpp | 165 ++++++++++++++++++++++++++++++++++++---- src/devices/machine/pc87306.h | 16 +++- src/mame/misc/odyssey.cpp | 7 +- 3 files changed, 171 insertions(+), 17 deletions(-) diff --git a/src/devices/machine/pc87306.cpp b/src/devices/machine/pc87306.cpp index c72717e30b9..6150023fe66 100644 --- a/src/devices/machine/pc87306.cpp +++ b/src/devices/machine/pc87306.cpp @@ -14,10 +14,14 @@ TODO: //#include "machine/ds128x.h" #include "machine/pc87306.h" -#define VERBOSE (LOG_GENERAL) +#define LOG_WARN (1U << 1) // Show warnings + +#define VERBOSE (LOG_GENERAL | LOG_WARN) //#define LOG_OUTPUT_FUNC osd_printf_info #include "logmacro.h" +#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__) + DEFINE_DEVICE_TYPE(PC87306, pc87306_device, "pc87306", "National Semiconductor PC87306 Super I/O Enhanced Sidewinder Lite") pc87306_device::pc87306_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) @@ -49,6 +53,8 @@ void pc87306_device::device_start() //m_isa->set_dma_channel(1, this, true); //m_isa->set_dma_channel(2, this, true); //m_isa->set_dma_channel(3, this, true); + // TODO: CFG0 (RTC) + MR (KBD) + m_krr = 8 | 1; remap(AS_IO, 0, 0x400); } @@ -66,18 +72,18 @@ device_memory_interface::space_config_vector pc87306_device::memory_space_config void pc87306_device::device_add_mconfig(machine_config &config) { - // doc doesn't explicitly mention this being at 8, assume from intialization + // TODO: can bank thru bit 5 of KRR DS12885(config, m_rtc, 32.768_kHz_XTAL); // m_rtc->irq().set(FUNC(pc87306_device::irq_rtc_w)); m_rtc->set_century_index(0x32); KBDC8042(config, m_kbdc); m_kbdc->set_keyboard_type(kbdc8042_device::KBDC8042_PS2); - m_kbdc->set_interrupt_type(kbdc8042_device::KBDC8042_DOUBLE); -// m_kbdc->input_buffer_full_callback().set(FUNC(pc87306_device::irq_keyboard_w)); -// m_kbdc->input_buffer_full_mouse_callback().set(FUNC(pc87306_device::irq_mouse_w)); -// m_kbdc->system_reset_callback().set(FUNC(pc87306_device::kbdp20_gp20_reset_w)); -// m_kbdc->gate_a20_callback().set(FUNC(pc87306_device::kbdp21_gp25_gatea20_w)); + m_kbdc->set_interrupt_type(kbdc8042_device::KBDC8042_SINGLE); + m_kbdc->input_buffer_full_callback().set(FUNC(pc87306_device::irq_keyboard_w)); + m_kbdc->input_buffer_full_mouse_callback().set(FUNC(pc87306_device::irq_mouse_w)); + m_kbdc->system_reset_callback().set(FUNC(pc87306_device::kbdp20_gp20_reset_w)); + m_kbdc->gate_a20_callback().set(FUNC(pc87306_device::kbdp21_gp25_gatea20_w)); } void pc87306_device::remap(int space_id, offs_t start, offs_t end) @@ -88,11 +94,14 @@ void pc87306_device::remap(int space_id, offs_t start, offs_t end) u16 superio_base = 0x0398; m_isa->install_device(superio_base, superio_base + 1, read8sm_delegate(*this, FUNC(pc87306_device::read)), write8sm_delegate(*this, FUNC(pc87306_device::write))); + if (BIT(m_krr, 0)) + { + m_isa->install_device(0x60, 0x60, read8sm_delegate(*m_kbdc, FUNC(kbdc8042_device::data_r)), write8sm_delegate(*m_kbdc, FUNC(kbdc8042_device::data_w))); + m_isa->install_device(0x64, 0x64, read8sm_delegate(*this, FUNC(pc87306_device::keybc_status_r)), write8sm_delegate(*this, FUNC(pc87306_device::keybc_command_w))); + } - m_isa->install_device(0x60, 0x60, read8sm_delegate(*m_kbdc, FUNC(kbdc8042_device::data_r)), write8sm_delegate(*m_kbdc, FUNC(kbdc8042_device::data_w))); - m_isa->install_device(0x64, 0x64, read8sm_delegate(*this, FUNC(pc87306_device::keybc_status_r)), write8sm_delegate(*this, FUNC(pc87306_device::keybc_command_w))); - - m_isa->install_device(0x70, 0x71, read8sm_delegate(*m_rtc, FUNC(ds12885_device::read)), write8sm_delegate(*m_rtc, FUNC(ds12885_device::write))); + if (BIT(m_krr, 3)) + m_isa->install_device(0x70, 0x71, read8sm_delegate(*m_rtc, FUNC(ds12885_device::read)), write8sm_delegate(*m_rtc, FUNC(ds12885_device::write))); } } @@ -119,16 +128,67 @@ void pc87306_device::write(offs_t offset, u8 data) } else { - //remap(AS_IO, 0, 0x400); + // TODO: two writes, first one just unlocks? space().write_byte(m_index, data); } } void pc87306_device::config_map(address_map &map) { - map(0x00, 0xff).unmaprw(); +// map(0x00, 0x00) FER Function Enable Register +// map(0x01, 0x01) FAR Function Address Register +// map(0x02, 0x02) PTR Power and Test Register +// map(0x03, 0x03) FCR Function Control Register +// map(0x04, 0x04) PCR Printer Control Register + map(0x05, 0x05).rw(FUNC(pc87306_device::krr_r), FUNC(pc87306_device::krr_w)); +// map(0x06, 0x06) PMC Power Management Control Register +// map(0x07, 0x07) TUP Tape, UART and Parallel Port Configuration Register + // SID Super I/O Identification Register + // bits 7-3 -> 01110 TL/C/12379-27 + // bits 2-0 -> + map(0x08, 0x08).lr8( + NAME([] (offs_t offset) { return 0x70; }) + ); +// map(0x09, 0x09) ASC Advanced Super I/O Configuration Register +// map(0x0a, 0x0a) CS0LA Chip Select 0 Low Address +// map(0x0b, 0x0b) CS0CF Chip Select 0 Configuration Address +// map(0x0c, 0x0c) CS1LA Chip Select 1 Low Address +// map(0x0d, 0x0d) CS1CF Chip Select 1 Configuration Address +// map(0x0e, 0x0e) IRC InfraRed Configuration Register +// map(0x0f, 0x0f) GPBA General Purpose I/O Port Base Address +// map(0x10, 0x10) CS0HA Chip Select 0 High Address +// map(0x11, 0x11) CS1HA Chip Select 1 High Address +// map(0x12, 0x12) SCF0 Super I/O Configuration Register 0 +// map(0x18, 0x18) SCF1 Super I/O Configuration Register 1 +// map(0x19, 0x19) LPTBA LPT Base Address + +// map(0x1b, 0x1b) PNP0 Plug and Play Configuration 0 Register +// map(0x1c, 0x1c) PNP1 Plug and Play Configuration 1 Register +} + +// [0x05] KRR KBC and RTC Control Register +/* + * x--- ---- KBC clock source select (0) X1 clock (1) SYSCLK + * --x- ---- RAMSREL RTC bank select + * ---- x--- RTC enable bit + * ---- -1-- must be 1 for KBC to work + * ---- --x- KBC speed control (0) X1 / 3 (1) X1 / 2, ignored when SYSCLK selected + * ---- ---x KBC Enable bit + * + */ +u8 pc87306_device::krr_r(offs_t offset) +{ + return m_krr; } +void pc87306_device::krr_w(offs_t offset, u8 data) +{ + m_krr = data; + LOG("krr %02x\n", data); + if (data & 0x20) + LOGWARN("RAMSREL active\n"); + remap(AS_IO, 0, 0x400); +} u8 pc87306_device::keybc_status_r(offs_t offset) { @@ -139,3 +199,82 @@ void pc87306_device::keybc_command_w(offs_t offset, u8 data) { m_kbdc->data_w(4, data); } + +/* + * KBC lines + */ +// Unlike other Super I/Os this doesn't seem to have irq line relocation + +void pc87306_device::kbdp21_gp25_gatea20_w(int state) +{ + if (!BIT(m_krr, 0)) + return; + m_gp25_gatea20_callback(state); +} + +void pc87306_device::kbdp20_gp20_reset_w(int state) +{ + if (!BIT(m_krr, 0)) + return; + m_gp20_reset_callback(state); +} + +void pc87306_device::irq_keyboard_w(int state) +{ + if (!BIT(m_krr, 0)) + return; + request_irq(1, state ? ASSERT_LINE : CLEAR_LINE); +} + +void pc87306_device::irq_mouse_w(int state) +{ + if (!BIT(m_krr, 0)) + return; + request_irq(12, state ? ASSERT_LINE : CLEAR_LINE); +} + +void pc87306_device::request_irq(int irq, int state) +{ + switch (irq) + { + case 1: + m_irq1_callback(state); + break; + case 3: + m_isa->irq3_w(state); + break; + case 4: + m_isa->irq4_w(state); + break; + case 5: + m_isa->irq5_w(state); + break; + case 6: + m_isa->irq6_w(state); + break; + case 7: + m_isa->irq7_w(state); + break; + case 8: + m_irq8_callback(state); + break; + case 9: + m_irq9_callback(state); + break; + case 10: + m_isa->irq10_w(state); + break; + case 11: + m_isa->irq11_w(state); + break; + case 12: + m_isa->irq12_w(state); + break; + case 14: + m_isa->irq14_w(state); + break; + case 15: + m_isa->irq15_w(state); + break; + } +} diff --git a/src/devices/machine/pc87306.h b/src/devices/machine/pc87306.h index f0f4515c916..a9c4aeb9c59 100644 --- a/src/devices/machine/pc87306.h +++ b/src/devices/machine/pc87306.h @@ -58,17 +58,29 @@ private: // devcb_write_line m_ndtr2_callback; // devcb_write_line m_nrts2_callback; - void config_map(address_map &map); + void request_irq(int irq, int state); u8 read(offs_t offset); void write(offs_t offset, u8 data); + void config_map(address_map &map); + u8 keybc_status_r(offs_t offset); void keybc_command_w(offs_t offset, u8 data); + void kbdp21_gp25_gatea20_w(int state); + void kbdp20_gp20_reset_w(int state); + + void irq_keyboard_w(int state); + void irq_mouse_w(int state); + + u8 krr_r(offs_t offset); + void krr_w(offs_t offset, u8 data); + u8 m_index = 0; - u8 m_locked_state; + u8 m_locked_state = 2; + u8 m_krr = 0; }; DECLARE_DEVICE_TYPE(PC87306, pc87306_device); diff --git a/src/mame/misc/odyssey.cpp b/src/mame/misc/odyssey.cpp index b7cc66fc1c1..4e95fb1786e 100644 --- a/src/mame/misc/odyssey.cpp +++ b/src/mame/misc/odyssey.cpp @@ -129,9 +129,9 @@ void odyssey_state::national_superio_config(device_t *device) //fdc.set_sysopt_pin(1); fdc.gp20_reset().set_inputline(":maincpu", INPUT_LINE_RESET); fdc.gp25_gatea20().set_inputline(":maincpu", INPUT_LINE_A20); -#if 0 fdc.irq1().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq1_w)); fdc.irq8().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq8n_w)); +#if 0 fdc.txd1().set(":serport0", FUNC(rs232_port_device::write_txd)); fdc.ndtr1().set(":serport0", FUNC(rs232_port_device::write_dtr)); fdc.nrts1().set(":serport0", FUNC(rs232_port_device::write_rts)); @@ -159,7 +159,9 @@ static void isa_com(device_slot_interface &device) // PCI config space is trusted by Intel TC430HX "Technical Product Specification" void odyssey_state::odyssey(machine_config &config) { - PENTIUM(config, m_maincpu, 133'000'000); // a Celeron at 1.70 GHz on the MB I checked. <- doesn't match being a Triton/Triton-II ... -AS + // a Celeron at 1.70 GHz on the MB I checked. <- doesn't match being a Triton/Triton-II ... -AS + // It also fails refresh check if it's 133 MHz + PENTIUM(config, m_maincpu, 66'000'000); m_maincpu->set_addrmap(AS_PROGRAM, &odyssey_state::odyssey_map); m_maincpu->set_addrmap(AS_IO, &odyssey_state::odyssey_io); m_maincpu->set_irq_acknowledge_callback("pci:07.0:pic8259_master", FUNC(pic8259_device::inta_cb)); @@ -180,6 +182,7 @@ void odyssey_state::odyssey(machine_config &config) // TODO: 82371FB USB at 07.2 // On-board Virge or Virge/DX + // TODO: actually a S3 Vision 968 VIRGE_PCI(config, "pci:08.0", 0); // pci:0d.0 (J4E1) PCI expansion slot 1 -- cgit v1.2.3