From b5c4ea75e69c733164301f1f72a7eb7f0524cd1a Mon Sep 17 00:00:00 2001 From: David Haywood <28625134+DavidHaywood@users.noreply.github.com> Date: Wed, 14 Jun 2023 20:26:06 +0100 Subject: misc/anes.cpp: Got it to boot and added preliminary video and inputs. (#11324) [Luca Elia, David Haywood] * Implemented ROM banking. * Added preliminary blitter and palette support. * Added preliminary inputs. --- src/mame/misc/anes.cpp | 609 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 526 insertions(+), 83 deletions(-) diff --git a/src/mame/misc/anes.cpp b/src/mame/misc/anes.cpp index 44570b61290..538941f6208 100644 --- a/src/mame/misc/anes.cpp +++ b/src/mame/misc/anes.cpp @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:Ivan Vangelista +// copyright-holders:Ivan Vangelista, Luca Elia, David Haywood /* Sanma - San-nin Uchi Mahjong (Japan) by ANES @@ -9,7 +9,7 @@ TODO: - ROM banking; - blitter, 8bpp with hardcoded palette & writes to ROM area!? - inputs; -- dip sheets are available for sanma. +- DIP sheets are available for sanma. - 1x Z0840008PSC Z80 CPU - 1x 16.000 XTAL near the Z80 @@ -38,8 +38,13 @@ namespace { class anes_state : public driver_device { public: - anes_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) + anes_state(const machine_config &mconfig, device_type type, const char *tag) : + driver_device(mconfig, type, tag), + m_maincpu(*this, "maincpu"), + m_palette(*this, "palette"), + m_rombank(*this, "rombank"), + m_blitrom(*this, "blitter"), + m_key(*this, "KEY1.%u", 0U) { } @@ -47,48 +52,361 @@ public: protected: virtual void machine_start() override; + virtual void video_start() override; private: void vram_offset_w(offs_t offset, uint8_t data); - void blit_trigger_w(uint8_t data); + + required_device m_maincpu; + required_device m_palette; + + required_memory_bank m_rombank; + required_region_ptr m_blitrom; + + required_ioport_array<5> m_key; + + uint8_t m_inp_matrix; + uint8_t m_bank; + uint8_t m_bank_delay; + + bitmap_ind16 m_bitmap[2]; + uint8_t m_blit[16]; + uint16_t m_blit_addr[2]; + uint8_t m_blit_val[2]; + + uint8_t m_palette_enable; + uint8_t m_palette_offset; + uint8_t m_palette_offset_msb; + uint8_t m_palette_active_bank; + uint8_t m_palette_active_bank_alt; + uint8_t m_palette_data_lsb[0x2000]; + uint8_t m_palette_data_msb[0x2000]; + + void do_blit_draw(bitmap_ind16 &bitmap, int &addr, int sx, int sy, int sw, int sh, int x, int y, bool flipx, bool flipy); + void do_blit(); + void blit_w(offs_t offset, uint8_t data); + void blit_rom_w(offs_t offset, uint8_t data); + uint8_t blit_status_r(); + void blit_unk_w(uint8_t data); + + void rombank_w(uint8_t data); + void matrix_w(uint8_t data); + uint8_t key_r(offs_t offset); + uint8_t m1_rom_r(offs_t offset); + + void palette_enable_w(uint8_t data); + void palette_offset_w(uint8_t data); + void palette_offset_msb_w(uint8_t data); + void palette_active_bank_w(uint8_t data); + uint8_t palette_data_lsb_r(); + uint8_t palette_data_msb_r(); + void palette_data_lsb_w(uint8_t data); + void palette_data_msb_w(uint8_t data); + void set_color(int offset); uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); void io_map(address_map &map); void prg_map(address_map &map); + void opcodes_map(address_map &map); - uint8_t m_vram_offset[3]; + INTERRUPT_GEN_MEMBER(interrupt); }; uint32_t anes_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) { + for (int y = cliprect.min_y; y <= cliprect.max_y; y++) + { + uint16_t const *const src = m_bitmap[0].pix(y); + uint16_t const *const src2 = m_bitmap[1].pix(y); + uint16_t *const dst = &bitmap.pix(y); + + for (int x = cliprect.min_x; x <= cliprect.max_x; x++) + { + if (src2[x]) + dst[x] = src2[x] + (m_palette_active_bank * 0x100); + else + dst[x] = src[x] + (m_palette_active_bank_alt * 0x100); + } + } + return 0; } -void anes_state::vram_offset_w(offs_t offset, uint8_t data) +/* + blitter operation is: + checks for bit 4 to be high in port $16 + writes either 0 or 3 to port $04 + writes a 0 to port $00 + writes an offset to ports $0c / $0d / $0e + writes 1 to port $0b, writes to program space, writes 2 to port $0b, writes to program space + writes a mode to port $0b, writes to trigger port $0a + */ + +void anes_state::do_blit_draw(bitmap_ind16 &bitmap, int &addr, int sx, int sy, int sw, int sh, int x, int y, bool flipx, bool flipy) +{ + int drawx, drawy; + + if (!flipy) + drawy = ((sy + y) & 0x1ff); + else + drawy = ((sy + (sh - 1) - y) & 0x1ff); + + if (!flipx) + drawx = ((sx + x) & 0x1ff); + else + drawx = ((sx + (sw - 1) - x) & 0x1ff); + + int pen = m_blitrom[(addr) & (m_blitrom.bytes() - 1)]; + if (!(m_blit[0x0b] & 0x10)) + addr++; + + if (pen != 0xff) + { + // if (pen != 0x00) + bitmap.pix(drawy, drawx) = pen; + } + else + { + bitmap.pix(drawy, drawx) = 0x00; + } +} + +void anes_state::do_blit() +{ + int src = (m_blit[0x0c] << 16) + (m_blit[0x0d] << 8) + m_blit[0x0e]; + + logerror("%s: src %06x, xpos %04X width %02X, ypos %04X height %02X | %02X %02X %02X %02X %02X %02X %02X | %02X %02X | %02X\n", + machine().describe_context(), + src, m_blit_addr[0], m_blit_val[0], m_blit_addr[1], m_blit_val[1], + m_blit[0x00], m_blit[0x01], m_blit[0x02], m_blit[0x03], m_blit[0x04], m_blit[0x05], m_blit[0x06], + m_blit[0x0a], m_blit[0x0b], + m_blit[0x0f]); + + bool flipx = m_blit[0x04] & 0x01; + bool flipy = m_blit[0x04] & 0x02; + + bitmap_ind16 &bitmap = m_bitmap[(m_blit[0x0b] & 0x04) ? 1 : 0]; + + int sx = m_blit_addr[0]; + int sy = m_blit_val[0]; + int16_t sw = m_blit_addr[1] - m_blit_addr[0] + 1; + int16_t sh = m_blit_val[1] - m_blit_val[0] + 1; + + if (m_blit[0x0b] & 0x40) // flipx x/y scan order on output? + { + for (int x = 0; x < sw; x++) + { + for (int y = 0; y < sh; y++) + { + do_blit_draw(bitmap, src, sx, sy, sw, sh, x, y, flipx, flipy); + } + } + } + else + { + for (int y = 0; y < sh; y++) + { + for (int x = 0; x < sw; x++) + { + do_blit_draw(bitmap, src, sx, sy, sw, sh, x, y, flipx, flipy); + } + } + } +} + +void anes_state::rombank_w(uint8_t data) +{ + if (data & (~0x07)) + logerror("%s: Unknown ROM bank bit written %02X\n", machine().describe_context(), data); + + m_bank = data & 0x07; + + // the bank change must happen AFTER the next instruction, be it a jmp or a ret + m_bank_delay = 2; +} + +void anes_state::blit_w(offs_t offset, uint8_t data) +{ + m_blit[offset] = data; + if (offset == 0x0a) + do_blit(); +} + +void anes_state::blit_rom_w(offs_t offset, uint8_t data) +{ + uint8_t which = m_blit[0x0b]; +// logerror("%s: blit ROM written %02X (%04X <- %02X)\n", machine().describe_context(), which, offset, data); + if (which == 1) + { + m_blit_addr[0] = offset; + m_blit_val[0] = data; + } + else if (which == 2) + { + m_blit_addr[1] = offset; + m_blit_val[1] = data; + } + else + logerror("%s: Unknown blit ROM which %02X\n", machine().describe_context(), which); +} + + + +uint8_t anes_state::blit_status_r() +{ + // bits 0-3 = ? + // bit 4 = busy + return 0x00; +} + +void anes_state::matrix_w(uint8_t data) +{ + m_inp_matrix = data; + if (m_inp_matrix & (~0x1f)) + logerror("%s: Unknown mux bit written %02X\n", machine().describe_context(), data); +} + +uint8_t anes_state::key_r(offs_t offset) +{ + uint8_t data = 0xff; + + // read key matrix + for (int i = 0; i < 5; i++) + if (!BIT(m_inp_matrix, i)) + data &= m_key[i]->read(); + + return data; +} + +uint8_t anes_state::m1_rom_r(offs_t offset) +{ + if (!machine().side_effects_disabled() && m_bank_delay) + { + if (--m_bank_delay == 0) + m_rombank->set_entry(m_bank); + } + + return m_maincpu->space(AS_PROGRAM).read_byte(offset); +} + +void anes_state::palette_enable_w(uint8_t data) +{ + m_palette_enable = data; +} + +void anes_state::set_color(int offset) +{ + uint16_t dat = (m_palette_data_msb[offset] << 8) | m_palette_data_lsb[offset]; + m_palette->set_pen_color(offset, rgb_t(pal5bit(dat >> 0), pal5bit(dat >> 5), pal5bit(dat >> 10))); +} + +void anes_state::palette_offset_w(uint8_t data) +{ + if (m_palette_enable != 0x01) + { + logerror("write to palette_offset_w when not enabled %02x (enable %02x)\n", data, m_palette_enable); + } + else + { + m_palette_offset = data; + } +} + +void anes_state::palette_offset_msb_w(uint8_t data) +{ + if (m_palette_enable != 0x01) + { + //logerror("%s: write to palette_offset_msb_w when not enabled %02x (enable %02x)\n", machine().describe_context(), data, m_palette_enable); + m_palette_active_bank_alt = data; + } + else + { + m_palette_offset_msb = data; + } +} + +void anes_state::palette_active_bank_w(uint8_t data) +{ + m_palette_active_bank = data & 0x1f; +} + +uint8_t anes_state::palette_data_lsb_r() +{ + if (m_palette_enable != 0x01) + { + logerror("read from palette_data_lsb_r when not enabled\n"); + } + else + { + int offs = (m_palette_offset + (m_palette_offset_msb << 8)) & 0x1fff; + return m_palette_data_lsb[offs]; + } + return 0x00; +} + +uint8_t anes_state::palette_data_msb_r() +{ + if (m_palette_enable != 0x01) + { + logerror("read from palette_data_msb_r when not enabled\n"); + } + else + { + int offs = (m_palette_offset + (m_palette_offset_msb << 8)) & 0x1fff; + return m_palette_data_msb[offs]; + } + return 0x00; +} + + + +void anes_state::palette_data_lsb_w(uint8_t data) +{ + if (m_palette_enable != 0x01) + { + logerror("write to palette_data_lsb_w when not enabled %02x\n", data); + } + else + { + int offs = (m_palette_offset + (m_palette_offset_msb << 8)) & 0x1fff; + m_palette_data_lsb[offs] = data; + set_color(offs); + } +} + +void anes_state::palette_data_msb_w(uint8_t data) { - m_vram_offset[offset] = data; + if (m_palette_enable != 0x01) + { + logerror("write to palette_data_msb_w when not enabled %02x\n", data); + } + else + { + int offs = (m_palette_offset + (m_palette_offset_msb << 8)) & 0x1fff; + m_palette_data_msb[offs] = data; + set_color(offs); + } } -void anes_state::blit_trigger_w(uint8_t data) +void anes_state::blit_unk_w(uint8_t data) { - /* - operation is: - checks for bit 4 to be high in port $16 - writes either 0 or 3 to port $04 - writes a 0 to port $00 - writes an offset to ports $0c / $0d / $0e - writes 1 to port $0b, writes to program space, writes 2 to port $0b, writes to program space - writes a mode to port $0b, writes to trigger port $0a - */ + if (data != 0x1f) + logerror("write to blit_unk_w %02x\n", data); +} - //printf("%02x%02x%02x\n",m_vram_offset[0],m_vram_offset[1],m_vram_offset[2]); +void anes_state::opcodes_map(address_map &map) +{ + map(0x0000, 0xffff).r(FUNC(anes_state::m1_rom_r)); } void anes_state::prg_map(address_map &map) { - map(0x0000, 0xefff).rom(); - map(0xf000, 0xffff).ram(); + map(0x0000, 0x1fff).rom(); + map(0x2000, 0xefff).bankr(m_rombank); + map(0x0000, 0x01ff).w(FUNC(anes_state::blit_rom_w)); + map(0x1000, 0x11ff).w(FUNC(anes_state::blit_rom_w)); // does writing with 0x1000 set on the address have a different meaning? + map(0xf000, 0xffff).ram(); // there might be a hole at 0xf800 - 0xf8ff } void anes_state::io_map(address_map &map) @@ -96,91 +414,216 @@ void anes_state::io_map(address_map &map) map.global_mask(0xff); map.unmap_value_high(); - map(0x07, 0x07).nopw(); // mux write + map(0x00, 0x0f).w(FUNC(anes_state::blit_w)); + + map(0x07, 0x07).w(FUNC(anes_state::matrix_w)); map(0x08, 0x09).w("ym", FUNC(ym2413_device::write)); - map(0x0a, 0x0a).w(FUNC(anes_state::blit_trigger_w)); -// map(0x0b, 0x0b).w(FUNC(anes_state::blit_mode_w)); - map(0x0c, 0x0e).w(FUNC(anes_state::vram_offset_w)); - map(0x11, 0x11).portr("DSW1"); - map(0x12, 0x12).portr("DSW2"); - map(0x13, 0x13).portr("DSW3"); - map(0x14, 0x15).nopr(); // mux read - map(0x16, 0x16).portr("IN0").nopw(); -// map(0xfe, 0xfe) banking? unknown ROM range + + map(0x10, 0x10).portr("SW1"); + map(0x11, 0x11).portr("SW2"); + map(0x12, 0x12).portr("SW3"); + map(0x13, 0x13).portr("SW4"); + map(0x14, 0x14).r(FUNC(anes_state::key_r)); + map(0x15, 0x15).portr("COIN"); + map(0x16, 0x16).rw(FUNC(anes_state::blit_status_r), FUNC(anes_state::blit_unk_w)); + map(0x50, 0x50).w(FUNC(anes_state::palette_enable_w)); + map(0x51, 0x51).w(FUNC(anes_state::palette_offset_w)); + map(0x52, 0x52).w(FUNC(anes_state::palette_offset_msb_w)); + map(0x53, 0x53).w(FUNC(anes_state::palette_active_bank_w)); + map(0x54, 0x54).rw(FUNC(anes_state::palette_data_lsb_r), FUNC(anes_state::palette_data_lsb_w)); + map(0x55, 0x55).rw(FUNC(anes_state::palette_data_msb_r), FUNC(anes_state::palette_data_msb_w)); + map(0xfe, 0xfe).w(FUNC(anes_state::rombank_w)); } static INPUT_PORTS_START( anes ) - PORT_START("IN0") - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN ) // blitter busy status - PORT_BIT( 0xef, IP_ACTIVE_LOW, IPT_UNKNOWN ) // used, coin? - - PORT_START("DSW1") - PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "SW1:1") - PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "SW1:2") - PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "SW1:3") - PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "SW1:4") - PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "SW1:5") - PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "SW1:6") - PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "SW1:7") - PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "SW1:8") - - PORT_START("DSW2") - PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "SW2:1") - PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "SW2:2") - PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "SW2:3") - PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "SW2:4") - PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "SW2:5") - PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "SW2:6") - PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "SW2:7") - PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "SW2:8") - - PORT_START("DSW3") - PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "SW3:1") - PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "SW3:2") - PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "SW3:3") - PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "SW3:4") - PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "SW3:5") - PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "SW3:6") - PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "SW3:7") - PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "SW3:8") - - PORT_START("DSW4") - PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "SW4:1") - PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "SW4:2") - PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "SW4:3") - PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "SW4:4") - PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "SW4:5") - PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "SW4:6") - PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "SW4:7") - PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "SW4:8") + PORT_START("COIN") + PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("KEY1.0") + PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("KEY1.1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("KEY1.2") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) + PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("KEY1.3") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) + PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("KEY1.4") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) + PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("SW1") + PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW1:1" ) + PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW1:2" ) + PORT_DIPUNKNOWN_DIPLOC( 0x04, 0x04, "SW1:3" ) + PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW1:4" ) + PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW1:5" ) + PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW1:6" ) + PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW1:7" ) + PORT_DIPUNKNOWN_DIPLOC( 0x80, 0x80, "SW1:8" ) + + PORT_START("SW2") + PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW2:1" ) + PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW2:2" ) + PORT_DIPUNKNOWN_DIPLOC( 0x04, 0x04, "SW2:3" ) + PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW2:4" ) + PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW2:5" ) + PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW2:6" ) + PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW2:7" ) + PORT_DIPUNKNOWN_DIPLOC( 0x80, 0x80, "SW2:8" ) + + PORT_START("SW3") // port 0x12 + PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW3:1,2,3") + PORT_DIPSETTING( 0x00, "10 Coins/1 Credit" ) + PORT_DIPSETTING( 0x04, DEF_STR( 5C_1C ) ) + PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) ) + PORT_DIPSETTING( 0x06, DEF_STR( 2C_1C ) ) + PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) ) + PORT_DIPSETTING( 0x03, DEF_STR( 1C_2C ) ) + PORT_DIPSETTING( 0x05, DEF_STR( 1C_5C ) ) + PORT_DIPSETTING( 0x01, "1 Coin/10 Credits" ) + PORT_DIPNAME( 0x38, 0x38, "Bonus Chance" ) PORT_DIPLOCATION("SW3:4,5,6") + PORT_DIPSETTING( 0x38, "10" ) + PORT_DIPSETTING( 0x18, "5" ) + PORT_DIPSETTING( 0x28, "2" ) + PORT_DIPSETTING( 0x08, "1" ) + PORT_DIPSETTING( 0x30, "1/rand<2" ) // 2 + PORT_DIPSETTING( 0x10, "1/rand<3" ) // 3 + PORT_DIPSETTING( 0x20, "1/rand<5" ) // 5 + PORT_DIPSETTING( 0x00, "1/rand<10" ) // 10 + PORT_DIPNAME( 0x40, 0x40, "Use Rand" ) PORT_DIPLOCATION("SW3:7") + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, "Twice" ) PORT_DIPLOCATION("SW3:8") + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + + PORT_START("SW4") // port 0x13 + PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW4:1" ) + PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW4:2" ) + PORT_DIPUNKNOWN_DIPLOC( 0x04, 0x04, "SW4:3" ) + PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW4:4" ) + PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW4:5" ) + PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW4:6" ) + PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW4:7" ) + PORT_DIPUNKNOWN_DIPLOC( 0x80, 0x80, "SW4:8" ) INPUT_PORTS_END +static INPUT_PORTS_START( tonpuu ) + PORT_INCLUDE( anes ) + + PORT_MODIFY("SW4") // port 0x13 + PORT_DIPNAME( 0x04, 0x04, "Background Style" ) PORT_DIPLOCATION("SW4:3") + PORT_DIPSETTING( 0x04, "Textured" ) + PORT_DIPSETTING( 0x00, "Flat") +INPUT_PORTS_END void anes_state::machine_start() { + uint8_t* rom = memregion("maincpu")->base(); + for (int i = 0; i < (memregion("maincpu")->bytes() - 0x2000) / 0xc000; i++) + m_rombank->configure_entry(i, &rom[0x2000 + (0xc000 * i)]); + + m_inp_matrix = 0; + m_bank = 0; + m_bank_delay = 0; + + save_item(NAME(m_inp_matrix)); + save_item(NAME(m_bank)); + save_item(NAME(m_bank_delay)); +} + +void anes_state::video_start() +{ + for (int layer = 0; layer < 2; layer++) + { + m_bitmap[layer].allocate(512, 512); + m_bitmap[layer].fill(0); + } + + std::fill(std::begin(m_blit), std::end(m_blit), 0); + std::fill(std::begin(m_blit_addr), std::end(m_blit_addr), 0); + std::fill(std::begin(m_blit_val), std::end(m_blit_val), 0); + + save_item(NAME(m_blit)); + save_item(NAME(m_blit_addr)); + save_item(NAME(m_blit_val)); + + m_palette_enable = 0; + m_palette_offset = 0; + m_palette_offset_msb = 0; + m_palette_active_bank = 0; + m_palette_active_bank_alt = 0; + + std::fill(std::begin(m_palette_data_lsb), std::end(m_palette_data_lsb), 0); + std::fill(std::begin(m_palette_data_msb), std::end(m_palette_data_msb), 0); + + save_item(NAME(m_palette_enable)); + save_item(NAME(m_palette_offset)); + save_item(NAME(m_palette_offset_msb)); + save_item(NAME(m_palette_active_bank)); + save_item(NAME(m_palette_active_bank_alt)); + save_item(NAME(m_palette_data_lsb)); + save_item(NAME(m_palette_data_msb)); } +INTERRUPT_GEN_MEMBER(anes_state::interrupt) +{ + if (!m_bank_delay) + device.execute().set_input_line(INPUT_LINE_IRQ0, HOLD_LINE); +} void anes_state::anes(machine_config &config) { // basic machine hardware z80_device &maincpu(Z80(config, "maincpu", XTAL(16'000'000) / 2)); // Z0840008PSC maincpu.set_addrmap(AS_PROGRAM, &anes_state::prg_map); + maincpu.set_addrmap(AS_OPCODES, &anes_state::opcodes_map); maincpu.set_addrmap(AS_IO, &anes_state::io_map); - maincpu.set_vblank_int("screen", FUNC(anes_state::irq0_line_hold)); + maincpu.set_vblank_int("screen", FUNC(anes_state::interrupt)); // all wrong screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); screen.set_refresh_hz(60); screen.set_vblank_time(ATTOSECONDS_IN_USEC(0)); screen.set_size(64*8, 32*8); - screen.set_visarea_full(); + screen.set_visarea(0*8, 46*8-1, 0*8, 31*8-1); screen.set_screen_update(FUNC(anes_state::screen_update)); screen.set_palette("palette"); - PALETTE(config, "palette").set_entries(0x100); + PALETTE(config, "palette").set_entries(0x2000); // sound hardware SPEAKER(config, "mono").front_center(); @@ -192,11 +635,11 @@ ROM_START( sanma ) // exact ROM type unknown, dumped multiple times as various s ROM_REGION(0x80000, "maincpu", 0) ROM_LOAD( "anes_s26.u32", 0x00000, 0x80000, CRC(2c14ed16) SHA1(8ce0ddee9501896f76dab63d57326812ba4a9a6c) ) // 27C040?, 1ST AND 2ND HALF IDENTICAL - ROM_REGION(0x200000, "gfx1", 0) + ROM_REGION(0x200000, "blitter", 0) ROM_LOAD( "anes_301.u33", 0x000000, 0x80000, CRC(d2ba943d) SHA1(9aea0bda5186c0a746bf86eeaa2bd7910d3d5e03) ) // 27C040? ROM_LOAD( "anes_302.u34", 0x080000, 0x80000, CRC(92cac418) SHA1(3f17a7a95cc7d9ca3e1eb638276c40c8dab9f12d) ) // 27C040? - ROM_LOAD( "anes_324.u35", 0x100000, 0x80000, CRC(7f6a7af5) SHA1(c8657dc3053d3e125c9e92ade7467ffa31e48a34) ) // 27C040? - ROM_LOAD( "anes_333.u36", 0x180000, 0x80000, CRC(f46db452) SHA1(b545b071a72323009110aecfda6c434468851a63) ) // 27C040? + ROM_LOAD( "anes_333.u36", 0x100000, 0x80000, CRC(f46db452) SHA1(b545b071a72323009110aecfda6c434468851a63) ) // 27C040? + ROM_LOAD( "anes_324.u35", 0x180000, 0x80000, CRC(7f6a7af5) SHA1(c8657dc3053d3e125c9e92ade7467ffa31e48a34) ) // 27C040? ROM_REGION(0x4001, "fpga_bitstream", 0) ROM_LOAD( "17128epc.u41", 0x0000, 0x4001, CRC(95e38a6c) SHA1(ba2f563f6aa6de7d6439f73ccc6d82346e453e22) ) @@ -206,7 +649,7 @@ ROM_START( tonpuu ) ROM_REGION(0x20000, "maincpu", 0) ROM_LOAD( "201.u32", 0x00000, 0x20000, CRC(ace857bb) SHA1(3f65976883c0c514abf73eeed9223ca52a2be410) ) // 27C010 - ROM_REGION(0x100000, "gfx1", 0) + ROM_REGION(0x100000, "blitter", 0) ROM_LOAD( "202.u33", 0x00000, 0x80000, CRC(4d62a358) SHA1(6edff8e031272cd5a466d9767454093870a0f90a) ) // 27C4001 ROM_LOAD( "203.u34", 0x80000, 0x80000, CRC(a6068528) SHA1(c988bd1fc2f91befa9d0d39995ba98ef86b5d854) ) // 27C4001 @@ -217,5 +660,5 @@ ROM_END } // anonymous namespace -GAME( 2001, sanma, 0, anes, anes, anes_state, empty_init, ROT0, "ANES", "Sanma - San-nin Uchi Mahjong [BET] (Japan, version 2.60)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS ) // flyer says 2000, manual says 2001 version 2.60 -GAME( 200?, tonpuu, 0, anes, anes, anes_state, empty_init, ROT0, "ANES", "Ton Puu Mahjong [BET] (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS ) +GAME( 2001, sanma, 0, anes, anes, anes_state, empty_init, ROT0, "ANES", "Sanma - San-nin Uchi Mahjong [BET] (Japan, version 2.60)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS ) // flyer says 2000, manual says 2001 version 2.60 +GAME( 200?, tonpuu, 0, anes, tonpuu, anes_state, empty_init, ROT0, "ANES", "Ton Puu Mahjong [BET] (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS ) -- cgit v1.2.3