From 8db28561e7ba5d5e1bb1e1ec233be08d6111f186 Mon Sep 17 00:00:00 2001 From: angelosa Date: Sat, 27 Jul 2024 20:54:10 +0200 Subject: commodore/c65.cpp: misc cleanups --- src/mame/commodore/c65.cpp | 421 ++++++++++++++++++++------------------------- 1 file changed, 186 insertions(+), 235 deletions(-) diff --git a/src/mame/commodore/c65.cpp b/src/mame/commodore/c65.cpp index 837ecab7d4a..37adbb82315 100644 --- a/src/mame/commodore/c65.cpp +++ b/src/mame/commodore/c65.cpp @@ -1,16 +1,9 @@ -// license:LGPL-2.1+ +// license: BSD-3-Clause // copyright-holders: Angelo Salese /************************************************************************************************** C=65 / C=64DX (c) 1991 Commodore -Attempt at rewriting the driver ... - -Note: -- VIC-4567 will be eventually be added via compile switch, once that I - get the hang of the system (and checking where the old code fails - eventually) - Hardware infos can be found at: http://www.zimmers.net/cbmpics/cbm/c65/c65manual.txt http://www.zimmers.net/cbmpics/cbm/c65/c65faq20.txt @@ -28,6 +21,8 @@ http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/C64DX_aka_C65_System #include "emu.h" #include "cpu/m6502/m4510.h" #include "machine/mos6526.h" +#include "sound/mos6581.h" + #include "emupal.h" #include "screen.h" #include "softlist_dev.h" @@ -41,23 +36,26 @@ public: c65_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag) , m_maincpu(*this, "maincpu") - , m_cia0(*this, "cia_0") - , m_cia1(*this, "cia_1") + , m_cia(*this, "cia_%u", 0U) + , m_sid(*this, "sid_%u", 0U) + , m_cia_view(*this, "cia_view") , m_screen(*this, "screen") , m_palette(*this, "palette") - , m_workram(*this, "wram") + , m_workram(*this, "work_ram") , m_palred(*this, "redpal") , m_palgreen(*this, "greenpal") , m_palblue(*this, "bluepal") , m_dmalist(*this, "dmalist") , m_cram(*this, "cram") , m_gfxdecode(*this, "gfxdecode") + , m_ipl_rom(*this, "ipl") { } // devices required_device m_maincpu; - required_device m_cia0; - required_device m_cia1; + required_device_array m_cia; + required_device_array m_sid; + memory_view m_cia_view; required_device m_screen; required_device m_palette; required_shared_ptr m_workram; @@ -67,33 +65,28 @@ public: required_shared_ptr m_dmalist; required_shared_ptr m_cram; required_device m_gfxdecode; + required_memory_region m_ipl_rom; - uint8_t *m_iplrom = nullptr; uint8_t m_keyb_input[10]{}; uint8_t m_keyb_c0_c7 = 0U; uint8_t m_keyb_c8_c9 = 0U; - uint8_t vic4567_dummy_r(offs_t offset); - void vic4567_dummy_w(offs_t offset, uint8_t data); + void vic4567_map(address_map &map); void PalRed_w(offs_t offset, uint8_t data); void PalGreen_w(offs_t offset, uint8_t data); void PalBlue_w(offs_t offset, uint8_t data); uint8_t uart_r(offs_t offset); void uart_w(offs_t offset, uint8_t data); void DMAgic_w(address_space &space, offs_t offset, uint8_t data); - uint8_t CIASelect_r(offs_t offset); - void CIASelect_w(offs_t offset, uint8_t data); uint8_t cia0_porta_r(); void cia0_porta_w(uint8_t data); uint8_t cia0_portb_r(); void cia0_portb_w(uint8_t data); void cia0_irq(int state); - uint8_t dummy_r(); - // screen updates uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); - void c65_palette(palette_device &palette); + void palette_init(palette_device &palette); void init_c65(); void init_c65pal(); @@ -119,23 +112,98 @@ private: void PalEntryFlush(uint8_t offset); void DMAgicExecute(address_space &space,uint32_t address); void IRQCheck(uint8_t irq_cause); - int inner_x_char(int xoffs); - int inner_y_char(int yoffs); }; +// TODO: move to own device void c65_state::video_start() { } -// TODO: inline? -int c65_state::inner_x_char(int xoffs) -{ - return xoffs>>3; -} - -int c65_state::inner_y_char(int yoffs) -{ - return yoffs>>3; +void c65_state::vic4567_map(address_map &map) +{ + map(0x11, 0x11).lr8( + NAME([this] (offs_t offset) { + return (m_screen->vpos() & 0x100) >> 1; + }) + ); + map(0x12, 0x12).lr8( + NAME([this] (offs_t offset) { + return (m_screen->vpos() & 0xff); + }) + ); + map(0x15, 0x15).lr8( + NAME([this] (offs_t offset) { + return 0xff; // silence log for now + }) + ); + map(0x18, 0x18).lrw8( + NAME([this] (offs_t offset) { + return m_VIC2_VS_CB_Base; + }), + NAME([this] (offs_t offset, u8 data) { + m_VIC2_VS_CB_Base = data; + }) + ); + map(0x19, 0x19).lrw8( + NAME([this] (offs_t offset) { + return m_VIC2_IRQPend; + }), + NAME([this] (offs_t offset, u8 data) { + m_VIC2_IRQPend &= ~data; + IRQCheck(0); + }) + ); + map(0x1a, 0x1a).lrw8( + NAME([this] (offs_t offset) { + return m_VIC2_IRQMask; + }), + NAME([this] (offs_t offset, u8 data) { + m_VIC2_IRQMask = data & 0xf; + IRQCheck(0); + }) + ); + map(0x20, 0x20).lrw8( + NAME([this] (offs_t offset) { + return m_VIC2_EXTColor; + }), + NAME([this] (offs_t offset, u8 data) { + m_VIC2_EXTColor = data & 0xf; + }) + ); + map(0x21, 0x21).lrw8( + NAME([this] (offs_t offset) { + return m_VIC2_BK0_Color; + }), + NAME([this] (offs_t offset, u8 data) { + m_VIC2_BK0_Color = data & 0xf; + }) + ); + /* + * KEY register, handles vic-iii and vic-ii modes via two consecutive writes + * 0xa5 -> 0x96 vic-iii mode + * any other write vic-ii mode + */ +// map(0x2f, 0x2f) + map(0x30, 0x30).lrw8( + NAME([this] (offs_t offset) { + return m_VIC3_ControlA; + }), + NAME([this] (offs_t offset, u8 data) { + if((data & 0xfe) != 0x64) + logerror("CONTROL A %02x\n",data); + m_VIC3_ControlA = data; + m_cia_view.select(BIT(data, 0)); + }) + ); + map(0x31, 0x31).lrw8( + NAME([this] (offs_t offset) { + return m_VIC3_ControlB; + }), + NAME([this] (offs_t offset, u8 data) { + logerror("CONTROL B %02x\n", data); + m_VIC3_ControlB = data; + }) + ); } uint32_t c65_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect ) @@ -143,25 +211,24 @@ uint32_t c65_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, int pixel_width = (m_VIC3_ControlB & 0x80) ? 1 : 2; int columns = 80 / pixel_width; - uint8_t *cptr = &m_iplrom[((m_VIC3_ControlA & 0x40) ? 0x9000: 0xd000) + ((m_VIC2_VS_CB_Base & 0x2) << 10)]; + uint8_t *cptr = &m_ipl_rom->base()[((m_VIC3_ControlA & 0x40) ? 0x9000: 0xd000) + ((m_VIC2_VS_CB_Base & 0x2) << 10)]; // TODO: border area - for(int y=cliprect.top();y<=cliprect.bottom();y++) + for(int y = cliprect.top(); y <= cliprect.bottom(); y++) { - for(int x=cliprect.left();x<=cliprect.right();x++) + for(int x = cliprect.left(); x <= cliprect.right(); x++) { - //int, xi,yi,xm,ym,dot_x; - int xi = inner_x_char(x / pixel_width); - int yi = inner_y_char(y); + int xi = (x >> 3) / pixel_width; + int yi = (y >> 3); int xm = 7 - ((x / pixel_width) & 7); int ym = (y & 7); - uint8_t tile = m_workram[xi+yi*columns+0x800]; - uint8_t attr = m_cram[xi+yi*columns]; + uint8_t tile = m_workram[xi + yi * columns + 0x800]; + uint8_t attr = m_cram[xi + yi * columns]; int foreground_color = attr & 0xf; int background_color = m_VIC2_BK0_Color & 0xf; int highlight_color = 0; - int enable_dot = ((cptr[(tile<<3)+ym] >> xm) & 1); + int enable_dot = ((cptr[(tile << 3) + ym] >> xm) & 1); if (attr & 0x10) { @@ -176,102 +243,13 @@ uint32_t c65_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, if (attr & 0x20) enable_dot = !enable_dot; if (attr & 0x10) enable_dot = 0; - //if(cliprect.contains(x, y)) bitmap.pix(y, x) = m_palette->pen(highlight_color + ((enable_dot) ? foreground_color : background_color)); - - - //gfx->opaque(bitmap,cliprect,tile,0,0,0,x*8,y*8); } } return 0; } -uint8_t c65_state::vic4567_dummy_r(offs_t offset) -{ - uint8_t res; - - res=0xff; - switch(offset) - { - case 0x11: - res = (m_screen->vpos() & 0x100) >> 1; - return res; - case 0x12: - res = (m_screen->vpos() & 0xff); - return res; - case 0x15: - return 0xff; // silence log for now - - case 0x18: - return m_VIC2_VS_CB_Base; - - case 0x19: - return m_VIC2_IRQPend; - - case 0x1a: - return m_VIC2_IRQMask; - - case 0x20: - return m_VIC2_EXTColor; - - case 0x21: - return m_VIC2_BK0_Color; - - case 0x30: - return m_VIC3_ControlA; - case 0x31: - return m_VIC3_ControlB; - } - - if(!machine().side_effects_disabled()) - logerror("%02x\n",offset); // TODO: PC - return res; -} - -void c65_state::vic4567_dummy_w(offs_t offset, uint8_t data) -{ - switch(offset) - { - case 0x18: - m_VIC2_VS_CB_Base = data; - break; - case 0x19: - m_VIC2_IRQPend &= ~data; - IRQCheck(0); - break; - case 0x1a: - m_VIC2_IRQMask = data & 0xf; - IRQCheck(0); - break; - case 0x20: - m_VIC2_EXTColor = data & 0xf; - break; - case 0x21: - m_VIC2_BK0_Color = data & 0xf; - break; - - /* KEY register, handles vic-iii and vic-ii modes via two consecutive writes - 0xa5 -> 0x96 vic-iii mode - any other write vic-ii mode - */ - //case 0x2f: break; - case 0x30: - if((data & 0xfe) != 0x64) - logerror("CONTROL A %02x\n",data); - m_VIC3_ControlA = data; - break; - case 0x31: - logerror("CONTROL B %02x\n",data); - m_VIC3_ControlB = data; - break; - default: - logerror("%02x %02x\n", offset, data); - break; - } - -} - void c65_state::PalEntryFlush(uint8_t offset) { m_palette->set_pen_color(offset, pal4bit(m_palred[offset]), pal4bit(m_palgreen[offset]), pal4bit(m_palblue[offset])); @@ -295,28 +273,6 @@ void c65_state::PalBlue_w(offs_t offset, uint8_t data) PalEntryFlush(offset); } -uint8_t c65_state::uart_r(offs_t offset) -{ - switch (offset) - { - case 7: - return ioport("CAPS")->read(); - } - return 0xff; -} - -void c65_state::uart_w(offs_t offset, uint8_t data) -{ - switch (offset) - { - case 7: - m_keyb_c8_c9 = (~data >> 1) & 3; - break; - case 8: - // ddr? - break; - } -} void c65_state::DMAgicExecute(address_space &space,uint32_t address) { @@ -391,51 +347,27 @@ void c65_state::DMAgic_w(address_space &space, offs_t offset, uint8_t data) DMAgicExecute(space,(m_dmalist[0])|(m_dmalist[1]<<8)|(m_dmalist[2]<<16)); } -uint8_t c65_state::CIASelect_r(offs_t offset) +uint8_t c65_state::uart_r(offs_t offset) { - if(m_VIC3_ControlA & 1) - return m_cram[offset]; - else + switch (offset) { - // CIA at 0xdc00 - switch((offset & 0x700) | 0x800) - { - case 0xc00: - return m_cia0->read(offset); - case 0xd00: - return m_cia1->read(offset); - default: - logerror("Unknown I/O access read to offset %04x\n",offset); - break; - } - + case 7: + return ioport("CAPS")->read(); } - return 0xff; } -void c65_state::CIASelect_w(offs_t offset, uint8_t data) +void c65_state::uart_w(offs_t offset, uint8_t data) { - if(m_VIC3_ControlA & 1) - m_cram[offset] = data; - else + switch (offset) { - // CIA at 0xdc00 - switch((offset & 0x700) | 0x800) - { - case 0xc00: - m_cia0->write(offset, data); - break; - - case 0xd00: - m_cia1->write(offset, data); - break; - default: - logerror("Unknown I/O access write to offset %04x data = %02x\n", offset, data); - break; - } + case 7: + m_keyb_c8_c9 = (~data >> 1) & 3; + break; + case 8: + // ddr? + break; } - } uint8_t c65_state::cia0_porta_r() @@ -479,42 +411,48 @@ void c65_state::cia0_portb_w(uint8_t data) { } -uint8_t c65_state::dummy_r() -{ - return 0; -} void c65_state::c65_map(address_map &map) { - map(0x00000, 0x07fff).ram().share("wram"); // TODO: bank - map(0x0c800, 0x0cfff).rom().region("maincpu", 0xc800); - map(0x0d000, 0x0d07f).rw(FUNC(c65_state::vic4567_dummy_r), FUNC(c65_state::vic4567_dummy_w)); // 0x0d000, 0x0d07f VIC-4567 - map(0x0d080, 0x0d081).r(FUNC(c65_state::dummy_r)); // 0x0d080, 0x0d09f FDC + map(0x00000, 0x07fff).ram().share("work_ram"); // TODO: bank + map(0x0c800, 0x0cfff).rom().region("ipl", 0xc800); + map(0x0d000, 0x0d07f).m(*this, FUNC(c65_state::vic4567_map)); + // 0x0d080, 0x0d09f FDC // 0x0d0a0, 0x0d0ff Ram Expansion Control (REC) map(0x0d100, 0x0d1ff).ram().w(FUNC(c65_state::PalRed_w)).share("redpal");// 0x0d100, 0x0d1ff Red Palette map(0x0d200, 0x0d2ff).ram().w(FUNC(c65_state::PalGreen_w)).share("greenpal"); // 0x0d200, 0x0d2ff Green Palette map(0x0d300, 0x0d3ff).ram().w(FUNC(c65_state::PalBlue_w)).share("bluepal"); // 0x0d300, 0x0d3ff Blue Palette // 0x0d400, 0x0d4*f Right SID + map(0x0d400, 0x0d41f).rw(m_sid[1], FUNC(mos6581_device::read), FUNC(mos6581_device::write)); // 0x0d440, 0x0d4*f Left SID + map(0x0d440, 0x0d45f).rw(m_sid[0], FUNC(mos6581_device::read), FUNC(mos6581_device::write)); map(0x0d600, 0x0d6ff).rw(FUNC(c65_state::uart_r), FUNC(c65_state::uart_w)); map(0x0d700, 0x0d702).w(FUNC(c65_state::DMAgic_w)).share("dmalist"); // 0x0d700, 0x0d7** DMAgic //map(0x0d703, 0x0d703).r(FUNC(c65_state::DMAgic_r)); // 0x0d800, 0x0d8** Color matrix - map(0x0d800, 0x0dfff).rw(FUNC(c65_state::CIASelect_r), FUNC(c65_state::CIASelect_w)).share("cram"); - // 0x0dc00, 0x0dc** CIA-1 - // 0x0dd00, 0x0dd** CIA-2 + map(0x0d800, 0x0dfff).view(m_cia_view); + // maps lower 1024 bytes regardless of the setting (essentially touches $dc00 as overlay) + m_cia_view[0](0x0d800, 0x0dbff).lrw8( + NAME([this] (offs_t offset) { return m_cram[offset]; }), + NAME([this] (offs_t offset, u8 data) { m_cram[offset] = data; }) + ); + m_cia_view[0](0x0dc00, 0x0dc0f).rw(m_cia[0], FUNC(mos6526_device::read), FUNC(mos6526_device::write)); + m_cia_view[0](0x0dd00, 0x0dd0f).rw(m_cia[1], FUNC(mos6526_device::read), FUNC(mos6526_device::write)); // 0x0de00, 0x0de** Ext I/O Select 1 // 0x0df00, 0x0df** Ext I/O Select 2 (RAM window?) - map(0x0e000, 0x0ffff).rom().region("maincpu", 0x0e000); + m_cia_view[1](0x0d800, 0x0dfff).ram().share("cram"); + map(0x0e000, 0x0ffff).rom().region("ipl", 0x0e000); map(0x10000, 0x1f7ff).ram(); - map(0x1f800, 0x1ffff).ram(); // VRAM attributes - map(0x20000, 0x3ffff).rom().region("maincpu", 0); + map(0x1f800, 0x1ffff).ram().share("cram"); + map(0x20000, 0x3ffff).rom().region("ipl", 0); +// 0x40000, 0x7ffff cart expansion +// 0x80000, 0xfffff RAM expansion } static INPUT_PORTS_START( c65 ) - PORT_START( "C0" ) + PORT_START("C0") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("INST DEL") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) PORT_CHAR(UCHAR_MAMEKEY(INSERT)) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Crsr Right Left") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) @@ -524,7 +462,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F5)) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Crsr Down Up") PORT_CODE(KEYCODE_RALT) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) PORT_CHAR(UCHAR_MAMEKEY(UP)) - PORT_START( "C1" ) + PORT_START("C1") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('A') @@ -534,7 +472,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Shift (Left)") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) - PORT_START( "C2" ) + PORT_START("C2") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('D') @@ -544,7 +482,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('X') - PORT_START( "C3" ) + PORT_START("C3") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('G') @@ -554,7 +492,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('V') - PORT_START( "C4" ) + PORT_START("C4") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('J') @@ -564,7 +502,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('N') - PORT_START( "C5" ) + PORT_START("C5") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('+') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('L') @@ -574,7 +512,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') - PORT_START( "C6" ) + PORT_START("C6") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR(0xA3) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('*') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(';') PORT_CHAR(']') @@ -584,7 +522,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x91 Pi") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x2191) PORT_CHAR(0x03C0) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') - PORT_START( "C7" ) + PORT_START("C7") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x90") PORT_CODE(KEYCODE_TILDE) PORT_CHAR(0x2190) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2) @@ -594,7 +532,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RUN STOP") PORT_CODE(KEYCODE_HOME) - PORT_START( "C8" ) + PORT_START("C8") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("NO SCROLL") PORT_CODE(KEYCODE_SCRLOCK) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RALT) @@ -604,7 +542,7 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F13)) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ESC) - PORT_START( "C9") + PORT_START("C9") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNKNOWN1") PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNKNOWN2") PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("linefeed?") @@ -614,29 +552,29 @@ static INPUT_PORTS_START( c65 ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNKNOWN7") PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNKNOWN8") - PORT_START( "CAPS" ) + PORT_START("CAPS") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CAPS LOCK") PORT_CODE(KEYCODE_F8) PORT_TOGGLE INPUT_PORTS_END void c65_state::machine_start() { - m_iplrom = memregion("maincpu")->base(); - save_pointer(NAME(m_cram.target()), 0x800); } void c65_state::machine_reset() { + m_cia_view.select(0); } -void c65_state::c65_palette(palette_device &palette) +void c65_state::palette_init(palette_device &palette) { for (int i = 0; i < 0x100; i++) PalEntryFlush(i); } +// debug static const gfx_layout charlayout = { 8,8, @@ -649,7 +587,9 @@ static const gfx_layout charlayout = }; static GFXDECODE_START( gfx_c65 ) - GFXDECODE_ENTRY( "maincpu", 0xd000, charlayout, 0, 16 ) // another identical copy is at 0x9000 + GFXDECODE_ENTRY( "ipl", 0xd000, charlayout, 0, 16 ) + // almost identical to above + GFXDECODE_ENTRY( "ipl", 0x9000, charlayout, 0, 16 ) GFXDECODE_END void c65_state::IRQCheck(uint8_t irq_cause) @@ -657,7 +597,7 @@ void c65_state::IRQCheck(uint8_t irq_cause) m_VIC2_IRQPend |= (irq_cause != 0) ? 0x80 : 0x00; m_VIC2_IRQPend |= irq_cause; - m_maincpu->set_input_line(M4510_IRQ_LINE,m_VIC2_IRQMask & m_VIC2_IRQPend ? ASSERT_LINE : CLEAR_LINE); + m_maincpu->set_input_line(M4510_IRQ_LINE, m_VIC2_IRQMask & m_VIC2_IRQPend ? ASSERT_LINE : CLEAR_LINE); } INTERRUPT_GEN_MEMBER(c65_state::vic3_vblank_irq) @@ -679,7 +619,7 @@ void c65_state::cia0_irq(int state) m_keyb_input[i] = ioport(c64ports[i])->read(); } #endif -// m_cia0_irq = state; +// m_cia[0]_irq = state; // c65_irq(state || m_vicirq); } @@ -690,19 +630,19 @@ void c65_state::c65(machine_config &config) m_maincpu->set_addrmap(AS_PROGRAM, &c65_state::c65_map); m_maincpu->set_vblank_int("screen", FUNC(c65_state::vic3_vblank_irq)); - MOS6526(config, m_cia0, MAIN_CLOCK); - m_cia0->set_tod_clock(60); - m_cia0->irq_wr_callback().set(FUNC(c65_state::cia0_irq)); - m_cia0->pa_rd_callback().set(FUNC(c65_state::cia0_porta_r)); - m_cia0->pa_wr_callback().set(FUNC(c65_state::cia0_porta_w)); - m_cia0->pb_rd_callback().set(FUNC(c65_state::cia0_portb_r)); - m_cia0->pb_wr_callback().set(FUNC(c65_state::cia0_portb_w)); + MOS6526(config, m_cia[0], MAIN_CLOCK); + m_cia[0]->set_tod_clock(60); + m_cia[0]->irq_wr_callback().set(FUNC(c65_state::cia0_irq)); + m_cia[0]->pa_rd_callback().set(FUNC(c65_state::cia0_porta_r)); + m_cia[0]->pa_wr_callback().set(FUNC(c65_state::cia0_porta_w)); + m_cia[0]->pb_rd_callback().set(FUNC(c65_state::cia0_portb_r)); + m_cia[0]->pb_wr_callback().set(FUNC(c65_state::cia0_portb_w)); - MOS6526(config, m_cia1, MAIN_CLOCK); - m_cia1->set_tod_clock(60); -// m_cia1->irq_wr_callback().set(FUNC(c65_state::c65_cia1_interrupt)); -// m_cia1->pa_rd_callback().set(FUNC(c65_state::c65_cia1_port_a_r)); -// m_cia1->pa_wr_callback().set(FUNC(c65_state::c65_cia1_port_a_w)); + MOS6526(config, m_cia[1], MAIN_CLOCK); + m_cia[1]->set_tod_clock(60); +// m_cia[1]->irq_wr_callback().set(FUNC(c65_state::c65_cia1_interrupt)); +// m_cia[1]->pa_rd_callback().set(FUNC(c65_state::c65_cia1_port_a_r)); +// m_cia[1]->pa_wr_callback().set(FUNC(c65_state::c65_cia1_port_a_w)); /* video hardware */ @@ -717,12 +657,23 @@ void c65_state::c65(machine_config &config) GFXDECODE(config, m_gfxdecode, m_palette, gfx_c65); - PALETTE(config, m_palette, FUNC(c65_state::c65_palette), 0x100); + PALETTE(config, m_palette, FUNC(c65_state::palette_init), 0x100); /* sound hardware */ SPEAKER(config, "lspeaker").front_left(); SPEAKER(config, "rspeaker").front_right(); - // 2x 8580 SID + // 8580 SID + constexpr XTAL sidxtal(XTAL(14'318'181) / 14); // TODO: check exact frequency + MOS6581(config, m_sid[0], sidxtal); + //m_sid->potx().set(FUNC(c64_state::sid_potx_r)); + //m_sid->poty().set(FUNC(c64_state::sid_poty_r)); + m_sid[0]->add_route(ALL_OUTPUTS, "lspeaker", 0.50); + + MOS6581(config, m_sid[1], sidxtal); + //m_sid->potx().set(FUNC(c64_state::sid_potx_r)); + //m_sid->poty().set(FUNC(c64_state::sid_poty_r)); + m_sid[1]->add_route(ALL_OUTPUTS, "rspeaker", 0.50); + // software list SOFTWARE_LIST(config, "flop_list").set_original("c65_flop"); @@ -736,7 +687,7 @@ void c65_state::c65(machine_config &config) ***************************************************************************/ ROM_START( c65 ) - ROM_REGION( 0x20000, "maincpu", 0 ) + ROM_REGION( 0x20000, "ipl", 0 ) ROM_SYSTEM_BIOS( 0, "910111", "V0.9.910111" ) // sum16 CAFF, this shows up on the picture from a spare, unused rom on the 20171102 c64dx auction as "390488-02 CAFF" with the 02 scratched off on the chip and 03 written in pen, unclear what the "correct" label is. ROMX_LOAD( "910111.bin", 0x0000, 0x20000, CRC(c5d8d32e) SHA1(71c05f098eff29d306b0170e2c1cdeadb1a5f206), ROM_BIOS(0) ) ROM_SYSTEM_BIOS( 1, "910523", "V0.9.910523" ) // sum16 B96B @@ -750,7 +701,7 @@ ROM_START( c65 ) ROM_END ROM_START( c64dx ) - ROM_REGION( 0x20000, "maincpu", 0 ) // "v0.90.910429", sum16 E96A + ROM_REGION( 0x20000, "ipl", 0 ) // "v0.90.910429", sum16 E96A ROM_LOAD( "910429.bin", 0x0000, 0x20000, CRC(b025805c) SHA1(c3b05665684f74adbe33052a2d10170a1063ee7d) ) ROM_END -- cgit v1.2.3