From 84a742314269652a6016ba587d5a2c99a2c2f8c8 Mon Sep 17 00:00:00 2001 From: hap Date: Mon, 11 Sep 2023 12:54:52 +0200 Subject: cps2: simplify prev commit, and change dsw setting order in UI from on-off to off-on --- src/mame/capcom/cps2.cpp | 81 +++++++++++++++++++++--------------------------- 1 file changed, 36 insertions(+), 45 deletions(-) diff --git a/src/mame/capcom/cps2.cpp b/src/mame/capcom/cps2.cpp index c2e5b12e58f..a80fc3b86b5 100644 --- a/src/mame/capcom/cps2.cpp +++ b/src/mame/capcom/cps2.cpp @@ -1389,6 +1389,7 @@ uint16_t cps2_state::joy_or_paddle_ecofghtr_r() } } + /************************************* * * Memory map @@ -1412,13 +1413,7 @@ void cps2_state::cps2_map(address_map &map) map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present. map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup) - map(0x8040b0, 0x8040b2).lr8( // DIP switches (only present on development hardware) - NAME([this] (offs_t offset) { - return this->ioport("HW_TYPE")->read() == 0 - ? (unsigned) 0xff - : m_dsw[offset]->read(); - }) - ); + map(0x8040b0, 0x8040b2).lr8(NAME([this](offs_t offset) { return m_dsw[offset]->read(); })); // DIP switches (only present on development hardware) map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom @@ -1457,13 +1452,7 @@ void cps2_state::dead_cps2_map(address_map &map) map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present. map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup) - map(0x8040b0, 0x8040b2).lr8( // DIP switches (only present on development hardware) - NAME([this] (offs_t offset) { - return this->ioport("HW_TYPE")->read() == 0 - ? (unsigned) 0xff - : m_dsw[offset]->read(); - }) - ); + map(0x8040b0, 0x8040b2).lr8(NAME([this](offs_t offset) { return m_dsw[offset]->read(); })); // DIP switches (only present on development hardware) map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom @@ -1552,89 +1541,91 @@ static INPUT_PORTS_START( cps2_4p4b ) PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_VOLUME_UP ) // Machine configuration for dev hardware with DIPs - PORT_START("HW_TYPE") - PORT_CONFNAME(0x01,0x00,"Hardware") - PORT_CONFSETTING(0x00, "Production") - PORT_CONFSETTING(0x01, "Development (Enable Debug DIPs)") + PORT_START( "HW_TYPE" ) + PORT_CONFNAME( 0x01, 0x00, "Hardware" ) + PORT_CONFSETTING( 0x00, "Production" ) + PORT_CONFSETTING( 0x01, "Development (Enable Debug DIPs)" ) - PORT_START("DSWA") + PORT_START("DSWA") PORT_DIPNAME( 0x01, 0x01, "1-1" ) PORT_DIPLOCATION("SW1:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) - PORT_DIPNAME( 0x02, 0x02, "1-2" ) PORT_DIPLOCATION("SW1:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, "1-2" ) PORT_DIPLOCATION("SW1:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) - PORT_DIPNAME( 0x04, 0x04, "1-3" ) PORT_DIPLOCATION("SW1:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, "1-3" ) PORT_DIPLOCATION("SW1:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) - PORT_DIPNAME( 0x08, 0x08, "1-4" ) PORT_DIPLOCATION("SW1:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, "1-4" ) PORT_DIPLOCATION("SW1:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) - PORT_DIPNAME( 0x10, 0x10, "1-5" ) PORT_DIPLOCATION("SW1:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, "1-5" ) PORT_DIPLOCATION("SW1:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) - PORT_DIPNAME( 0x20, 0x20, "1-6" ) PORT_DIPLOCATION("SW1:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, "1-6" ) PORT_DIPLOCATION("SW1:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) - PORT_DIPNAME( 0x40, 0x40, "1-7" ) PORT_DIPLOCATION("SW1:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, "1-7" ) PORT_DIPLOCATION("SW1:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) - PORT_DIPNAME( 0x80, 0x80, "1-8" ) PORT_DIPLOCATION("SW1:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, "1-8" ) PORT_DIPLOCATION("SW1:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x00) PORT_START("DSWB") PORT_DIPNAME( 0x01, 0x01, "2-1" ) PORT_DIPLOCATION("SW2:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) - PORT_DIPNAME( 0x02, 0x02, "2-2" ) PORT_DIPLOCATION("SW2:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, "2-2" ) PORT_DIPLOCATION("SW2:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) - PORT_DIPNAME( 0x04, 0x04, "2-3" ) PORT_DIPLOCATION("SW2:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, "2-3" ) PORT_DIPLOCATION("SW2:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) - PORT_DIPNAME( 0x08, 0x08, "2-4" ) PORT_DIPLOCATION("SW2:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, "2-4" ) PORT_DIPLOCATION("SW2:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) - PORT_DIPNAME( 0x10, 0x10, "2-5" ) PORT_DIPLOCATION("SW2:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, "2-5" ) PORT_DIPLOCATION("SW2:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) - PORT_DIPNAME( 0x20, 0x20, "2-6" ) PORT_DIPLOCATION("SW2:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, "2-6" ) PORT_DIPLOCATION("SW2:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) - PORT_DIPNAME( 0x40, 0x40, "2-7" ) PORT_DIPLOCATION("SW2:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, "2-7" ) PORT_DIPLOCATION("SW2:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) - PORT_DIPNAME( 0x80, 0x80, "2-8" ) PORT_DIPLOCATION("SW2:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, "2-8" ) PORT_DIPLOCATION("SW2:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x00) - PORT_START("DSWC") + PORT_START("DSWC") PORT_DIPNAME( 0x01, 0x01, "3-1" ) PORT_DIPLOCATION("SW3:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) - PORT_DIPNAME( 0x02, 0x02, "3-2" ) PORT_DIPLOCATION("SW3:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, "3-2" ) PORT_DIPLOCATION("SW3:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) - PORT_DIPNAME( 0x04, 0x04, "3-3" ) PORT_DIPLOCATION("SW3:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, "3-3" ) PORT_DIPLOCATION("SW3:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) - PORT_DIPNAME( 0x08, 0x08, "3-4" ) PORT_DIPLOCATION("SW3:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, "3-4" ) PORT_DIPLOCATION("SW3:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) - PORT_DIPNAME( 0x10, 0x10, "3-5" ) PORT_DIPLOCATION("SW3:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, "3-5" ) PORT_DIPLOCATION("SW3:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) - PORT_DIPNAME( 0x20, 0x20, "3-6" ) PORT_DIPLOCATION("SW3:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, "3-6" ) PORT_DIPLOCATION("SW3:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) - PORT_DIPNAME( 0x40, 0x40, "3-7" ) PORT_DIPLOCATION("SW3:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, "3-7" ) PORT_DIPLOCATION("SW3:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) - PORT_DIPNAME( 0x80, 0x80, "3-8" ) PORT_DIPLOCATION("SW3:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, "3-8" ) PORT_DIPLOCATION("SW3:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01) PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) - + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x00) INPUT_PORTS_END // 4 players and 3 buttons -- cgit v1.2.3