From 802de68cb476f38894b86560ae458ce45f4e986c Mon Sep 17 00:00:00 2001 From: Mark Garlanger Date: Sat, 11 Jan 2025 04:28:16 -0600 Subject: bus/heathzenith/h89: Remove signals present on a real h89bus (#13193) --- scripts/src/bus.lua | 14 +- src/devices/bus/heathzenith/h89/cards.cpp | 46 ---- src/devices/bus/heathzenith/h89/cards.h | 18 -- src/devices/bus/heathzenith/h89/h89bus.cpp | 18 -- src/devices/bus/heathzenith/h89/h89bus.h | 26 +-- src/devices/bus/heathzenith/h89/intr_cntrl.cpp | 278 +++++++++++++++++++++++ src/devices/bus/heathzenith/h89/intr_cntrl.h | 168 ++++++++++++++ src/devices/bus/heathzenith/h89/mms77316_fdc.cpp | 74 +----- src/devices/bus/heathzenith/h89/mms77316_fdc.h | 55 +++++ src/devices/bus/heathzenith/h89/z37_fdc.cpp | 71 +----- src/devices/bus/heathzenith/h89/z37_fdc.h | 53 +++++ src/mame/heathzenith/h89.cpp | 68 ++++-- src/mame/heathzenith/intr_cntrl.cpp | 278 ----------------------- src/mame/heathzenith/intr_cntrl.h | 168 -------------- 14 files changed, 641 insertions(+), 694 deletions(-) delete mode 100644 src/devices/bus/heathzenith/h89/cards.cpp delete mode 100644 src/devices/bus/heathzenith/h89/cards.h create mode 100644 src/devices/bus/heathzenith/h89/intr_cntrl.cpp create mode 100644 src/devices/bus/heathzenith/h89/intr_cntrl.h delete mode 100644 src/mame/heathzenith/intr_cntrl.cpp delete mode 100644 src/mame/heathzenith/intr_cntrl.h diff --git a/scripts/src/bus.lua b/scripts/src/bus.lua index 7341724f85c..ae88c1125e6 100644 --- a/scripts/src/bus.lua +++ b/scripts/src/bus.lua @@ -5771,8 +5771,6 @@ end if (BUSES["H89BUS"]~=null) then files { - MAME_DIR .. "src/devices/bus/heathzenith/h89/cards.cpp", - MAME_DIR .. "src/devices/bus/heathzenith/h89/cards.h", MAME_DIR .. "src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp", MAME_DIR .. "src/devices/bus/heathzenith/h89/cdr_fdc_880h.h", MAME_DIR .. "src/devices/bus/heathzenith/h89/h89bus.cpp", @@ -5798,6 +5796,18 @@ if (BUSES["H89BUS"]~=null) then } end +--------------------------------------------------- +-- +--@src/devices/bus/heathzenith/h89/intr_cntrl.h,BUSES["HEATH_INTR_SOCKET"] = true +--------------------------------------------------- + +if (BUSES["HEATH_INTR_SOCKET"]~=null) then + files { + MAME_DIR .. "src/devices/bus/heathzenith/h89/intr_cntrl.cpp", + MAME_DIR .. "src/devices/bus/heathzenith/h89/intr_cntrl.h", + } +end + --------------------------------------------------- -- --@src/devices/bus/heathzenith/h19/tlb.h,BUSES["HEATH_TLB_CONNECTOR"] = true diff --git a/src/devices/bus/heathzenith/h89/cards.cpp b/src/devices/bus/heathzenith/h89/cards.cpp deleted file mode 100644 index 0a33bd8593f..00000000000 --- a/src/devices/bus/heathzenith/h89/cards.cpp +++ /dev/null @@ -1,46 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:R. Belmont -/*************************************************************************** - - H-89 and Z-90 slot cards - -***************************************************************************/ - -#include "emu.h" -#include "cards.h" - -#include "cdr_fdc_880h.h" -#include "h_88_3.h" -#include "h_88_5.h" -#include "mms77316_fdc.h" -#include "sigmasoft_sound.h" -#include "we_pullup.h" -#include "z_89_11.h" -#include "z37_fdc.h" - - -void h89_right_cards(device_slot_interface &device) -{ - device.option_add("cdr_fdc", H89BUS_CDR_FDC_880H); - device.option_add("h_88_3", H89BUS_H_88_3); - device.option_add("ha_88_3", H89BUS_HA_88_3); - device.option_add("h_88_5", H89BUS_H_88_5); - device.option_add("ss_snd", H89BUS_SIGMASOFT_SND); - device.option_add("z_89_11", H89BUS_Z_89_11); - - device.option_add("z37fdc", H89BUS_Z37); -} - -void h89_right_cards_mms(device_slot_interface &device) -{ - h89_right_cards(device); - device.option_add("mms77316", H89BUS_MMS77316); -} - -void h89_right_p506_cards(device_slot_interface &device) -{ - device.option_add("h_88_3", H89BUS_H_88_3); - device.option_add("ha_88_3", H89BUS_HA_88_3); - device.option_add("ss_snd", H89BUS_SIGMASOFT_SND); - device.option_add("we_pullup", H89BUS_WE_PULLUP); -} diff --git a/src/devices/bus/heathzenith/h89/cards.h b/src/devices/bus/heathzenith/h89/cards.h deleted file mode 100644 index f9ca720a021..00000000000 --- a/src/devices/bus/heathzenith/h89/cards.h +++ /dev/null @@ -1,18 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:R. Belmont -/*************************************************************************** - - Heath/Zenith H-89 and Z-90 cards - -***************************************************************************/ - -#ifndef MAME_BUS_HEATHZENITH_H89_CARDS_H -#define MAME_BUS_HEATHZENITH_H89_CARDS_H - -#pragma once - -void h89_right_cards(device_slot_interface &device) ATTR_COLD; -void h89_right_cards_mms(device_slot_interface &device) ATTR_COLD; -void h89_right_p506_cards(device_slot_interface &device) ATTR_COLD; - -#endif // MAME_BUS_HEATHZENITH_H89_CARDS_H diff --git a/src/devices/bus/heathzenith/h89/h89bus.cpp b/src/devices/bus/heathzenith/h89/h89bus.cpp index 1b05c49e480..8bff638a3c8 100644 --- a/src/devices/bus/heathzenith/h89/h89bus.cpp +++ b/src/devices/bus/heathzenith/h89/h89bus.cpp @@ -150,9 +150,6 @@ h89bus_device::h89bus_device(const machine_config &mconfig, device_type type, co m_out_int3_cb(*this), m_out_int4_cb(*this), m_out_int5_cb(*this), - m_out_fdcirq_cb(*this), - m_out_fdcdrq_cb(*this), - m_out_blockirq_cb(*this), m_out_fmwe_cb(*this), m_out_wait_cb(*this), m_in_tlb_cb(*this, 0), @@ -324,21 +321,6 @@ void h89bus_device::set_int5_line(int state) m_out_int5_cb(state); } -void h89bus_device::set_fdcirq_line(int state) -{ - m_out_fdcirq_cb(state); -} - -void h89bus_device::set_fdcdrq_line(int state) -{ - m_out_fdcdrq_cb(state); -} - -void h89bus_device::set_blockirq_line(int state) -{ - m_out_blockirq_cb(state); -} - void h89bus_device::set_fmwe_line(int state) { m_out_fmwe_cb(state); diff --git a/src/devices/bus/heathzenith/h89/h89bus.h b/src/devices/bus/heathzenith/h89/h89bus.h index 8befec480bb..0cfe29da10a 100644 --- a/src/devices/bus/heathzenith/h89/h89bus.h +++ b/src/devices/bus/heathzenith/h89/h89bus.h @@ -149,9 +149,6 @@ public: void set_slot_int3(int state); void set_slot_int4(int state); void set_slot_int5(int state); - void set_slot_fdcirq(int state); - void set_slot_fdcdrq(int state); - void set_slot_blockirq(int state); void set_slot_fmwe(int state); void set_slot_wait(int state); int get_io0(); @@ -304,9 +301,6 @@ public: auto out_int3_callback() { return m_out_int3_cb.bind(); } auto out_int4_callback() { return m_out_int4_cb.bind(); } auto out_int5_callback() { return m_out_int5_cb.bind(); } - auto out_fdcirq_callback() { return m_out_fdcirq_cb.bind(); } - auto out_fdcdrq_callback() { return m_out_fdcdrq_cb.bind(); } - auto out_blockirq_callback() { return m_out_blockirq_cb.bind(); } auto out_fmwe_callback() { return m_out_fmwe_cb.bind(); } auto out_wait_callback() { return m_out_wait_cb.bind(); } auto in_tlb_callback() { return m_in_tlb_cb.bind(); } @@ -329,9 +323,6 @@ protected: void set_int3_line(int state); void set_int4_line(int state); void set_int5_line(int state); - void set_fdcirq_line(int state); - void set_fdcdrq_line(int state); - void set_blockirq_line(int state); void set_fmwe_line(int state); void set_wait_line(int state); u8 read_gpp(); @@ -343,7 +334,7 @@ protected: int m_io0, m_io1, m_mem0, m_mem1; private: - devcb_write_line m_out_int3_cb, m_out_int4_cb, m_out_int5_cb, m_out_fdcirq_cb, m_out_fdcdrq_cb, m_out_blockirq_cb; + devcb_write_line m_out_int3_cb, m_out_int4_cb, m_out_int5_cb; devcb_write_line m_out_fmwe_cb, m_out_wait_cb; devcb_read8 m_in_tlb_cb, m_in_nmi_cb, m_in_gpp_cb; devcb_write8 m_out_tlb_cb, m_out_nmi_cb, m_out_gpp_cb; @@ -390,21 +381,6 @@ inline void device_h89bus_right_card_interface::set_slot_int5(int state) h89bus().set_int5_line(state); } -inline void device_h89bus_right_card_interface::set_slot_fdcirq(int state) -{ - h89bus().set_fdcirq_line(state); -} - -inline void device_h89bus_right_card_interface::set_slot_fdcdrq(int state) -{ - h89bus().set_fdcdrq_line(state); -} - -inline void device_h89bus_right_card_interface::set_slot_blockirq(int state) -{ - h89bus().set_blockirq_line(state); -} - inline void device_h89bus_right_card_interface::set_slot_fmwe(int state) { if (m_p506_signals) diff --git a/src/devices/bus/heathzenith/h89/intr_cntrl.cpp b/src/devices/bus/heathzenith/h89/intr_cntrl.cpp new file mode 100644 index 00000000000..961d2662bb1 --- /dev/null +++ b/src/devices/bus/heathzenith/h89/intr_cntrl.cpp @@ -0,0 +1,278 @@ +// license:BSD-3-Clause +// copyright-holders:Mark Garlanger +/*************************************************************************** + + Heathkit Interrupt controller for H89 + +****************************************************************************/ + +#include "emu.h" + +#include "intr_cntrl.h" + +DEFINE_DEVICE_TYPE(HEATH_INTR_CNTRL, heath_intr_cntrl, "heath_intr_cntrl", "Heath H/Z-89 Interrupt Controller"); +DEFINE_DEVICE_TYPE(HEATH_Z37_INTR_CNTRL, z37_intr_cntrl, "heath_z37_intr_cntrl", "Heath H/Z-89 with Z-37 Interrupt Controller"); +DEFINE_DEVICE_TYPE(HEATH_MMS_INTR_CNTRL, mms_intr_cntrl, "heath_mms_intr_cntrl", "Heath H/Z-89 with MMS Interrupt Controller"); + +DEFINE_DEVICE_TYPE(HEATH_INTR_SOCKET, heath_intr_socket, "heath_intr_socket", "Heath Interrupt Socket"); + +/** + * Heath interrupt interface + */ +device_heath_intr_interface::device_heath_intr_interface(const machine_config &mconfig, device_t &device) : + device_interface(device, "heathintrdevice"), + m_socket(dynamic_cast(device.owner())) +{ +} + +/** + * Original Heath interrrupt controller + * + */ +heath_intr_cntrl::heath_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): + heath_intr_cntrl(mconfig, HEATH_INTR_CNTRL, tag, owner, clock) +{ +} + +heath_intr_cntrl::heath_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock): + device_t(mconfig, type, tag, owner, 0), + device_heath_intr_interface(mconfig, *this) +{ +} + +void heath_intr_cntrl::device_start() +{ + save_item(NAME(m_intr_lines)); + + m_intr_lines = 0; +} + +void heath_intr_cntrl::update_intr_line() +{ + if (m_socket) + { + m_socket->raise_irq((m_intr_lines == 0) ? 0 : 1); + } +} + +void heath_intr_cntrl::set_irq_level(u8 level, int data) +{ + // only 0 to 7 is valid + level &= 0x7; + + if (data == 0) + { + m_intr_lines &= ~(1 << level); + } + else + { + m_intr_lines |= 1 << level; + } + + update_intr_line(); +} + +u8 heath_intr_cntrl::get_instruction() +{ + + // determine top priority instruction + if (!m_intr_lines) + { + // should not occur. + // NO-OP ? + logerror("get instruct: bad m_intr_lines\n"); + + return 0x00; + } + + // ideally this would be handled with a function like ffs() + u8 level = 0; + u8 mask = 0x01; + + while (mask) + { + if (m_intr_lines & mask) + { + break; + } + level++; + mask <<= 1; + } + + if (level > 7) + { + logerror("bad level: %d\n", level); + } + + // return RST based on level + return 0xc7 | ((level & 0x7) << 3); +} + + +/** + * Base interrupt controller for soft-sectored controller. + * + */ +ss_intr_cntrl::ss_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock): + heath_intr_cntrl(mconfig, type, tag, owner, clock) +{ +} + +void ss_intr_cntrl::set_drq(int state) +{ + m_drq_raised = bool(state); + + update_intr_line(); +} + + +void ss_intr_cntrl::set_irq(int state) +{ + m_irq_raised = bool(state); + + update_intr_line(); +} + +void ss_intr_cntrl::device_start() +{ + heath_intr_cntrl::device_start(); + + save_item(NAME(m_drq_raised)); + save_item(NAME(m_irq_raised)); + + m_drq_raised = false; + m_irq_raised = false; +} + + +/** + * Interrupt controller for the Z37 soft-sectored controller. + * + * It will take control of the interrupt system and block all other + * interrupts while it is waiting for Z37 events. + */ +z37_intr_cntrl::z37_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): + ss_intr_cntrl(mconfig, HEATH_Z37_INTR_CNTRL, tag, owner, clock) +{ +} + +void z37_intr_cntrl::update_intr_line() +{ + m_socket->raise_irq( + (m_irq_raised || m_drq_raised || + (!m_intr_blocked && (m_intr_lines != 0))) ? 1 : 0); +} + +u8 z37_intr_cntrl::get_instruction() +{ + + if (m_drq_raised) + { + // EI + return 0xfb; + } + + if (m_irq_raised) + { + // RST 20H (Interrupt 4) + return 0xe7; + } + + if (!m_intr_blocked) + { + return heath_intr_cntrl::get_instruction(); + } + + // shouldn't get here - NO-OP? + logerror("Warning: z37 intr get_instruction: fd: %d dr: %d ib: %d\n", m_irq_raised, m_drq_raised, m_intr_blocked); + return 0x00; +} + +void z37_intr_cntrl::device_start() +{ + ss_intr_cntrl::device_start(); + + save_item(NAME(m_intr_blocked)); + + m_intr_blocked = false; +} + +void z37_intr_cntrl::block_interrupts(u8 data) +{ + m_intr_blocked = bool(data); + + update_intr_line(); +} + + +/** + * Interrupt controller for the mms 77316 soft-sectored controller. + * + */ +mms_intr_cntrl::mms_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): + ss_intr_cntrl(mconfig, HEATH_MMS_INTR_CNTRL, tag, owner, clock) +{ +} + +void mms_intr_cntrl::update_intr_line() +{ + m_socket->raise_irq((m_irq_raised || m_drq_raised || (m_intr_lines != 0)) ? 1 : 0); +} + +u8 mms_intr_cntrl::get_instruction() +{ + if (m_irq_raised) + { + // RST 30H (Interrupt 6) + return 0xf7; + } + + if (m_drq_raised) + { + // EI + return 0xfb; + } + + return heath_intr_cntrl::get_instruction(); +} + +void mms_intr_cntrl::device_start() +{ + ss_intr_cntrl::device_start(); +} + + +/** + * Heath Interrupt socket + * + * Allows choice of interrupt controllers for Heath 8-bit computers. + */ +heath_intr_socket::heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : + device_t(mconfig, HEATH_INTR_SOCKET, tag, owner, clock), + device_single_card_slot_interface(mconfig, *this), + m_irq_line(*this), + m_cntrl(nullptr) +{ +} + +heath_intr_socket::~heath_intr_socket() +{ +} + +void heath_intr_socket::device_start() +{ + m_cntrl = get_card_device(); +} + +IRQ_CALLBACK_MEMBER(heath_intr_socket::irq_callback) +{ + // assume NO-OP + u8 instr = 0x00; + + if (m_cntrl) + { + instr = m_cntrl->get_instruction(); + } + + return instr; +} diff --git a/src/devices/bus/heathzenith/h89/intr_cntrl.h b/src/devices/bus/heathzenith/h89/intr_cntrl.h new file mode 100644 index 00000000000..b4f9b76f840 --- /dev/null +++ b/src/devices/bus/heathzenith/h89/intr_cntrl.h @@ -0,0 +1,168 @@ +// license:BSD-3-Clause +// copyright-holders:Mark Garlanger +/*************************************************************************** + + Heathkit Interrupt Controllers + + Interrupt controllers for the Heath H89. + +****************************************************************************/ + +#ifndef MAME_BUS_HEATHZENITH_H89_INTR_CNTRL_H +#define MAME_BUS_HEATHZENITH_H89_INTR_CNTRL_H + +#pragma once + +class heath_intr_socket; + +class device_heath_intr_interface : public device_interface +{ +public: + virtual void set_irq_level(u8 level, int state) = 0; + + virtual void set_drq(int state) {} + virtual void set_irq(int state) {} + virtual void block_interrupts(u8 data) {} + +protected: + device_heath_intr_interface(const machine_config &mconfig, device_t &device); + + virtual u8 get_instruction() = 0; + + heath_intr_socket *const m_socket; + + friend heath_intr_socket; +}; + + +/** + * Heath original interrupt controller + * + */ +class heath_intr_cntrl : public device_t, + public device_heath_intr_interface +{ +public: + heath_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + virtual void set_irq_level(u8 level, int state) override; + +protected: + heath_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock = 0); + + virtual u8 get_instruction() override; + virtual void update_intr_line(); + + virtual void device_start() override ATTR_COLD; + + u8 m_intr_lines; +}; + + +/** + * Base interrupt controller for multiple soft-sectored controllers. + * + */ +class ss_intr_cntrl : public heath_intr_cntrl +{ +public: + virtual void set_drq(int state) override; + virtual void set_irq(int state) override; + +protected: + ss_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock = 0); + + virtual void device_start() override ATTR_COLD; + + bool m_drq_raised; + bool m_irq_raised; +}; + + +/** + * Interrupt controller when the Z37 soft-sectored controller is installed. + * + */ +class z37_intr_cntrl : public ss_intr_cntrl +{ +public: + z37_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + virtual void block_interrupts(u8 data) override; + +protected: + virtual u8 get_instruction() override; + virtual void update_intr_line() override; + + virtual void device_start() override ATTR_COLD; + + bool m_intr_blocked; +}; + + +/** + * Interrupt controller when the mms soft-sectored controller is installed. + * + */ +class mms_intr_cntrl : public ss_intr_cntrl +{ +public: + mms_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + +protected: + virtual u8 get_instruction() override; + virtual void update_intr_line() override; + + virtual void device_start() override ATTR_COLD; +}; + + +DECLARE_DEVICE_TYPE(HEATH_INTR_CNTRL, heath_intr_cntrl) +DECLARE_DEVICE_TYPE(HEATH_Z37_INTR_CNTRL, z37_intr_cntrl) +DECLARE_DEVICE_TYPE(HEATH_MMS_INTR_CNTRL, mms_intr_cntrl); + + +class heath_intr_socket : public device_t, + public device_single_card_slot_interface +{ +public: + + template + heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, T &&opts, const char *dflt, bool fixed = false) : + heath_intr_socket(mconfig, tag, owner, 0) + { + option_reset(); + opts(*this); + set_default_option(dflt); + set_fixed(fixed); + } + + heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + virtual ~heath_intr_socket(); + + auto irq_line_cb() { return m_irq_line.bind(); } + + // required operation + void set_irq_level(u8 level, int state) { if (m_cntrl) { m_cntrl->set_irq_level(level, state); }} + + IRQ_CALLBACK_MEMBER(irq_callback); + + void raise_irq(int state) { m_irq_line(state); } + + void set_irq(int state) { if (m_cntrl) { m_cntrl->set_irq(state); } } + void set_drq(int state) { if (m_cntrl) { m_cntrl->set_drq(state); } } + void block_interrupts(u8 data) { if (m_cntrl) { m_cntrl->block_interrupts(data); } } + +protected: + + virtual void device_start() override ATTR_COLD; + + devcb_write8 m_irq_line; + + device_heath_intr_interface *m_cntrl; +}; + + +DECLARE_DEVICE_TYPE(HEATH_INTR_SOCKET, heath_intr_socket) + +#endif // MAME_BUS_HEATHZENITH_H89_INTR_CNTRL_H diff --git a/src/devices/bus/heathzenith/h89/mms77316_fdc.cpp b/src/devices/bus/heathzenith/h89/mms77316_fdc.cpp index b0af15bdcea..87a1599d8a2 100644 --- a/src/devices/bus/heathzenith/h89/mms77316_fdc.cpp +++ b/src/devices/bus/heathzenith/h89/mms77316_fdc.cpp @@ -14,9 +14,6 @@ #include "mms77316_fdc.h" -#include "imagedev/floppy.h" -#include "machine/wd_fdc.h" - #define LOG_REG (1U << 1) // Shows register setup #define LOG_LINES (1U << 2) // Show control lines #define LOG_DRIVE (1U << 3) // Show drive select @@ -43,60 +40,13 @@ #define FUNCNAME __PRETTY_FUNCTION__ #endif -namespace { - -class mms77316_fdc_device : public device_t, public device_h89bus_right_card_interface -{ -public: - mms77316_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - - virtual void write(u8 select_lines, u8 offset, u8 data) override; - virtual u8 read(u8 select_lines, u8 offset) override; - -protected: - virtual void device_start() override ATTR_COLD; - virtual void device_reset() override ATTR_COLD; - virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; - - void ctrl_w(u8 val); - void data_w(u8 val); - u8 data_r(); - - void set_irq(int state); - void set_drq(int state); - - // Burst mode was required for a 2 MHz Z80 to handle 8" DD data rates. - // The typical irq/drq was too slow, this utilizes wait states to read the - // WD1797 data port once the drq line is high. - inline bool burst_mode_r() { return !m_drq_allowed; } - -private: - required_device m_fdc; - required_device_array m_floppies; - - bool m_irq_allowed; - bool m_drq_allowed; - - bool m_irq; - bool m_drq; - u32 m_drq_count; - - /// Bits set in cmd_ControlPort_c - static constexpr u8 ctrl_525DriveSel_c = 2; - static constexpr u8 ctrl_EnableIntReq_c = 3; - static constexpr u8 ctrl_EnableDrqInt_c = 5; - static constexpr u8 ctrl_SetMFMRecording_c = 6; - - static constexpr XTAL MASTER_CLOCK = XTAL(8'000'000); - static constexpr XTAL FIVE_IN_CLOCK = MASTER_CLOCK / 8; - static constexpr XTAL EIGHT_IN_CLOCK = MASTER_CLOCK / 4; -}; mms77316_fdc_device::mms77316_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): device_t(mconfig, H89BUS_MMS77316, tag, owner, 0), device_h89bus_right_card_interface(mconfig, *this), m_fdc(*this, "mms_fdc"), - m_floppies(*this, "mms_fdc:%u", 0U) + m_floppies(*this, "mms_fdc:%u", 0U), + m_intr_cntrl(*this, finder_base::DUMMY_TAG) { } @@ -117,13 +67,13 @@ void mms77316_fdc_device::ctrl_w(u8 val) if (m_irq_allowed) { - set_slot_fdcirq(m_irq); - set_slot_fdcdrq(m_drq); + m_intr_cntrl->set_irq(m_irq); + m_intr_cntrl->set_drq(m_drq); } else { - set_slot_fdcirq(CLEAR_LINE); - set_slot_fdcdrq(CLEAR_LINE); + m_intr_cntrl->set_irq(CLEAR_LINE); + m_intr_cntrl->set_drq(CLEAR_LINE); } LOGDRIVE("%s: floppydrive: %d, 5.25 in: %d\n", FUNCNAME, floppy_drive, five_in_drv); @@ -273,8 +223,8 @@ void mms77316_fdc_device::device_reset() m_irq = false; m_drq_count = 0; - set_slot_fdcirq(CLEAR_LINE); - set_slot_fdcdrq(CLEAR_LINE); + m_intr_cntrl->set_irq(CLEAR_LINE); + m_intr_cntrl->set_drq(CLEAR_LINE); set_slot_wait(CLEAR_LINE); for (int i = 0; i < 4; i++) @@ -355,7 +305,7 @@ void mms77316_fdc_device::set_irq(int state) m_drq_count = 0; } - set_slot_fdcirq(m_irq_allowed ? m_irq : CLEAR_LINE); + m_intr_cntrl->set_irq(m_irq_allowed ? m_irq : CLEAR_LINE); } void mms77316_fdc_device::set_drq(int state) @@ -373,14 +323,12 @@ void mms77316_fdc_device::set_drq(int state) set_slot_wait(CLEAR_LINE); } - set_slot_fdcdrq(m_drq_count == 0 ? m_drq : CLEAR_LINE); + m_intr_cntrl->set_drq(m_drq_count == 0 ? m_drq : CLEAR_LINE); } else { - set_slot_fdcdrq(m_drq_allowed ? m_drq : CLEAR_LINE); + m_intr_cntrl->set_drq(m_drq_allowed ? m_drq : CLEAR_LINE); } } -} // anonymous namespace - DEFINE_DEVICE_TYPE_PRIVATE(H89BUS_MMS77316, device_h89bus_right_card_interface, mms77316_fdc_device, "mms77316_fdc", "Magnolia MicroSystems 77316 Soft-sectored Controller"); diff --git a/src/devices/bus/heathzenith/h89/mms77316_fdc.h b/src/devices/bus/heathzenith/h89/mms77316_fdc.h index 699db267adf..04838c0fff6 100644 --- a/src/devices/bus/heathzenith/h89/mms77316_fdc.h +++ b/src/devices/bus/heathzenith/h89/mms77316_fdc.h @@ -13,6 +13,61 @@ #include "h89bus.h" +#include "imagedev/floppy.h" +#include "machine/wd_fdc.h" + +#include "bus/heathzenith/h89/intr_cntrl.h" + +class mms77316_fdc_device : public device_t, public device_h89bus_right_card_interface +{ +public: + mms77316_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + virtual void write(u8 select_lines, u8 offset, u8 data) override; + virtual u8 read(u8 select_lines, u8 offset) override; + + template void set_intr_cntrl(T &&tag) { m_intr_cntrl.set_tag(std::forward(tag)); } + +protected: + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + + void ctrl_w(u8 val); + void data_w(u8 val); + u8 data_r(); + + void set_irq(int state); + void set_drq(int state); + + // Burst mode was required for a 2 MHz Z80 to handle 8" DD data rates. + // The typical irq/drq was too slow, this utilizes wait states to read the + // WD1797 data port once the drq line is high. + inline bool burst_mode_r() { return !m_drq_allowed; } + +private: + required_device m_fdc; + required_device_array m_floppies; + required_device m_intr_cntrl; + + bool m_irq_allowed; + bool m_drq_allowed; + + bool m_irq; + bool m_drq; + u32 m_drq_count; + + /// Bits set in cmd_ControlPort_c + static constexpr u8 ctrl_525DriveSel_c = 2; + static constexpr u8 ctrl_EnableIntReq_c = 3; + static constexpr u8 ctrl_EnableDrqInt_c = 5; + static constexpr u8 ctrl_SetMFMRecording_c = 6; + + static constexpr XTAL MASTER_CLOCK = XTAL(8'000'000); + static constexpr XTAL FIVE_IN_CLOCK = MASTER_CLOCK / 8; + static constexpr XTAL EIGHT_IN_CLOCK = MASTER_CLOCK / 4; +}; + DECLARE_DEVICE_TYPE(H89BUS_MMS77316, device_h89bus_right_card_interface) #endif // MAME_BUS_HEATHZENITH_H89_MMS77316_FDC_H diff --git a/src/devices/bus/heathzenith/h89/z37_fdc.cpp b/src/devices/bus/heathzenith/h89/z37_fdc.cpp index 41dc53b4b8a..af0c4d9ae79 100644 --- a/src/devices/bus/heathzenith/h89/z37_fdc.cpp +++ b/src/devices/bus/heathzenith/h89/z37_fdc.cpp @@ -35,65 +35,16 @@ #define FUNCNAME __PRETTY_FUNCTION__ #endif -namespace { - -class h89bus_z37_device : public device_t, public device_h89bus_right_card_interface -{ -public: - h89bus_z37_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - - virtual void write(u8 select_lines, u8 offset, u8 data) override; - virtual u8 read(u8 select_lines, u8 offset) override; - -protected: - virtual void device_start() override ATTR_COLD; - virtual void device_reset() override ATTR_COLD; - virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; - - void ctrl_w(u8 val); - - void intf_w(u8 val); - - void cmd_w(u8 val); - u8 stat_r(); - - void data_w(u8 val); - u8 data_r(); - - void set_irq(int state); - void set_drq(int state); - -private: - required_device m_fdc; - required_device_array m_floppies; - - bool m_irq_allowed; - bool m_drq_allowed; - bool m_access_track_sector; - - /// Bits set in cmd_ControlPort_c - DK.CON - static constexpr u8 ctrl_EnableIntReq_c = 0; - static constexpr u8 ctrl_EnableDrqInt_c = 1; - static constexpr u8 ctrl_SetMFMRecording_c = 2; - static constexpr u8 ctrl_MotorsOn_c = 3; - static constexpr u8 ctrl_Drive_0_c = 4; - static constexpr u8 ctrl_Drive_1_c = 5; - static constexpr u8 ctrl_Drive_2_c = 6; - static constexpr u8 ctrl_Drive_3_c = 7; - - /// Bits to set alternate registers on InterfaceControl_c - DK.INT - static constexpr u8 if_SelectSectorTrack_c = 0; -}; h89bus_z37_device::h89bus_z37_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): device_t(mconfig, H89BUS_Z37, tag, owner, 0), device_h89bus_right_card_interface(mconfig, *this), m_fdc(*this, "z37_fdc"), - m_floppies(*this, "z37_fdc:%u", 0U) + m_floppies(*this, "z37_fdc:%u", 0U), + m_intr_cntrl(*this, finder_base::DUMMY_TAG) { } - void h89bus_z37_device::ctrl_w(u8 val) { bool motor_on = bool(BIT(val, ctrl_MotorsOn_c)); @@ -107,12 +58,12 @@ void h89bus_z37_device::ctrl_w(u8 val) if (m_drq_allowed) { - set_slot_blockirq(1); + m_intr_cntrl->block_interrupts(1); } else { - set_slot_blockirq(0); - set_slot_fdcdrq(0); + m_intr_cntrl->block_interrupts(0); + m_intr_cntrl->set_drq(0); } if (BIT(val, ctrl_Drive_0_c)) @@ -246,9 +197,9 @@ void h89bus_z37_device::device_reset() m_drq_allowed = false; m_access_track_sector = false; - set_slot_fdcirq(0); - set_slot_fdcdrq(0); - set_slot_blockirq(0); + m_intr_cntrl->set_irq(0); + m_intr_cntrl->set_drq(0); + m_intr_cntrl->block_interrupts(0); } static void z37_floppies(device_slot_interface &device) @@ -285,16 +236,14 @@ void h89bus_z37_device::set_irq(int state) { LOGLINES("set irq, allowed: %d state: %d\n", m_irq_allowed, state); - set_slot_fdcirq(m_irq_allowed ? state : CLEAR_LINE); + m_intr_cntrl->set_irq(m_irq_allowed ? state : CLEAR_LINE); } void h89bus_z37_device::set_drq(int state) { LOGLINES("set drq, allowed: %d state: %d\n", m_drq_allowed, state); - set_slot_fdcdrq(m_drq_allowed ? state : CLEAR_LINE); + m_intr_cntrl->set_drq(m_drq_allowed ? state : CLEAR_LINE); } -} // anonymous namespace - DEFINE_DEVICE_TYPE_PRIVATE(H89BUS_Z37, device_h89bus_right_card_interface, h89bus_z37_device, "h89_z37", "Heathkit Z-37 Floppy Disk Controller"); diff --git a/src/devices/bus/heathzenith/h89/z37_fdc.h b/src/devices/bus/heathzenith/h89/z37_fdc.h index 045ccabc74a..ad2e52027be 100644 --- a/src/devices/bus/heathzenith/h89/z37_fdc.h +++ b/src/devices/bus/heathzenith/h89/z37_fdc.h @@ -13,6 +13,59 @@ #include "h89bus.h" +#include "bus/heathzenith/h89/intr_cntrl.h" + +class h89bus_z37_device : public device_t, public device_h89bus_right_card_interface +{ +public: + h89bus_z37_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + virtual void write(u8 select_lines, u8 offset, u8 data) override; + virtual u8 read(u8 select_lines, u8 offset) override; + + template void set_intr_cntrl(T &&tag) { m_intr_cntrl.set_tag(std::forward(tag)); } + +protected: + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + + void ctrl_w(u8 val); + + void intf_w(u8 val); + + void cmd_w(u8 val); + u8 stat_r(); + + void data_w(u8 val); + u8 data_r(); + + void set_irq(int state); + void set_drq(int state); + +private: + required_device m_fdc; + required_device_array m_floppies; + required_device m_intr_cntrl; + + bool m_irq_allowed; + bool m_drq_allowed; + bool m_access_track_sector; + + /// Bits set in cmd_ControlPort_c - DK.CON + static constexpr u8 ctrl_EnableIntReq_c = 0; + static constexpr u8 ctrl_EnableDrqInt_c = 1; + static constexpr u8 ctrl_SetMFMRecording_c = 2; + static constexpr u8 ctrl_MotorsOn_c = 3; + static constexpr u8 ctrl_Drive_0_c = 4; + static constexpr u8 ctrl_Drive_1_c = 5; + static constexpr u8 ctrl_Drive_2_c = 6; + static constexpr u8 ctrl_Drive_3_c = 7; + + /// Bits to set alternate registers on InterfaceControl_c - DK.INT + static constexpr u8 if_SelectSectorTrack_c = 0; +}; + DECLARE_DEVICE_TYPE(H89BUS_Z37, device_h89bus_right_card_interface) #endif // MAME_BUS_HEATHZENITH_H89_Z37_FDC_H diff --git a/src/mame/heathzenith/h89.cpp b/src/mame/heathzenith/h89.cpp index 04029c902ee..19300b532e9 100644 --- a/src/mame/heathzenith/h89.cpp +++ b/src/mame/heathzenith/h89.cpp @@ -43,12 +43,18 @@ #include "emu.h" -#include "intr_cntrl.h" - #include "bus/heathzenith/h19/tlb.h" #include "bus/heathzenith/h89/h89bus.h" -#include "bus/heathzenith/h89/cards.h" +#include "bus/heathzenith/h89/intr_cntrl.h" +#include "bus/heathzenith/h89/cdr_fdc_880h.h" +#include "bus/heathzenith/h89/h_88_3.h" +#include "bus/heathzenith/h89/h_88_5.h" +#include "bus/heathzenith/h89/mms77316_fdc.h" #include "bus/heathzenith/h89/sigmasoft_parallel_port.h" +#include "bus/heathzenith/h89/sigmasoft_sound.h" +#include "bus/heathzenith/h89/we_pullup.h" +#include "bus/heathzenith/h89/z_89_11.h" +#include "bus/heathzenith/h89/z37_fdc.h" #include "cpu/z80/z80.h" #include "machine/ins8250.h" @@ -161,6 +167,9 @@ protected: template void slot_irq(int state); void h89_left_cards(device_slot_interface &device); + void h89_right_cards(device_slot_interface &device); + void h89_right_cards_mms(device_slot_interface &device); + void h89_right_p506_cards(device_slot_interface &device); }; /** @@ -934,6 +943,39 @@ void h89_base_state::h89_left_cards(device_slot_interface &device) }); } +void h89_base_state::h89_right_cards(device_slot_interface &device) +{ + device.option_add("cdr_fdc", H89BUS_CDR_FDC_880H); + device.option_add("h_88_3", H89BUS_H_88_3); + device.option_add("ha_88_3", H89BUS_HA_88_3); + device.option_add("h_88_5", H89BUS_H_88_5); + device.option_add("ss_snd", H89BUS_SIGMASOFT_SND); + device.option_add("z_89_11", H89BUS_Z_89_11); + + device.option_add("z37fdc", H89BUS_Z37).machine_config( + [this](device_t *device) + { + downcast(*device).set_intr_cntrl(m_intr_socket); + }); +} + +void h89_base_state::h89_right_cards_mms(device_slot_interface &device) +{ + h89_right_cards(device); + device.option_add("mms77316", H89BUS_MMS77316).machine_config( + [this](device_t *device) + { + downcast(*device).set_intr_cntrl(m_intr_socket); + }); +} + +void h89_base_state::h89_right_p506_cards(device_slot_interface &device) +{ + device.option_add("h_88_3", H89BUS_H_88_3); + device.option_add("ha_88_3", H89BUS_HA_88_3); + device.option_add("ss_snd", H89BUS_SIGMASOFT_SND); + device.option_add("we_pullup", H89BUS_WE_PULLUP); +} void h89_base_state::h89_base(machine_config &config) { @@ -979,16 +1021,13 @@ void h89_base_state::h89_base(machine_config &config) m_h89bus->out_int4_callback().set(FUNC(h89_base_state::slot_irq<4>)); m_h89bus->out_int5_callback().set(FUNC(h89_base_state::slot_irq<5>)); m_h89bus->out_wait_callback().set(FUNC(h89_base_state::set_wait_state)); - m_h89bus->out_fdcirq_callback().set(m_intr_socket, FUNC(heath_intr_socket::set_irq)); - m_h89bus->out_fdcdrq_callback().set(m_intr_socket, FUNC(heath_intr_socket::set_drq)); - m_h89bus->out_blockirq_callback().set(m_intr_socket, FUNC(heath_intr_socket::block_interrupts)); m_h89bus->out_fmwe_callback().set(FUNC(h89_base_state::set_fmwe)); H89BUS_LEFT_SLOT(config, "p501", "h89bus", [this](device_slot_interface &device) { h89_left_cards(device); }, nullptr); H89BUS_LEFT_SLOT(config, "p502", "h89bus", [this](device_slot_interface &device) { h89_left_cards(device); }, nullptr); H89BUS_LEFT_SLOT(config, "p503", "h89bus", [this](device_slot_interface &device) { h89_left_cards(device); }, nullptr); - H89BUS_RIGHT_SLOT(config, "p504", "h89bus", h89_right_cards, nullptr); - H89BUS_RIGHT_SLOT(config, "p505", "h89bus", h89_right_cards, "ha_88_3"); - H89BUS_RIGHT_SLOT(config, "p506", "h89bus", h89_right_p506_cards, "we_pullup").set_p506_signalling(true); + H89BUS_RIGHT_SLOT(config, "p504", "h89bus", [this](device_slot_interface &device) { h89_right_cards(device); }, nullptr); + H89BUS_RIGHT_SLOT(config, "p505", "h89bus", [this](device_slot_interface &device) { h89_right_cards(device); }, "ha_88_3"); + H89BUS_RIGHT_SLOT(config, "p506", "h89bus", [this](device_slot_interface &device) { h89_right_p506_cards(device); }, "we_pullup").set_p506_signalling(true); // H89 interrupt interval is 2mSec TIMER(config, "irq_timer", 0).configure_periodic(FUNC(h89_base_state::h89_irq_timer), attotime::from_msec(2)); @@ -1002,7 +1041,7 @@ void h88_state::h88(machine_config &config) m_intr_socket->set_default_option("original"); m_intr_socket->set_fixed(true); - H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", h89_right_cards, "h_88_5"); + H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", [this](device_slot_interface &device) { h89_right_cards(device); }, "h_88_5"); } void h89_state::h89(machine_config &config) @@ -1013,7 +1052,7 @@ void h89_state::h89(machine_config &config) m_intr_socket->set_default_option("h37"); m_intr_socket->set_fixed(true); - H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", h89_right_cards, "z37fdc"); + H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", [this](device_slot_interface &device) { h89_right_cards(device); }, "z37fdc"); } void h89_cdr_state::h89_cdr(machine_config &config) @@ -1024,7 +1063,7 @@ void h89_cdr_state::h89_cdr(machine_config &config) m_intr_socket->set_default_option("original"); m_intr_socket->set_fixed(true); - H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", h89_right_cards, "cdr_fdc"); + H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", [this](device_slot_interface &device) { h89_right_cards(device); }, "cdr_fdc"); } void h89_mms_state::h89_mms(machine_config &config) @@ -1036,9 +1075,8 @@ void h89_mms_state::h89_mms(machine_config &config) m_h89bus->out_gpp_callback().set(FUNC(h89_mms_state::port_f2_mms_w)); // the card selection is different with the MMS mapping PROM - H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", h89_right_cards_mms, "mms77316"); - H89BUS_RIGHT_SLOT(config.replace(), "p505", "h89bus", h89_right_cards_mms, "ha_88_3"); - H89BUS_RIGHT_SLOT(config.replace(), "p506", "h89bus", h89_right_cards_mms, nullptr).set_p506_signalling(true); + H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", [this](device_slot_interface &device) { h89_right_cards_mms(device); }, "mms77316"); + H89BUS_RIGHT_SLOT(config.replace(), "p505", "h89bus", [this](device_slot_interface &device) { h89_right_cards_mms(device); }, "ha_88_3"); m_intr_socket->set_default_option("mms"); m_intr_socket->set_fixed(true); diff --git a/src/mame/heathzenith/intr_cntrl.cpp b/src/mame/heathzenith/intr_cntrl.cpp deleted file mode 100644 index 961d2662bb1..00000000000 --- a/src/mame/heathzenith/intr_cntrl.cpp +++ /dev/null @@ -1,278 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Mark Garlanger -/*************************************************************************** - - Heathkit Interrupt controller for H89 - -****************************************************************************/ - -#include "emu.h" - -#include "intr_cntrl.h" - -DEFINE_DEVICE_TYPE(HEATH_INTR_CNTRL, heath_intr_cntrl, "heath_intr_cntrl", "Heath H/Z-89 Interrupt Controller"); -DEFINE_DEVICE_TYPE(HEATH_Z37_INTR_CNTRL, z37_intr_cntrl, "heath_z37_intr_cntrl", "Heath H/Z-89 with Z-37 Interrupt Controller"); -DEFINE_DEVICE_TYPE(HEATH_MMS_INTR_CNTRL, mms_intr_cntrl, "heath_mms_intr_cntrl", "Heath H/Z-89 with MMS Interrupt Controller"); - -DEFINE_DEVICE_TYPE(HEATH_INTR_SOCKET, heath_intr_socket, "heath_intr_socket", "Heath Interrupt Socket"); - -/** - * Heath interrupt interface - */ -device_heath_intr_interface::device_heath_intr_interface(const machine_config &mconfig, device_t &device) : - device_interface(device, "heathintrdevice"), - m_socket(dynamic_cast(device.owner())) -{ -} - -/** - * Original Heath interrrupt controller - * - */ -heath_intr_cntrl::heath_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): - heath_intr_cntrl(mconfig, HEATH_INTR_CNTRL, tag, owner, clock) -{ -} - -heath_intr_cntrl::heath_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock): - device_t(mconfig, type, tag, owner, 0), - device_heath_intr_interface(mconfig, *this) -{ -} - -void heath_intr_cntrl::device_start() -{ - save_item(NAME(m_intr_lines)); - - m_intr_lines = 0; -} - -void heath_intr_cntrl::update_intr_line() -{ - if (m_socket) - { - m_socket->raise_irq((m_intr_lines == 0) ? 0 : 1); - } -} - -void heath_intr_cntrl::set_irq_level(u8 level, int data) -{ - // only 0 to 7 is valid - level &= 0x7; - - if (data == 0) - { - m_intr_lines &= ~(1 << level); - } - else - { - m_intr_lines |= 1 << level; - } - - update_intr_line(); -} - -u8 heath_intr_cntrl::get_instruction() -{ - - // determine top priority instruction - if (!m_intr_lines) - { - // should not occur. - // NO-OP ? - logerror("get instruct: bad m_intr_lines\n"); - - return 0x00; - } - - // ideally this would be handled with a function like ffs() - u8 level = 0; - u8 mask = 0x01; - - while (mask) - { - if (m_intr_lines & mask) - { - break; - } - level++; - mask <<= 1; - } - - if (level > 7) - { - logerror("bad level: %d\n", level); - } - - // return RST based on level - return 0xc7 | ((level & 0x7) << 3); -} - - -/** - * Base interrupt controller for soft-sectored controller. - * - */ -ss_intr_cntrl::ss_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock): - heath_intr_cntrl(mconfig, type, tag, owner, clock) -{ -} - -void ss_intr_cntrl::set_drq(int state) -{ - m_drq_raised = bool(state); - - update_intr_line(); -} - - -void ss_intr_cntrl::set_irq(int state) -{ - m_irq_raised = bool(state); - - update_intr_line(); -} - -void ss_intr_cntrl::device_start() -{ - heath_intr_cntrl::device_start(); - - save_item(NAME(m_drq_raised)); - save_item(NAME(m_irq_raised)); - - m_drq_raised = false; - m_irq_raised = false; -} - - -/** - * Interrupt controller for the Z37 soft-sectored controller. - * - * It will take control of the interrupt system and block all other - * interrupts while it is waiting for Z37 events. - */ -z37_intr_cntrl::z37_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): - ss_intr_cntrl(mconfig, HEATH_Z37_INTR_CNTRL, tag, owner, clock) -{ -} - -void z37_intr_cntrl::update_intr_line() -{ - m_socket->raise_irq( - (m_irq_raised || m_drq_raised || - (!m_intr_blocked && (m_intr_lines != 0))) ? 1 : 0); -} - -u8 z37_intr_cntrl::get_instruction() -{ - - if (m_drq_raised) - { - // EI - return 0xfb; - } - - if (m_irq_raised) - { - // RST 20H (Interrupt 4) - return 0xe7; - } - - if (!m_intr_blocked) - { - return heath_intr_cntrl::get_instruction(); - } - - // shouldn't get here - NO-OP? - logerror("Warning: z37 intr get_instruction: fd: %d dr: %d ib: %d\n", m_irq_raised, m_drq_raised, m_intr_blocked); - return 0x00; -} - -void z37_intr_cntrl::device_start() -{ - ss_intr_cntrl::device_start(); - - save_item(NAME(m_intr_blocked)); - - m_intr_blocked = false; -} - -void z37_intr_cntrl::block_interrupts(u8 data) -{ - m_intr_blocked = bool(data); - - update_intr_line(); -} - - -/** - * Interrupt controller for the mms 77316 soft-sectored controller. - * - */ -mms_intr_cntrl::mms_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): - ss_intr_cntrl(mconfig, HEATH_MMS_INTR_CNTRL, tag, owner, clock) -{ -} - -void mms_intr_cntrl::update_intr_line() -{ - m_socket->raise_irq((m_irq_raised || m_drq_raised || (m_intr_lines != 0)) ? 1 : 0); -} - -u8 mms_intr_cntrl::get_instruction() -{ - if (m_irq_raised) - { - // RST 30H (Interrupt 6) - return 0xf7; - } - - if (m_drq_raised) - { - // EI - return 0xfb; - } - - return heath_intr_cntrl::get_instruction(); -} - -void mms_intr_cntrl::device_start() -{ - ss_intr_cntrl::device_start(); -} - - -/** - * Heath Interrupt socket - * - * Allows choice of interrupt controllers for Heath 8-bit computers. - */ -heath_intr_socket::heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : - device_t(mconfig, HEATH_INTR_SOCKET, tag, owner, clock), - device_single_card_slot_interface(mconfig, *this), - m_irq_line(*this), - m_cntrl(nullptr) -{ -} - -heath_intr_socket::~heath_intr_socket() -{ -} - -void heath_intr_socket::device_start() -{ - m_cntrl = get_card_device(); -} - -IRQ_CALLBACK_MEMBER(heath_intr_socket::irq_callback) -{ - // assume NO-OP - u8 instr = 0x00; - - if (m_cntrl) - { - instr = m_cntrl->get_instruction(); - } - - return instr; -} diff --git a/src/mame/heathzenith/intr_cntrl.h b/src/mame/heathzenith/intr_cntrl.h deleted file mode 100644 index e0e9c3966f7..00000000000 --- a/src/mame/heathzenith/intr_cntrl.h +++ /dev/null @@ -1,168 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Mark Garlanger -/*************************************************************************** - - Heathkit Interrupt Controllers - - Interrupt controllers for the Heath H89. - -****************************************************************************/ - -#ifndef MAME_HEATHZENITH_INTR_CNTRL_H -#define MAME_HEATHZENITH_INTR_CNTRL_H - -#pragma once - -class heath_intr_socket; - -class device_heath_intr_interface : public device_interface -{ -public: - virtual void set_irq_level(u8 level, int state) = 0; - - virtual void set_drq(int state) {} - virtual void set_irq(int state) {} - virtual void block_interrupts(u8 data) {} - -protected: - device_heath_intr_interface(const machine_config &mconfig, device_t &device); - - virtual u8 get_instruction() = 0; - - heath_intr_socket *const m_socket; - - friend heath_intr_socket; -}; - - -/** - * Heath original interrupt controller - * - */ -class heath_intr_cntrl : public device_t, - public device_heath_intr_interface -{ -public: - heath_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - - virtual void set_irq_level(u8 level, int state) override; - -protected: - heath_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock = 0); - - virtual u8 get_instruction() override; - virtual void update_intr_line(); - - virtual void device_start() override ATTR_COLD; - - u8 m_intr_lines; -}; - - -/** - * Base interrupt controller for multiple soft-sectored controllers. - * - */ -class ss_intr_cntrl : public heath_intr_cntrl -{ -public: - virtual void set_drq(int state) override; - virtual void set_irq(int state) override; - -protected: - ss_intr_cntrl(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock = 0); - - virtual void device_start() override ATTR_COLD; - - bool m_drq_raised; - bool m_irq_raised; -}; - - -/** - * Interrupt controller when the Z37 soft-sectored controller is installed. - * - */ -class z37_intr_cntrl : public ss_intr_cntrl -{ -public: - z37_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - - virtual void block_interrupts(u8 data) override; - -protected: - virtual u8 get_instruction() override; - virtual void update_intr_line() override; - - virtual void device_start() override ATTR_COLD; - - bool m_intr_blocked; -}; - - -/** - * Interrupt controller when the mms soft-sectored controller is installed. - * - */ -class mms_intr_cntrl : public ss_intr_cntrl -{ -public: - mms_intr_cntrl(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - -protected: - virtual u8 get_instruction() override; - virtual void update_intr_line() override; - - virtual void device_start() override ATTR_COLD; -}; - - -DECLARE_DEVICE_TYPE(HEATH_INTR_CNTRL, heath_intr_cntrl) -DECLARE_DEVICE_TYPE(HEATH_Z37_INTR_CNTRL, z37_intr_cntrl) -DECLARE_DEVICE_TYPE(HEATH_MMS_INTR_CNTRL, mms_intr_cntrl); - - -class heath_intr_socket : public device_t, - public device_single_card_slot_interface -{ -public: - - template - heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, T &&opts, const char *dflt, bool fixed = false) : - heath_intr_socket(mconfig, tag, owner, 0) - { - option_reset(); - opts(*this); - set_default_option(dflt); - set_fixed(fixed); - } - - heath_intr_socket(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); - virtual ~heath_intr_socket(); - - auto irq_line_cb() { return m_irq_line.bind(); } - - // required operation - void set_irq_level(u8 level, int state) { if (m_cntrl) { m_cntrl->set_irq_level(level, state); }} - - IRQ_CALLBACK_MEMBER(irq_callback); - - void raise_irq(int state) { m_irq_line(state); } - - void set_irq(int state) { if (m_cntrl) { m_cntrl->set_irq(state); } } - void set_drq(int state) { if (m_cntrl) { m_cntrl->set_drq(state); } } - void block_interrupts(u8 data) { if (m_cntrl) { m_cntrl->block_interrupts(data); } } - -protected: - - virtual void device_start() override ATTR_COLD; - - devcb_write8 m_irq_line; - - device_heath_intr_interface *m_cntrl; -}; - - -DECLARE_DEVICE_TYPE(HEATH_INTR_SOCKET, heath_intr_socket) - -#endif // MAME_HEATHZENITH_H89_INTR_CNTRL_H -- cgit v1.2.3