From 698b634196ff8ea959c8c466e6afe5bf1a0922f4 Mon Sep 17 00:00:00 2001 From: 987123879113 <63495610+987123879113@users.noreply.github.com> Date: Sun, 19 May 2024 03:00:12 +0900 Subject: konami/konamigv.cpp, konami/konamigq.cpp, konami/twinkle.cpp: Process SCSI DMA transfers instantaneously. (#12375) * Avoids issues described in MT08860. * Also added TODO notes about implementing correct DMA timings. --- src/mame/konami/konamigq.cpp | 12 +++++------- src/mame/konami/konamigv.cpp | 12 +++++------- src/mame/konami/twinkle.cpp | 12 +++++------- 3 files changed, 15 insertions(+), 21 deletions(-) diff --git a/src/mame/konami/konamigq.cpp b/src/mame/konami/konamigq.cpp index 004f6a105cb..aa617c2d4e9 100644 --- a/src/mame/konami/konamigq.cpp +++ b/src/mame/konami/konamigq.cpp @@ -287,7 +287,7 @@ void konamigq_state::scsi_dma_read( uint32_t *p_n_psxram, uint32_t n_address, in m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = false; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size ) @@ -296,12 +296,13 @@ void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, i m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = true; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer) { - if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) + // TODO: Figure out proper DMA timings + while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) { if (m_dma_is_write) m_ncr53cf96->dma_w(util::little_endian_cast(m_dma_data_ptr)[m_dma_offset]); @@ -311,15 +312,12 @@ TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer) m_dma_offset++; m_dma_size--; } - - if (m_dma_requested && m_dma_size > 0) - m_dma_timer->adjust(attotime::from_usec(10)); } void konamigq_state::scsi_drq(int state) { if (!m_dma_requested && state) - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); m_dma_requested = state; } diff --git a/src/mame/konami/konamigv.cpp b/src/mame/konami/konamigv.cpp index 0935ce6c773..0c45f806844 100644 --- a/src/mame/konami/konamigv.cpp +++ b/src/mame/konami/konamigv.cpp @@ -455,7 +455,7 @@ void konamigv_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = false; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size) @@ -464,12 +464,13 @@ void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, in m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = true; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer) { - if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) + // TODO: Figure out proper DMA timings + while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) { if (m_dma_is_write) m_ncr53cf96->dma_w(util::little_endian_cast(m_dma_data_ptr)[m_dma_offset]); @@ -479,15 +480,12 @@ TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer) m_dma_offset++; m_dma_size--; } - - if (m_dma_requested && m_dma_size > 0) - m_dma_timer->adjust(attotime::from_usec(10)); } void konamigv_state::scsi_drq(int state) { if (!m_dma_requested && state) - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); m_dma_requested = state; } diff --git a/src/mame/konami/twinkle.cpp b/src/mame/konami/twinkle.cpp index cf91266a77f..b273c58292d 100644 --- a/src/mame/konami/twinkle.cpp +++ b/src/mame/konami/twinkle.cpp @@ -1088,7 +1088,7 @@ void twinkle_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int3 m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = false; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size) @@ -1097,12 +1097,13 @@ void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int m_dma_offset = n_address; m_dma_size = n_size * 4; m_dma_is_write = true; - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); } TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer) { - if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) + // TODO: Figure out proper DMA timings + while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0) { if (m_dma_is_write) m_ncr53cf96->dma_w(util::little_endian_cast(m_dma_data_ptr)[m_dma_offset]); @@ -1112,15 +1113,12 @@ TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer) m_dma_offset++; m_dma_size--; } - - if (m_dma_requested && m_dma_size > 0) - m_dma_timer->adjust(attotime::from_usec(10)); } void twinkle_state::scsi_drq(int state) { if (!m_dma_requested && state) - m_dma_timer->adjust(attotime::from_usec(10)); + m_dma_timer->adjust(attotime::zero); m_dma_requested = state; } -- cgit v1.2.3