From 65b35b09b78dd42d461c04665a275eef3c6ce220 Mon Sep 17 00:00:00 2001 From: Mark Garlanger Date: Sat, 7 Dec 2024 23:41:35 -0600 Subject: heathzenith/h89.cpp: Add h89 clone with CDR hardware (#13027) --- scripts/src/bus.lua | 2 + src/devices/bus/heathzenith/h89/cards.cpp | 2 + src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp | 403 +++++++++++++++++++++++ src/devices/bus/heathzenith/h89/cdr_fdc_880h.h | 19 ++ src/devices/bus/heathzenith/h89/h89bus.cpp | 4 + src/mame/heathzenith/h89.cpp | 83 +++++ src/mame/mame.lst | 1 + 7 files changed, 514 insertions(+) create mode 100644 src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp create mode 100644 src/devices/bus/heathzenith/h89/cdr_fdc_880h.h diff --git a/scripts/src/bus.lua b/scripts/src/bus.lua index d7fdfe15364..106967eb2cb 100644 --- a/scripts/src/bus.lua +++ b/scripts/src/bus.lua @@ -5755,6 +5755,8 @@ if (BUSES["H89BUS"]~=null) then files { MAME_DIR .. "src/devices/bus/heathzenith/h89/cards.cpp", MAME_DIR .. "src/devices/bus/heathzenith/h89/cards.h", + MAME_DIR .. "src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp", + MAME_DIR .. "src/devices/bus/heathzenith/h89/cdr_fdc_880h.h", MAME_DIR .. "src/devices/bus/heathzenith/h89/h89bus.cpp", MAME_DIR .. "src/devices/bus/heathzenith/h89/h89bus.h", MAME_DIR .. "src/devices/bus/heathzenith/h89/h17_fdc.cpp", diff --git a/src/devices/bus/heathzenith/h89/cards.cpp b/src/devices/bus/heathzenith/h89/cards.cpp index 618f07d4f6a..0f22c6401f8 100644 --- a/src/devices/bus/heathzenith/h89/cards.cpp +++ b/src/devices/bus/heathzenith/h89/cards.cpp @@ -9,6 +9,7 @@ #include "emu.h" #include "cards.h" +#include "cdr_fdc_880h.h" #include "h_88_3.h" #include "h_88_5.h" #include "mms77316_fdc.h" @@ -24,6 +25,7 @@ void h89_left_cards(device_slot_interface &device) void h89_right_cards(device_slot_interface &device) { + device.option_add("cdr_fdc", H89BUS_CDR_FDC_880H); device.option_add("h_88_3", H89BUS_H_88_3); device.option_add("ha_88_3", H89BUS_HA_88_3); device.option_add("h_88_5", H89BUS_H_88_5); diff --git a/src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp b/src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp new file mode 100644 index 00000000000..21ca7209c9a --- /dev/null +++ b/src/devices/bus/heathzenith/h89/cdr_fdc_880h.cpp @@ -0,0 +1,403 @@ +// license:BSD-3-Clause +// copyright-holders:Mark Garlanger +/*************************************************************************** + + CDR FDC-880H soft-sectored floppy controller + + Supports up to 4 floppy drives, both 5.25" and 8" drives. + +****************************************************************************/ + +#include "emu.h" + +#include "cdr_fdc_880h.h" + +#include "imagedev/floppy.h" +#include "machine/wd_fdc.h" + +namespace { + +class cdr_fdc_880h_device : public device_t, public device_h89bus_right_card_interface +{ +public: + + cdr_fdc_880h_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + virtual void write(u8 select_lines, u8 offset, u8 data) override; + virtual u8 read(u8 select_lines, u8 offset) override; + + // The controller has two 16L8 PALs which are not dumped (z15 and z20 from schematics). + static constexpr feature_type unemulated_features() { return feature::DISK; } + +protected: + + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + + void cmd_w(u8 val); + void data_w(u8 val); + u8 data_r(); + u8 status_r(); + + void set_irq(int state); + void set_drq(int state); + +private: + + required_device m_fdc; + required_device_array m_floppies; + + bool m_irq_allowed; + + bool m_irq; + bool m_drq; + + bool m_double_density; + bool m_five_in_drive; + bool m_mode_operate; + s8 m_drive; + + + /// Bits set in cmd_ControlPort_c + static constexpr u8 ctrl_EnableIntReq_c = 7; + static constexpr u8 ctrl_SetMFMRecording_c = 6; + static constexpr u8 ctrl_DriveType_c = 5; + static constexpr u8 ctrl_Mode_c = 4; + + static constexpr XTAL MASTER_CLOCK = XTAL(4'000'000); + static constexpr XTAL FIVE_IN_CLOCK = MASTER_CLOCK / 4; + static constexpr XTAL EIGHT_IN_CLOCK = MASTER_CLOCK / 2; + +}; + +#define LOG_REG (1U << 1) // Shows register setup +#define LOG_LINES (1U << 2) // Show control lines +#define LOG_DRIVE (1U << 3) // Show drive select +#define LOG_FUNC (1U << 4) // Function calls +#define LOG_ERR (1U << 5) // log errors +#define LOG_WAIT (1U << 6) // wait mode +#define LOG_DATA (1U << 7) // data read/writes + +#define VERBOSE (0xff) + +#include "logmacro.h" + +#define LOGREG(...) LOGMASKED(LOG_REG, __VA_ARGS__) +#define LOGLINES(...) LOGMASKED(LOG_LINES, __VA_ARGS__) +#define LOGDRIVE(...) LOGMASKED(LOG_DRIVE, __VA_ARGS__) +#define LOGFUNC(...) LOGMASKED(LOG_FUNC, __VA_ARGS__) +#define LOGERR(...) LOGMASKED(LOG_ERR, __VA_ARGS__) +#define LOGWAIT(...) LOGMASKED(LOG_WAIT, __VA_ARGS__) +#define LOGDATA(...) LOGMASKED(LOG_DATA, __VA_ARGS__) + +#ifdef _MSC_VER +#define FUNCNAME __func__ +#else +#define FUNCNAME __PRETTY_FUNCTION__ +#endif + + +cdr_fdc_880h_device::cdr_fdc_880h_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock): + device_t(mconfig, H89BUS_CDR_FDC_880H, tag, owner, 0), + device_h89bus_right_card_interface(mconfig, *this), + m_fdc(*this, "cdr_fdc_880h"), + m_floppies(*this, "cdr_fdc_880h:%u", 0U) +{ +} + +void cdr_fdc_880h_device::cmd_w(u8 val) +{ + LOGREG("%s: val: %d\n", FUNCNAME, val); + + u8 drive = BIT(val, 0, 3); + + if (drive & 0x01) + { + m_drive = 0; + } + else if (drive & 0x02) + { + m_drive = 1; + } + else if (drive & 0x04) + { + m_drive = 2; + } + else if (drive & 0x08) + { + m_drive = 3; + } + else + { + m_drive = -1; + } + m_mode_operate = bool(BIT(val, ctrl_Mode_c)); + m_five_in_drive = bool(BIT(val, ctrl_DriveType_c)); + m_double_density = !bool(BIT(val, ctrl_SetMFMRecording_c)); + m_irq_allowed = bool(BIT(val, ctrl_EnableIntReq_c)); + + m_fdc->dden_w(!m_double_density); + + LOGLINES("%s: intrq allowed: %d\n", FUNCNAME, m_irq_allowed); + + set_slot_int5(m_irq_allowed ? m_irq : CLEAR_LINE); + + LOGDRIVE("%s: floppydrive: %d, 5.25 in: %d\n", FUNCNAME, m_drive, m_five_in_drive); + + if (m_drive >= 0) + { + m_fdc->set_floppy(m_floppies[m_drive]->get_device()); + } + + for (auto &elem : m_floppies) + { + floppy_image_device *floppy = elem->get_device(); + if (floppy) + { + floppy->mon_w(m_drive == -1); + } + } + + m_fdc->set_clock(m_five_in_drive ? FIVE_IN_CLOCK : EIGHT_IN_CLOCK); +} + +void cdr_fdc_880h_device::data_w(u8 val) +{ + LOGDATA("%s: val: %d\n", FUNCNAME, val); + + if (!m_drq && !m_irq) + { + LOGWAIT("%s: wait state\n", FUNCNAME); + + set_slot_wait(ASSERT_LINE); + return; + } + + m_fdc->data_w(val); +} + +void cdr_fdc_880h_device::write(u8 select_lines, u8 offset, u8 data) +{ + if (!(select_lines & h89bus_device::H89_CASS)) + { + return; + } + + LOGREG("%s: reg: %d val: 0x%02x\n", FUNCNAME, offset, data); + + switch (offset) + { + case 0: + case 1: + case 2: + // read not supported on these addresses + LOGERR("%s: Unexpected port read reg: %d\n", FUNCNAME, offset); + break; + case 3: // Select Port + cmd_w(data); + break; + case 4: // Command Port + m_fdc->cmd_w(data); + break; + case 5: // Track Port + m_fdc->track_w(data); + break; + case 6: // Sector Port + m_fdc->sector_w(data); + break; + case 7: // Data Port + data_w(data); + break; + } +} + +u8 cdr_fdc_880h_device::status_r() +{ + u8 data = 0; + + switch(m_drive) + { + case 0: + data |= 0x0e; + break; + case 1: + data |= 0x0d; + break; + case 2: + data |= 0x0b; + break; + case 3: + data |= 0x07; + break; + case -1: + default: + data |= 0x0f; + break; + } + data |= m_mode_operate ? 0x10 : 0; + data |= m_five_in_drive ? 0 : 0x20; + data |= m_double_density ? 0x40 : 0; + data |= m_irq ? 0 : 0x80; + + return data; +} + +u8 cdr_fdc_880h_device::data_r() +{ + u8 data = 0; + + if (!m_drq && !m_irq) + { + LOGWAIT("%s: wait state\n", FUNCNAME); + + if (!machine().side_effects_disabled()) + { + set_slot_wait(ASSERT_LINE); + } + } + else + { + data = m_fdc->data_r(); + } + + LOGDATA("%s: data: %d\n", FUNCNAME, data); + + return data; +} + +u8 cdr_fdc_880h_device::read(u8 select_lines, u8 offset) +{ + if (!(select_lines & h89bus_device::H89_CASS)) + { + return 0; + } + + u8 value = 0; + + switch (offset) + { + case 0: + case 1: + case 2: + // read not supported on these addresses + LOGERR("%s: Unexpected port read reg: %d\n", FUNCNAME, offset); + break; + case 3: // ?? + value = status_r(); + break; + case 4: // Drive Status Port + value = m_fdc->status_r(); + break; + case 5: // Track Port + value = m_fdc->track_r(); + break; + case 6: // Sector Port + value = m_fdc->sector_r(); + break; + case 7: // Data Port + value = data_r(); + break; + } + + LOGREG("%s: reg: %d val: 0x%02x\n", FUNCNAME, offset, value); + + return value; +} + +void cdr_fdc_880h_device::device_start() +{ + save_item(NAME(m_irq_allowed)); + save_item(NAME(m_irq)); + save_item(NAME(m_drq)); +} + +void cdr_fdc_880h_device::device_reset() +{ + m_irq_allowed = false; + m_irq = false; + + set_slot_int5(CLEAR_LINE); + set_slot_wait(CLEAR_LINE); + + for (int i = 0; i < 4; i++) + { + auto elem = m_floppies[i]; + if (elem) + { + floppy_image_device *floppy = elem->get_device(); + if (floppy) + { + // turn on motor of all installed 8" floppies + floppy->mon_w(0); + } + } + } +} + +static void cdr_floppies(device_slot_interface &device) +{ + // 5.25" SS 48tpi + device.option_add("5_ss_dd", FLOPPY_525_SSDD); + // 5.25" SS 96tpi + device.option_add("5_ss_qd", FLOPPY_525_SSQD); + // 5.25" DS 48tpi + device.option_add("5_ds_dd", FLOPPY_525_DD); + // 5.25" DS 96tpi + device.option_add("5_ds_qd", FLOPPY_525_QD); + + // 8" SSSD + device.option_add("8_ss_sd", FLOPPY_8_SSSD); + // 8" DSSD + device.option_add("8_ds_sd", FLOPPY_8_DSSD); + // 8" SSDD + device.option_add("8_ss_dd", FLOPPY_8_SSDD); + // 8" DSDD + device.option_add("8_ds_dd", FLOPPY_8_DSDD); +} + +void cdr_fdc_880h_device::device_add_mconfig(machine_config &config) +{ + FD1797(config, m_fdc, EIGHT_IN_CLOCK); + m_fdc->intrq_wr_callback().set(FUNC(cdr_fdc_880h_device::set_irq)); + m_fdc->drq_wr_callback().set(FUNC(cdr_fdc_880h_device::set_drq)); + + FLOPPY_CONNECTOR(config, m_floppies[0], cdr_floppies, "5_ds_qd", floppy_image_device::default_mfm_floppy_formats); + m_floppies[0]->enable_sound(true); + FLOPPY_CONNECTOR(config, m_floppies[1], cdr_floppies, "5_ds_qd", floppy_image_device::default_mfm_floppy_formats); + m_floppies[1]->enable_sound(true); + FLOPPY_CONNECTOR(config, m_floppies[2], cdr_floppies, "5_ds_qd", floppy_image_device::default_mfm_floppy_formats); + m_floppies[2]->enable_sound(true); + FLOPPY_CONNECTOR(config, m_floppies[3], cdr_floppies, "5_ds_qd", floppy_image_device::default_mfm_floppy_formats); + m_floppies[3]->enable_sound(true); +} + +void cdr_fdc_880h_device::set_irq(int state) +{ + LOGLINES("set irq, allowed: %d state: %d\n", m_irq_allowed, state); + + m_irq = state; + + if (m_irq) + { + set_slot_wait(CLEAR_LINE); + } + + set_slot_int5(m_irq_allowed ? m_irq : CLEAR_LINE); +} + +void cdr_fdc_880h_device::set_drq(int state) +{ + LOGLINES("set drq state: %d\n", state); + + m_drq = state; + + if (m_drq) + { + set_slot_wait(CLEAR_LINE); + } + +} +} + +DEFINE_DEVICE_TYPE_PRIVATE(H89BUS_CDR_FDC_880H, device_h89bus_right_card_interface, cdr_fdc_880h_device, "cdr_fdc_880h", "CDR FDC-880H Soft-sectored Controller"); diff --git a/src/devices/bus/heathzenith/h89/cdr_fdc_880h.h b/src/devices/bus/heathzenith/h89/cdr_fdc_880h.h new file mode 100644 index 00000000000..2bb62de1dea --- /dev/null +++ b/src/devices/bus/heathzenith/h89/cdr_fdc_880h.h @@ -0,0 +1,19 @@ +// license:BSD-3-Clause +// copyright-holders:Mark Garlanger +/*************************************************************************** + + CDR FDC-880H soft-sectored floppy controller + +****************************************************************************/ + +#ifndef MAME_BUS_HEATHZENITH_H89_CDR_FDC_880H_H +#define MAME_BUS_HEATHZENITH_H89_CDR_FDC_880H_H + +#pragma once + +#include "h89bus.h" + +DECLARE_DEVICE_TYPE(H89BUS_CDR_FDC_880H, device_h89bus_right_card_interface) + + +#endif // MAME_BUS_HEATHZENITH_H89_CDR_FDC_880H_H diff --git a/src/devices/bus/heathzenith/h89/h89bus.cpp b/src/devices/bus/heathzenith/h89/h89bus.cpp index 17a6fab2dd6..1b05c49e480 100644 --- a/src/devices/bus/heathzenith/h89/h89bus.cpp +++ b/src/devices/bus/heathzenith/h89/h89bus.cpp @@ -123,6 +123,10 @@ ROM_START(h89bus) // MMS (Magnolia Micro Systems) I/O decoding ROM_SYSTEM_BIOS(2, "444-61c", "MMS decoding (444-61c)") ROMX_LOAD( "444-61c.bin", 0x000000, 0x000100, CRC(e7122061) SHA1(33c124f44c0f9cb99c9b17ad15411b4bc6407eae), ROM_BIOS(2)) + + // CDR Systems + ROM_SYSTEM_BIOS(3, "cdr86", "CDR decoding (CDR86)") + ROMX_LOAD( "cdr86.bin", 0x000000, 0x000100, CRC(d35e4063) SHA1(879f9d265d77f8a74c70febd9a80d6896ab8ec7e), ROM_BIOS(3)) ROM_END //************************************************************************** diff --git a/src/mame/heathzenith/h89.cpp b/src/mame/heathzenith/h89.cpp index 0412404811b..fec89e8763f 100644 --- a/src/mame/heathzenith/h89.cpp +++ b/src/mame/heathzenith/h89.cpp @@ -204,6 +204,16 @@ public: void h89_sigmasoft(machine_config &config); }; +class h89_cdr_state : public h89_base_state +{ +public: + h89_cdr_state(const machine_config &mconfig, device_type type, const char *tag): + h89_base_state(mconfig, type, tag) + { + } + + void h89_cdr(machine_config &config); +}; /** * Heathkit H89 with MMS hardware @@ -605,6 +615,30 @@ static INPUT_PORTS_START( h89 ) PORT_DIPSETTING( 0x00, DEF_STR( Normal ) ) PORT_DIPSETTING( 0x80, "Auto" ) + // CDR8390 ROM + PORT_DIPNAME( 0x03, 0x00, "Disk I/O #2" ) PORT_DIPLOCATION("SW501:1,2") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x00, "H-88-1" ) + PORT_DIPSETTING( 0x01, "undefined" ) + PORT_DIPSETTING( 0x02, "undefined" ) + PORT_DIPSETTING( 0x03, "undefined" ) + PORT_DIPNAME( 0x0c, 0x00, "Disk I/O #1" ) PORT_DIPLOCATION("SW501:3,4") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x00, "undefined" ) + PORT_DIPSETTING( 0x04, "CDR FDC-880H" ) + PORT_DIPSETTING( 0x08, "undefined" ) + PORT_DIPSETTING( 0x0c, "undefined" ) + PORT_DIPNAME( 0x10, 0x00, "Primary Boot from" ) PORT_DIPLOCATION("SW501:5") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x00, "Disk I/O #2" ) + PORT_DIPSETTING( 0x10, "Disk I/O #1" ) + PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("SW501:6") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x20, DEF_STR( No ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) + PORT_DIPNAME( 0x40, 0x00, "Console Baud rate" ) PORT_DIPLOCATION("SW501:7") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x00, "9600" ) + PORT_DIPSETTING( 0x40, "19200" ) + PORT_DIPNAME( 0x80, 0x00, "Boot mode" ) PORT_DIPLOCATION("SW501:8") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x20) + PORT_DIPSETTING( 0x00, DEF_STR( Normal ) ) + PORT_DIPSETTING( 0x80, "Auto" ) + PORT_START("CONFIG") PORT_CONFNAME(0x03, 0x00, "CPU Clock Speed Upgrade") @@ -620,6 +654,7 @@ static INPUT_PORTS_START( h89 ) PORT_CONFSETTING( 0x14, "Ultimeth MTRHEX-4k") PORT_CONFSETTING( 0x18, "Ultimeth MTRHEX-2k") PORT_CONFSETTING( 0x1c, "SigmaROM") + PORT_CONFSETTING( 0x20, "CDR8390 ROM") INPUT_PORTS_END @@ -993,6 +1028,17 @@ void h89_sigmasoft_state::h89_sigmasoft(machine_config &config) H89BUS_LEFT_SLOT(config.replace(), "p501", "h89bus", h89_left_cards, "ss_parallel"); } +void h89_cdr_state::h89_cdr(machine_config &config) +{ + h89_base(config); + m_h89bus->set_default_bios_tag("cdr86"); + + m_intr_socket->set_default_option("original"); + m_intr_socket->set_fixed(true); + + H89BUS_RIGHT_SLOT(config.replace(), "p504", "h89bus", h89_right_cards, "cdr_fdc"); +} + void h89_mms_state::h89_mms(machine_config &config) { h89_base(config); @@ -1053,6 +1099,15 @@ void h89_mms_state::h89_mms(machine_config &config) ROM_SYSTEM_BIOS(x, "sigmarom_v1_2", "SigmaROM v1.2") \ ROMX_LOAD("2732_sigma_rom_v_1.2.bin", 0x0000, 0x1000, CRC(c4ff47c5) SHA1(d6f3d71ff270a663003ec18a3ed1fa49f627123a), ROM_BIOS(x)) +#define ROM_CDR_8390(x) \ + ROM_SYSTEM_BIOS(x, "cdr8390", "CDR 8390") \ + ROMX_LOAD("2732_cdr8390.u518", 0x0000, 0x1000, CRC(1d30fe43) SHA1(170092d1b62cf88edd29338b474e799c249a0dd7), ROM_BIOS(x)) + +// NOTE: this rom is not currently working +#define ROM_CDR_80B2(x) \ + ROM_SYSTEM_BIOS(x, "cdr80b2", "CDR 80B2") \ + ROMX_LOAD("2732_cdr80b2.u518", 0x0000, 0x1000, CRC(804a6898) SHA1(a58daca0baf7b5d7c1485531680bd63168eb2d7e), ROM_BIOS(x)) + ROM_START( h88 ) ROM_REGION( 0x2000, "maincpu", ROMREGION_ERASEFF ) @@ -1087,6 +1142,10 @@ ROM_START( h89 ) ROM_SIGMA_V_1_3(8) ROM_SIGMA_V_1_2(9) + + ROM_CDR_8390(10) + + ROM_CDR_80B2(11) ROM_END ROM_START( h89_sigmasoft ) @@ -1114,6 +1173,25 @@ ROM_START( h89_sigmasoft ) ROM_SIGMA_V_1_3(8) ROM_SIGMA_V_1_2(9) + + ROM_CDR_8390(10) + + ROM_CDR_80B2(11) +ROM_END + +ROM_START( h89_cdr ) + ROM_REGION( 0x2000, "maincpu", ROMREGION_ERASEFF ) + ROM_DEFAULT_BIOS("cdr8390") + + ROM_H17 + + ROM_CDR_8390(0) + + ROM_CDR_80B2(1) + + ROM_KMR_100(2) + + ROM_ULTIMETH_4K(3) ROM_END ROM_START( h89_mms ) @@ -1154,6 +1232,10 @@ ROM_START( z90 ) ROM_SIGMA_V_1_3(6) ROM_SIGMA_V_1_2(7) + + ROM_CDR_8390(8) + + ROM_CDR_80B2(9) ROM_END } // anonymous namespace @@ -1162,6 +1244,7 @@ ROM_END // year name parent compat machine input class init company fullname flags COMP( 1979, h88, h89, 0, h88, h88, h88_state, empty_init, "Heath Company", "H-88", MACHINE_SUPPORTS_SAVE) COMP( 1979, h89, 0, 0, h89, h89, h89_state, empty_init, "Heath Company", "H-89", MACHINE_SUPPORTS_SAVE) +COMP( 1981, h89_cdr, h89, 0, h89_cdr, h89, h89_cdr_state, empty_init, "Heath Company", "H-89 with CDR Equipment", MACHINE_SUPPORTS_SAVE) COMP( 1981, h89_mms, h89, 0, h89_mms, h89, h89_mms_state, empty_init, "Heath Company", "H-89 with MMS Equipment", MACHINE_SUPPORTS_SAVE) COMP( 1981, z90, h89, 0, h89, h89, h89_state, empty_init, "Zenith Data Systems", "Z-90", MACHINE_SUPPORTS_SAVE) COMP( 1984, h89_sigmasoft, h89, 0, h89_sigmasoft, h89, h89_sigmasoft_state, empty_init, "Heath Company", "H-89 with SigmaSoft IGC", MACHINE_SUPPORTS_SAVE) diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 0c77c411eed..8ff3eea453b 100644 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -19559,6 +19559,7 @@ h19 // Heath H19 @source:heathzenith/h89.cpp h89 // Heath H89 (WH89) h88 // Heath H88 (with cassette tape) +h89_cdr // Heath H89 with CDR Systems hardware h89_mms // Heath H89 with Magnolia MicroSystems(MMS) hardware h89_sigmasoft // H89 with the SigmaSoft IGC card z90 // Zenith Z-90 -- cgit v1.2.3