From 5d5d085ef21ab7ccce28b73519dcdba699881925 Mon Sep 17 00:00:00 2001 From: hap Date: Thu, 15 Aug 2024 15:20:32 +0200 Subject: mcs48: shorthand variable types --- src/devices/cpu/mcs48/mcs48.cpp | 306 ++++++++++++++++++------------------- src/devices/cpu/mcs48/mcs48.h | 184 +++++++++++----------- src/devices/cpu/mcs48/mcs48dsm.cpp | 2 - src/devices/cpu/mcs48/mcs48dsm.h | 3 - 4 files changed, 245 insertions(+), 250 deletions(-) diff --git a/src/devices/cpu/mcs48/mcs48.cpp b/src/devices/cpu/mcs48/mcs48.cpp index ce0dce03d7a..92ba7d1a400 100644 --- a/src/devices/cpu/mcs48/mcs48.cpp +++ b/src/devices/cpu/mcs48/mcs48.cpp @@ -45,22 +45,22 @@ UPI-41/42 chips are MCS-48 derived, with some opcode changes: - MCS-48 opcode UPI-41/42 opcode - ------------- ---------------- - 02: OUTL BUS,A OUT DBB,A - 08: INS BUS,A - 22: IN DBB,A - 75: ENT0 CLK - 80: MOVX A,@R0 - 81: MOVX A,@R1 - 86: JNI JOBF - 88: ORL BUS,#n - 90: MOVX @R0,A MOV STS,A - 91: MOVX @R1,A - 98: ANL BUS,#n - D6: JNIBF - E5: SEL MB0 EN DMA - F5: SEL MB1 EN FLAGS + MCS-48 opcode UPI-41/42 opcode + ------------- ---------------- + 02: OUTL BUS,A OUT DBB,A + 08: INS BUS,A + 22: IN DBB,A + 75: ENT0 CLK + 80: MOVX A,@R0 + 81: MOVX A,@R1 + 86: JNI JOBF + 88: ORL BUS,#n + 90: MOVX @R0,A MOV STS,A + 91: MOVX @R1,A + 98: ANL BUS,#n + D6: JNIBF + E5: SEL MB0 EN DMA + F5: SEL MB1 EN FLAGS Chip numbers are similar to the MCS-48 series: @@ -168,7 +168,7 @@ DEFINE_DEVICE_TYPE(M58715, m58715_device, "m58715", "M58715") CONSTRUCTOR ***************************************************************************/ -mcs48_cpu_device::mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int rom_size, int ram_size, uint8_t feature_mask, const mcs48_cpu_device::mcs48_ophandler *opcode_table) +mcs48_cpu_device::mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int rom_size, int ram_size, u8 feature_mask, const mcs48_cpu_device::mcs48_ophandler *opcode_table) : cpu_device(mconfig, type, tag, owner, clock) , m_program_config("program", ENDIANNESS_LITTLE, 8, (feature_mask & MB_FEATURE) != 0 ? 12 : 11, 0, rom_size ? address_map_constructor(FUNC(mcs48_cpu_device::program_map), this) : address_map_constructor()) @@ -202,117 +202,117 @@ mcs48_cpu_device::mcs48_cpu_device(const machine_config &mconfig, device_type ty } } -i8021_device::i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8021_device::i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8021, tag, owner, clock, 1024, 64, I802X_FEATURE, s_i8021_opcodes) { } -i8022_device::i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8022_device::i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8022, tag, owner, clock, 2048, 128, I802X_FEATURE, s_i8022_opcodes) { } -i8035_device::i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8035_device::i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8035, tag, owner, clock, 0, 64, I8048_FEATURE, s_mcs48_opcodes) { } -i8048_device::i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8048_device::i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8048, tag, owner, clock, 1024, 64, I8048_FEATURE, s_mcs48_opcodes) { } -i8648_device::i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8648_device::i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8648, tag, owner, clock, 1024, 64, I8048_FEATURE, s_mcs48_opcodes) { } -i8748_device::i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8748_device::i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8748, tag, owner, clock, 1024, 64, I8048_FEATURE, s_mcs48_opcodes) { } -i8039_device::i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8039_device::i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8039, tag, owner, clock, 0, 128, I8048_FEATURE, s_mcs48_opcodes) { } -i8049_device::i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8049_device::i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8049, tag, owner, clock, 2048, 128, I8048_FEATURE, s_mcs48_opcodes) { } -i8749_device::i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8749_device::i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8749, tag, owner, clock, 2048, 128, I8048_FEATURE, s_mcs48_opcodes) { } -i8040_device::i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8040_device::i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8040, tag, owner, clock, 0, 256, I8048_FEATURE, s_mcs48_opcodes) { } -i8050_device::i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8050_device::i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, I8050, tag, owner, clock, 4096, 256, I8048_FEATURE, s_mcs48_opcodes) { } -mb8884_device::mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +mb8884_device::mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, MB8884, tag, owner, clock, 0, 64, I8048_FEATURE, s_mcs48_opcodes) { } -n7751_device::n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +n7751_device::n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, N7751, tag, owner, clock, 1024, 64, I8048_FEATURE, s_mcs48_opcodes) { } -m58715_device::m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +m58715_device::m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : mcs48_cpu_device(mconfig, M58715, tag, owner, clock, 2048, 128, I8048_FEATURE, s_mcs48_opcodes) { } -upi41_cpu_device::upi41_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int rom_size, int ram_size) +upi41_cpu_device::upi41_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int rom_size, int ram_size) : mcs48_cpu_device(mconfig, type, tag, owner, clock, rom_size, ram_size, UPI41_FEATURE, s_upi41_opcodes) { } -i8041a_device::i8041a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8041a_device::i8041a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8041A, tag, owner, clock, 1024, 64) { } -i8741a_device::i8741a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8741a_device::i8741a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8741A, tag, owner, clock, 1024, 64) { } -i8041ah_device::i8041ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8041ah_device::i8041ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8041AH, tag, owner, clock, 1024, 128) { } -i8741ah_device::i8741ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8741ah_device::i8741ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8741AH, tag, owner, clock, 1024, 128) { } -i8042_device::i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8042_device::i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8042, tag, owner, clock, 2048, 128) { } -i8742_device::i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8742_device::i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8742, tag, owner, clock, 2048, 128) { } -i8042ah_device::i8042ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8042ah_device::i8042ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8042AH, tag, owner, clock, 2048, 256) { } -i8742ah_device::i8742ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) +i8742ah_device::i8742ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : upi41_cpu_device(mconfig, I8742AH, tag, owner, clock, 2048, 256) { } @@ -344,15 +344,15 @@ std::unique_ptr mcs48_cpu_device::create_disassembler() void mcs48_cpu_device::program_map(address_map &map) { - const uint16_t mask = m_rom_size - 1; + const u16 end = m_rom_size - 1; // I802X does not have EA pin if (m_feature_mask & I802X_FEATURE) - map(0, mask).rom(); + map(0, end).rom(); else { - map(0, mask).view(m_rom_view); - m_rom_view[0](0, mask).rom(); + map(0, end).view(m_rom_view); + m_rom_view[0](0, end).rom(); } } @@ -370,9 +370,9 @@ void mcs48_cpu_device::data_map(address_map &map) opcode_fetch - fetch an opcode byte -------------------------------------------------*/ -uint8_t mcs48_cpu_device::opcode_fetch() +u8 mcs48_cpu_device::opcode_fetch() { - uint16_t address = m_pc; + u16 address = m_pc; m_pc = ((m_pc + 1) & 0x7ff) | (m_pc & 0x800); return m_program.read_byte(address); } @@ -383,9 +383,9 @@ uint8_t mcs48_cpu_device::opcode_fetch() byte -------------------------------------------------*/ -uint8_t mcs48_cpu_device::argument_fetch() +u8 mcs48_cpu_device::argument_fetch() { - uint16_t address = m_pc; + u16 address = m_pc; m_pc = ((m_pc + 1) & 0x7ff) | (m_pc & 0x800); return m_program.read_byte(address); } @@ -420,13 +420,13 @@ void mcs48_cpu_device::update_ea() /*------------------------------------------------- - push_pc_psw - push the m_pc and m_psw values onto + push_pc_psw - push the PC and PSW values onto the stack -------------------------------------------------*/ void mcs48_cpu_device::push_pc_psw() { - uint8_t sp = m_psw & 0x07; + u8 sp = m_psw & 0x07; ram_w(8 + 2*sp, m_pc); ram_w(9 + 2*sp, ((m_pc >> 8) & 0x0f) | (m_psw & 0xf0)); m_psw = (m_psw & 0xf0) | ((sp + 1) & 0x07); @@ -440,7 +440,7 @@ void mcs48_cpu_device::push_pc_psw() void mcs48_cpu_device::pull_pc_psw() { - uint8_t sp = (m_psw - 1) & 0x07; + u8 sp = (m_psw - 1) & 0x07; m_pc = ram_r(8 + 2*sp); m_pc |= ram_r(9 + 2*sp) << 8; m_psw = ((m_pc >> 8) & 0xf0) | sp; @@ -456,7 +456,7 @@ void mcs48_cpu_device::pull_pc_psw() void mcs48_cpu_device::pull_pc() { - uint8_t sp = (m_psw - 1) & 0x07; + u8 sp = (m_psw - 1) & 0x07; m_pc = ram_r(8 + 2*sp); m_pc |= ram_r(9 + 2*sp) << 8; m_pc &= (m_irq_in_progress) ? 0x7ff : 0xfff; @@ -469,10 +469,10 @@ void mcs48_cpu_device::pull_pc() instruction -------------------------------------------------*/ -void mcs48_cpu_device::execute_add(uint8_t dat) +void mcs48_cpu_device::execute_add(u8 dat) { - uint16_t temp = m_a + dat; - uint16_t temp4 = (m_a & 0x0f) + (dat & 0x0f); + u16 temp = m_a + dat; + u16 temp4 = (m_a & 0x0f) + (dat & 0x0f); m_psw &= ~(C_FLAG | A_FLAG); m_psw |= (temp4 << 2) & A_FLAG; @@ -486,11 +486,11 @@ void mcs48_cpu_device::execute_add(uint8_t dat) instruction -------------------------------------------------*/ -void mcs48_cpu_device::execute_addc(uint8_t dat) +void mcs48_cpu_device::execute_addc(u8 dat) { - uint8_t carryin = (m_psw & C_FLAG) >> 7; - uint16_t temp = m_a + dat + carryin; - uint16_t temp4 = (m_a & 0x0f) + (dat & 0x0f) + carryin; + u8 carryin = (m_psw & C_FLAG) >> 7; + u16 temp = m_a + dat + carryin; + u16 temp4 = (m_a & 0x0f) + (dat & 0x0f) + carryin; m_psw &= ~(C_FLAG | A_FLAG); m_psw |= (temp4 << 2) & A_FLAG; @@ -504,9 +504,9 @@ void mcs48_cpu_device::execute_addc(uint8_t dat) instruction -------------------------------------------------*/ -void mcs48_cpu_device::execute_jmp(uint16_t address) +void mcs48_cpu_device::execute_jmp(u16 address) { - uint16_t a11 = (m_irq_in_progress) ? 0 : m_a11; + u16 a11 = (m_irq_in_progress) ? 0 : m_a11; m_pc = address | a11; } @@ -516,7 +516,7 @@ void mcs48_cpu_device::execute_jmp(uint16_t address) instruction -------------------------------------------------*/ -void mcs48_cpu_device::execute_call(uint16_t address) +void mcs48_cpu_device::execute_call(u16 address) { push_pc_psw(); execute_jmp(address); @@ -530,8 +530,8 @@ void mcs48_cpu_device::execute_call(uint16_t address) void mcs48_cpu_device::execute_jcc(bool result) { - uint16_t pch = m_pc & 0xf00; - uint8_t offset = argument_fetch(); + u16 pch = m_pc & 0xf00; + u8 offset = argument_fetch(); if (result) m_pc = pch | offset; } @@ -542,9 +542,9 @@ void mcs48_cpu_device::execute_jcc(bool result) code can directly affect -------------------------------------------------*/ -uint8_t mcs48_cpu_device::p2_mask() +u8 mcs48_cpu_device::p2_mask() { - uint8_t result = 0xff; + u8 result = 0xff; if ((m_feature_mask & UPI41_FEATURE) == 0) return result; if (m_flags_enabled) @@ -560,10 +560,10 @@ uint8_t mcs48_cpu_device::p2_mask() the 8243 expander chip -------------------------------------------------*/ -void mcs48_cpu_device::expander_operation(expander_op operation, uint8_t port) +void mcs48_cpu_device::expander_operation(expander_op operation, u8 port) { // put opcode on low 4 bits of P2 (overwriting latch) - port_w(2, m_p2 = (m_p2 & 0xf0) | (uint8_t(operation) << 2) | (port & 3)); + port_w(2, m_p2 = (m_p2 & 0xf0) | (u8(operation) << 2) | (port & 3)); // generate high-to-low transition on PROG line prog_w(0); @@ -857,7 +857,7 @@ OPHANDLER( orld_p7_a ) { burn_cycles(2); expander_operation(EXPANDER_OP_OR, OPHANDLER( outl_bus_a ) { burn_cycles(2); bus_w(m_a); } OPHANDLER( outl_p0_a ) { burn_cycles(2); bus_w(m_dbbo = m_a); } OPHANDLER( outl_p1_a ) { burn_cycles(2); port_w(1, m_p1 = m_a); } -OPHANDLER( outl_p2_a ) { burn_cycles(2); uint8_t mask = p2_mask(); port_w(2, m_p2 = (m_p2 & ~mask) | (m_a & mask)); } +OPHANDLER( outl_p2_a ) { burn_cycles(2); u8 mask = p2_mask(); port_w(2, m_p2 = (m_p2 & ~mask) | (m_a & mask)); } OPHANDLER( out_dbb_a ) { burn_cycles(1); @@ -883,10 +883,10 @@ OPHANDLER( retr ) } OPHANDLER( rl_a ) { burn_cycles(1); m_a = (m_a << 1) | (m_a >> 7); } -OPHANDLER( rlc_a ) { burn_cycles(1); uint8_t newc = m_a & C_FLAG; m_a = (m_a << 1) | (m_psw >> 7); m_psw = (m_psw & ~C_FLAG) | newc; } +OPHANDLER( rlc_a ) { burn_cycles(1); u8 newc = m_a & C_FLAG; m_a = (m_a << 1) | (m_psw >> 7); m_psw = (m_psw & ~C_FLAG) | newc; } OPHANDLER( rr_a ) { burn_cycles(1); m_a = (m_a >> 1) | (m_a << 7); } -OPHANDLER( rrc_a ) { burn_cycles(1); uint8_t newc = (m_a << 7) & C_FLAG; m_a = (m_a >> 1) | (m_psw & C_FLAG); m_psw = (m_psw & ~C_FLAG) | newc; } +OPHANDLER( rrc_a ) { burn_cycles(1); u8 newc = (m_a << 7) & C_FLAG; m_a = (m_a >> 1) | (m_psw & C_FLAG); m_psw = (m_psw & ~C_FLAG) | newc; } OPHANDLER( sel_mb0 ) { burn_cycles(1); m_a11 = 0x000; } OPHANDLER( sel_mb1 ) { burn_cycles(1); m_a11 = 0x800; } @@ -907,19 +907,19 @@ OPHANDLER( strt_cnt ) OPHANDLER( swap_a ) { burn_cycles(1); m_a = (m_a << 4) | (m_a >> 4); } -OPHANDLER( xch_a_r0 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R0; R0 = tmp; } -OPHANDLER( xch_a_r1 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R1; R1 = tmp; } -OPHANDLER( xch_a_r2 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R2; R2 = tmp; } -OPHANDLER( xch_a_r3 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R3; R3 = tmp; } -OPHANDLER( xch_a_r4 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R4; R4 = tmp; } -OPHANDLER( xch_a_r5 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R5; R5 = tmp; } -OPHANDLER( xch_a_r6 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R6; R6 = tmp; } -OPHANDLER( xch_a_r7 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = R7; R7 = tmp; } -OPHANDLER( xch_a_xr0 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = ram_r(R0); ram_w(R0, tmp); } -OPHANDLER( xch_a_xr1 ) { burn_cycles(1); uint8_t tmp = m_a; m_a = ram_r(R1); ram_w(R1, tmp); } +OPHANDLER( xch_a_r0 ) { burn_cycles(1); u8 tmp = m_a; m_a = R0; R0 = tmp; } +OPHANDLER( xch_a_r1 ) { burn_cycles(1); u8 tmp = m_a; m_a = R1; R1 = tmp; } +OPHANDLER( xch_a_r2 ) { burn_cycles(1); u8 tmp = m_a; m_a = R2; R2 = tmp; } +OPHANDLER( xch_a_r3 ) { burn_cycles(1); u8 tmp = m_a; m_a = R3; R3 = tmp; } +OPHANDLER( xch_a_r4 ) { burn_cycles(1); u8 tmp = m_a; m_a = R4; R4 = tmp; } +OPHANDLER( xch_a_r5 ) { burn_cycles(1); u8 tmp = m_a; m_a = R5; R5 = tmp; } +OPHANDLER( xch_a_r6 ) { burn_cycles(1); u8 tmp = m_a; m_a = R6; R6 = tmp; } +OPHANDLER( xch_a_r7 ) { burn_cycles(1); u8 tmp = m_a; m_a = R7; R7 = tmp; } +OPHANDLER( xch_a_xr0 ) { burn_cycles(1); u8 tmp = m_a; m_a = ram_r(R0); ram_w(R0, tmp); } +OPHANDLER( xch_a_xr1 ) { burn_cycles(1); u8 tmp = m_a; m_a = ram_r(R1); ram_w(R1, tmp); } -OPHANDLER( xchd_a_xr0 ) { burn_cycles(1); uint8_t oldram = ram_r(R0); ram_w(R0, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); } -OPHANDLER( xchd_a_xr1 ) { burn_cycles(1); uint8_t oldram = ram_r(R1); ram_w(R1, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); } +OPHANDLER( xchd_a_xr0 ) { burn_cycles(1); u8 oldram = ram_r(R0); ram_w(R0, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); } +OPHANDLER( xchd_a_xr1 ) { burn_cycles(1); u8 oldram = ram_r(R1); ram_w(R1, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); } OPHANDLER( xrl_a_r0 ) { burn_cycles(1); m_a ^= R0; } OPHANDLER( xrl_a_r1 ) { burn_cycles(1); m_a ^= R1; } @@ -943,145 +943,145 @@ OPHANDLER( xrl_a_n ) { burn_cycles(2); m_a ^= argument_fetch(); } const mcs48_cpu_device::mcs48_ophandler mcs48_cpu_device::s_mcs48_opcodes[256] = { - OP(nop), OP(illegal), OP(outl_bus_a),OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 + OP(nop), OP(illegal), OP(outl_bus_a),OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 OP(ins_a_bus), OP(in_a_p1), OP(in_a_p2), OP(illegal), OP(movd_a_p4), OP(movd_a_p5), OP(movd_a_p6), OP(movd_a_p7), - OP(inc_xr0), OP(inc_xr1), OP(jb_0), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 + OP(inc_xr0), OP(inc_xr1), OP(jb_0), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 OP(inc_r0), OP(inc_r1), OP(inc_r2), OP(inc_r3), OP(inc_r4), OP(inc_r5), OP(inc_r6), OP(inc_r7), - OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 + OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 OP(xch_a_r0), OP(xch_a_r1), OP(xch_a_r2), OP(xch_a_r3), OP(xch_a_r4), OP(xch_a_r5), OP(xch_a_r6), OP(xch_a_r7), - OP(xchd_a_xr0), OP(xchd_a_xr1), OP(jb_1), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 + OP(xchd_a_xr0), OP(xchd_a_xr1), OP(jb_1), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 OP(illegal), OP(outl_p1_a), OP(outl_p2_a), OP(illegal), OP(movd_p4_a), OP(movd_p5_a), OP(movd_p6_a), OP(movd_p7_a), - OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 + OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 OP(orl_a_r0), OP(orl_a_r1), OP(orl_a_r2), OP(orl_a_r3), OP(orl_a_r4), OP(orl_a_r5), OP(orl_a_r6), OP(orl_a_r7), - OP(anl_a_xr0), OP(anl_a_xr1), OP(jb_2), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 + OP(anl_a_xr0), OP(anl_a_xr1), OP(jb_2), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 OP(anl_a_r0), OP(anl_a_r1), OP(anl_a_r2), OP(anl_a_r3), OP(anl_a_r4), OP(anl_a_r5), OP(anl_a_r6), OP(anl_a_r7), - OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 + OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 OP(add_a_r0), OP(add_a_r1), OP(add_a_r2), OP(add_a_r3), OP(add_a_r4), OP(add_a_r5), OP(add_a_r6), OP(add_a_r7), - OP(adc_a_xr0), OP(adc_a_xr1), OP(jb_3), OP(illegal), OP(call_3), OP(ent0_clk), OP(jf1), OP(rr_a), // 70 + OP(adc_a_xr0), OP(adc_a_xr1), OP(jb_3), OP(illegal), OP(call_3), OP(ent0_clk), OP(jf1), OP(rr_a), // 70 OP(adc_a_r0), OP(adc_a_r1), OP(adc_a_r2), OP(adc_a_r3), OP(adc_a_r4), OP(adc_a_r5), OP(adc_a_r6), OP(adc_a_r7), - OP(movx_a_xr0), OP(movx_a_xr1), OP(illegal), OP(ret), OP(jmp_4), OP(clr_f0), OP(jni), OP(illegal), // 80 + OP(movx_a_xr0), OP(movx_a_xr1), OP(illegal), OP(ret), OP(jmp_4), OP(clr_f0), OP(jni), OP(illegal), // 80 OP(orl_bus_n), OP(orl_p1_n), OP(orl_p2_n), OP(illegal), OP(orld_p4_a), OP(orld_p5_a), OP(orld_p6_a), OP(orld_p7_a), - OP(movx_xr0_a), OP(movx_xr1_a), OP(jb_4), OP(retr), OP(call_4), OP(cpl_f0), OP(jnz), OP(clr_c), // 90 + OP(movx_xr0_a), OP(movx_xr1_a), OP(jb_4), OP(retr), OP(call_4), OP(cpl_f0), OP(jnz), OP(clr_c), // 90 OP(anl_bus_n), OP(anl_p1_n), OP(anl_p2_n), OP(illegal), OP(anld_p4_a), OP(anld_p5_a), OP(anld_p6_a), OP(anld_p7_a), - OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(clr_f1), OP(illegal), OP(cpl_c), // A0 + OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(clr_f1), OP(illegal), OP(cpl_c), // A0 OP(mov_r0_a), OP(mov_r1_a), OP(mov_r2_a), OP(mov_r3_a), OP(mov_r4_a), OP(mov_r5_a), OP(mov_r6_a), OP(mov_r7_a), - OP(mov_xr0_n), OP(mov_xr1_n), OP(jb_5), OP(jmpp_xa), OP(call_5), OP(cpl_f1), OP(jf0), OP(illegal), // B0 + OP(mov_xr0_n), OP(mov_xr1_n), OP(jb_5), OP(jmpp_xa), OP(call_5), OP(cpl_f1), OP(jf0), OP(illegal), // B0 OP(mov_r0_n), OP(mov_r1_n), OP(mov_r2_n), OP(mov_r3_n), OP(mov_r4_n), OP(mov_r5_n), OP(mov_r6_n), OP(mov_r7_n), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(sel_rb0), OP(jz), OP(mov_a_psw), // C0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(sel_rb0), OP(jz), OP(mov_a_psw), // C0 OP(dec_r0), OP(dec_r1), OP(dec_r2), OP(dec_r3), OP(dec_r4), OP(dec_r5), OP(dec_r6), OP(dec_r7), - OP(xrl_a_xr0), OP(xrl_a_xr1), OP(jb_6), OP(xrl_a_n), OP(call_6), OP(sel_rb1), OP(illegal), OP(mov_psw_a), // D0 + OP(xrl_a_xr0), OP(xrl_a_xr1), OP(jb_6), OP(xrl_a_n), OP(call_6), OP(sel_rb1), OP(illegal), OP(mov_psw_a), // D0 OP(xrl_a_r0), OP(xrl_a_r1), OP(xrl_a_r2), OP(xrl_a_r3), OP(xrl_a_r4), OP(xrl_a_r5), OP(xrl_a_r6), OP(xrl_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(movp3_a_xa),OP(jmp_7), OP(sel_mb0), OP(jnc), OP(rl_a), // E0 + OP(illegal), OP(illegal), OP(illegal), OP(movp3_a_xa),OP(jmp_7), OP(sel_mb0), OP(jnc), OP(rl_a), // E0 OP(djnz_r0), OP(djnz_r1), OP(djnz_r2), OP(djnz_r3), OP(djnz_r4), OP(djnz_r5), OP(djnz_r6), OP(djnz_r7), - OP(mov_a_xr0), OP(mov_a_xr1), OP(jb_7), OP(illegal), OP(call_7), OP(sel_mb1), OP(jc), OP(rlc_a), // F0 + OP(mov_a_xr0), OP(mov_a_xr1), OP(jb_7), OP(illegal), OP(call_7), OP(sel_mb1), OP(jc), OP(rlc_a), // F0 OP(mov_a_r0), OP(mov_a_r1), OP(mov_a_r2), OP(mov_a_r3), OP(mov_a_r4), OP(mov_a_r5), OP(mov_a_r6), OP(mov_a_r7) }; const mcs48_cpu_device::mcs48_ophandler mcs48_cpu_device::s_upi41_opcodes[256] = { - OP(nop), OP(illegal), OP(out_dbb_a), OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 + OP(nop), OP(illegal), OP(out_dbb_a), OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 OP(illegal), OP(in_a_p1), OP(in_a_p2), OP(illegal), OP(movd_a_p4), OP(movd_a_p5), OP(movd_a_p6), OP(movd_a_p7), - OP(inc_xr0), OP(inc_xr1), OP(jb_0), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 + OP(inc_xr0), OP(inc_xr1), OP(jb_0), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 OP(inc_r0), OP(inc_r1), OP(inc_r2), OP(inc_r3), OP(inc_r4), OP(inc_r5), OP(inc_r6), OP(inc_r7), - OP(xch_a_xr0), OP(xch_a_xr1), OP(in_a_dbb), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 + OP(xch_a_xr0), OP(xch_a_xr1), OP(in_a_dbb), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 OP(xch_a_r0), OP(xch_a_r1), OP(xch_a_r2), OP(xch_a_r3), OP(xch_a_r4), OP(xch_a_r5), OP(xch_a_r6), OP(xch_a_r7), - OP(xchd_a_xr0), OP(xchd_a_xr1), OP(jb_1), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 + OP(xchd_a_xr0), OP(xchd_a_xr1), OP(jb_1), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 OP(illegal), OP(outl_p1_a), OP(outl_p2_a), OP(illegal), OP(movd_p4_a), OP(movd_p5_a), OP(movd_p6_a), OP(movd_p7_a), - OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 + OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 OP(orl_a_r0), OP(orl_a_r1), OP(orl_a_r2), OP(orl_a_r3), OP(orl_a_r4), OP(orl_a_r5), OP(orl_a_r6), OP(orl_a_r7), - OP(anl_a_xr0), OP(anl_a_xr1), OP(jb_2), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 + OP(anl_a_xr0), OP(anl_a_xr1), OP(jb_2), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 OP(anl_a_r0), OP(anl_a_r1), OP(anl_a_r2), OP(anl_a_r3), OP(anl_a_r4), OP(anl_a_r5), OP(anl_a_r6), OP(anl_a_r7), - OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 + OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 OP(add_a_r0), OP(add_a_r1), OP(add_a_r2), OP(add_a_r3), OP(add_a_r4), OP(add_a_r5), OP(add_a_r6), OP(add_a_r7), - OP(adc_a_xr0), OP(adc_a_xr1), OP(jb_3), OP(illegal), OP(call_3), OP(illegal), OP(jf1), OP(rr_a), // 70 + OP(adc_a_xr0), OP(adc_a_xr1), OP(jb_3), OP(illegal), OP(call_3), OP(illegal), OP(jf1), OP(rr_a), // 70 OP(adc_a_r0), OP(adc_a_r1), OP(adc_a_r2), OP(adc_a_r3), OP(adc_a_r4), OP(adc_a_r5), OP(adc_a_r6), OP(adc_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(clr_f0), OP(jobf), OP(illegal), // 80 + OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(clr_f0), OP(jobf), OP(illegal), // 80 OP(illegal), OP(orl_p1_n), OP(orl_p2_n), OP(illegal), OP(orld_p4_a), OP(orld_p5_a), OP(orld_p6_a), OP(orld_p7_a), - OP(mov_sts_a), OP(illegal), OP(jb_4), OP(retr), OP(call_4), OP(cpl_f0), OP(jnz), OP(clr_c), // 90 + OP(mov_sts_a), OP(illegal), OP(jb_4), OP(retr), OP(call_4), OP(cpl_f0), OP(jnz), OP(clr_c), // 90 OP(illegal), OP(anl_p1_n), OP(anl_p2_n), OP(illegal), OP(anld_p4_a), OP(anld_p5_a), OP(anld_p6_a), OP(anld_p7_a), - OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(clr_f1), OP(illegal), OP(cpl_c), // A0 + OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(clr_f1), OP(illegal), OP(cpl_c), // A0 OP(mov_r0_a), OP(mov_r1_a), OP(mov_r2_a), OP(mov_r3_a), OP(mov_r4_a), OP(mov_r5_a), OP(mov_r6_a), OP(mov_r7_a), - OP(mov_xr0_n), OP(mov_xr1_n), OP(jb_5), OP(jmpp_xa), OP(call_5), OP(cpl_f1), OP(jf0), OP(illegal), // B0 + OP(mov_xr0_n), OP(mov_xr1_n), OP(jb_5), OP(jmpp_xa), OP(call_5), OP(cpl_f1), OP(jf0), OP(illegal), // B0 OP(mov_r0_n), OP(mov_r1_n), OP(mov_r2_n), OP(mov_r3_n), OP(mov_r4_n), OP(mov_r5_n), OP(mov_r6_n), OP(mov_r7_n), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(sel_rb0), OP(jz), OP(mov_a_psw), // C0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(sel_rb0), OP(jz), OP(mov_a_psw), // C0 OP(dec_r0), OP(dec_r1), OP(dec_r2), OP(dec_r3), OP(dec_r4), OP(dec_r5), OP(dec_r6), OP(dec_r7), - OP(xrl_a_xr0), OP(xrl_a_xr1), OP(jb_6), OP(xrl_a_n), OP(call_6), OP(sel_rb1), OP(jnibf), OP(mov_psw_a), // D0 + OP(xrl_a_xr0), OP(xrl_a_xr1), OP(jb_6), OP(xrl_a_n), OP(call_6), OP(sel_rb1), OP(jnibf), OP(mov_psw_a), // D0 OP(xrl_a_r0), OP(xrl_a_r1), OP(xrl_a_r2), OP(xrl_a_r3), OP(xrl_a_r4), OP(xrl_a_r5), OP(xrl_a_r6), OP(xrl_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(movp3_a_xa),OP(jmp_7), OP(en_dma), OP(jnc), OP(rl_a), // E0 + OP(illegal), OP(illegal), OP(illegal), OP(movp3_a_xa),OP(jmp_7), OP(en_dma), OP(jnc), OP(rl_a), // E0 OP(djnz_r0), OP(djnz_r1), OP(djnz_r2), OP(djnz_r3), OP(djnz_r4), OP(djnz_r5), OP(djnz_r6), OP(djnz_r7), - OP(mov_a_xr0), OP(mov_a_xr1), OP(jb_7), OP(illegal), OP(call_7), OP(en_flags), OP(jc), OP(rlc_a), // F0 + OP(mov_a_xr0), OP(mov_a_xr1), OP(jb_7), OP(illegal), OP(call_7), OP(en_flags), OP(jc), OP(rlc_a), // F0 OP(mov_a_r0), OP(mov_a_r1), OP(mov_a_r2), OP(mov_a_r3), OP(mov_a_r4), OP(mov_a_r5), OP(mov_a_r6), OP(mov_a_r7) }; const mcs48_cpu_device::mcs48_ophandler mcs48_cpu_device::s_i8021_opcodes[256] = { - OP(nop), OP(illegal), OP(illegal), OP(add_a_n), OP(jmp_0), OP(illegal), OP(illegal), OP(dec_a), // 00 + OP(nop), OP(illegal), OP(illegal), OP(add_a_n), OP(jmp_0), OP(illegal), OP(illegal), OP(dec_a), // 00 OP(in_a_p0), OP(in_a_p1), OP(in_a_p2), OP(illegal), OP(movd_a_p4), OP(movd_a_p5), OP(movd_a_p6), OP(movd_a_p7), - OP(inc_xr0), OP(inc_xr1), OP(illegal), OP(adc_a_n), OP(call_0), OP(illegal), OP(jtf), OP(inc_a), // 10 + OP(inc_xr0), OP(inc_xr1), OP(illegal), OP(adc_a_n), OP(call_0), OP(illegal), OP(jtf), OP(inc_a), // 10 OP(inc_r0), OP(inc_r1), OP(inc_r2), OP(inc_r3), OP(inc_r4), OP(inc_r5), OP(inc_r6), OP(inc_r7), - OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(illegal), OP(illegal), OP(clr_a), // 20 + OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(illegal), OP(illegal), OP(clr_a), // 20 OP(xch_a_r0), OP(xch_a_r1), OP(xch_a_r2), OP(xch_a_r3), OP(xch_a_r4), OP(xch_a_r5), OP(xch_a_r6), OP(xch_a_r7), - OP(xchd_a_xr0), OP(xchd_a_xr1), OP(illegal), OP(illegal), OP(call_1), OP(illegal), OP(illegal), OP(cpl_a), // 30 + OP(xchd_a_xr0), OP(xchd_a_xr1), OP(illegal), OP(illegal), OP(call_1), OP(illegal), OP(illegal), OP(cpl_a), // 30 OP(illegal), OP(outl_p1_a), OP(outl_p2_a), OP(illegal), OP(movd_p4_a), OP(movd_p5_a), OP(movd_p6_a), OP(movd_p7_a), - OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 + OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 OP(orl_a_r0), OP(orl_a_r1), OP(orl_a_r2), OP(orl_a_r3), OP(orl_a_r4), OP(orl_a_r5), OP(orl_a_r6), OP(orl_a_r7), - OP(anl_a_xr0), OP(anl_a_xr1), OP(illegal), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 + OP(anl_a_xr0), OP(anl_a_xr1), OP(illegal), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 OP(anl_a_r0), OP(anl_a_r1), OP(anl_a_r2), OP(anl_a_r3), OP(anl_a_r4), OP(anl_a_r5), OP(anl_a_r6), OP(anl_a_r7), - OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 + OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 OP(add_a_r0), OP(add_a_r1), OP(add_a_r2), OP(add_a_r3), OP(add_a_r4), OP(add_a_r5), OP(add_a_r6), OP(add_a_r7), - OP(adc_a_xr0), OP(adc_a_xr1), OP(illegal), OP(illegal), OP(call_3), OP(illegal), OP(illegal), OP(rr_a), // 70 + OP(adc_a_xr0), OP(adc_a_xr1), OP(illegal), OP(illegal), OP(call_3), OP(illegal), OP(illegal), OP(rr_a), // 70 OP(adc_a_r0), OP(adc_a_r1), OP(adc_a_r2), OP(adc_a_r3), OP(adc_a_r4), OP(adc_a_r5), OP(adc_a_r6), OP(adc_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(illegal), OP(illegal), OP(illegal), // 80 + OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(illegal), OP(illegal), OP(illegal), // 80 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(orld_p4_a), OP(orld_p5_a), OP(orld_p6_a), OP(orld_p7_a), - OP(outl_p0_a), OP(illegal), OP(illegal), OP(illegal), OP(call_4), OP(illegal), OP(jnz), OP(clr_c), // 90 + OP(outl_p0_a), OP(illegal), OP(illegal), OP(illegal), OP(call_4), OP(illegal), OP(jnz), OP(clr_c), // 90 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(anld_p4_a), OP(anld_p5_a), OP(anld_p6_a), OP(anld_p7_a), - OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(illegal), OP(illegal), OP(cpl_c), // A0 + OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(illegal), OP(illegal), OP(cpl_c), // A0 OP(mov_r0_a), OP(mov_r1_a), OP(mov_r2_a), OP(mov_r3_a), OP(mov_r4_a), OP(mov_r5_a), OP(mov_r6_a), OP(mov_r7_a), - OP(mov_xr0_n), OP(mov_xr1_n), OP(illegal), OP(jmpp_xa), OP(call_5), OP(illegal), OP(illegal), OP(illegal), // B0 + OP(mov_xr0_n), OP(mov_xr1_n), OP(illegal), OP(jmpp_xa), OP(call_5), OP(illegal), OP(illegal), OP(illegal), // B0 OP(mov_r0_n), OP(mov_r1_n), OP(mov_r2_n), OP(mov_r3_n), OP(mov_r4_n), OP(mov_r5_n), OP(mov_r6_n), OP(mov_r7_n), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(illegal), OP(jz), OP(illegal), // C0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(illegal), OP(jz), OP(illegal), // C0 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), - OP(xrl_a_xr0), OP(xrl_a_xr1), OP(illegal), OP(xrl_a_n), OP(call_6), OP(illegal), OP(illegal), OP(illegal), // D0 + OP(xrl_a_xr0), OP(xrl_a_xr1), OP(illegal), OP(xrl_a_n), OP(call_6), OP(illegal), OP(illegal), OP(illegal), // D0 OP(xrl_a_r0), OP(xrl_a_r1), OP(xrl_a_r2), OP(xrl_a_r3), OP(xrl_a_r4), OP(xrl_a_r5), OP(xrl_a_r6), OP(xrl_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_7), OP(illegal), OP(jnc), OP(rl_a), // E0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_7), OP(illegal), OP(jnc), OP(rl_a), // E0 OP(djnz_r0), OP(djnz_r1), OP(djnz_r2), OP(djnz_r3), OP(djnz_r4), OP(djnz_r5), OP(djnz_r6), OP(djnz_r7), - OP(mov_a_xr0), OP(mov_a_xr1), OP(illegal), OP(illegal), OP(call_7), OP(illegal), OP(jc), OP(rlc_a), // F0 + OP(mov_a_xr0), OP(mov_a_xr1), OP(illegal), OP(illegal), OP(call_7), OP(illegal), OP(jc), OP(rlc_a), // F0 OP(mov_a_r0), OP(mov_a_r1), OP(mov_a_r2), OP(mov_a_r3), OP(mov_a_r4), OP(mov_a_r5), OP(mov_a_r6), OP(mov_a_r7) }; const mcs48_cpu_device::mcs48_ophandler mcs48_cpu_device::s_i8022_opcodes[256] = { - OP(nop), OP(illegal), OP(illegal), OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 + OP(nop), OP(illegal), OP(illegal), OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), // 00 OP(in_a_p0), OP(in_a_p1), OP(in_a_p2), OP(illegal), OP(movd_a_p4), OP(movd_a_p5), OP(movd_a_p6), OP(movd_a_p7), - OP(inc_xr0), OP(inc_xr1), OP(illegal), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 + OP(inc_xr0), OP(inc_xr1), OP(illegal), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), // 10 OP(inc_r0), OP(inc_r1), OP(inc_r2), OP(inc_r3), OP(inc_r4), OP(inc_r5), OP(inc_r6), OP(inc_r7), - OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 + OP(xch_a_xr0), OP(xch_a_xr1), OP(illegal), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), // 20 OP(xch_a_r0), OP(xch_a_r1), OP(xch_a_r2), OP(xch_a_r3), OP(xch_a_r4), OP(xch_a_r5), OP(xch_a_r6), OP(xch_a_r7), - OP(xchd_a_xr0), OP(xchd_a_xr1), OP(illegal), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 + OP(xchd_a_xr0), OP(xchd_a_xr1), OP(illegal), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), // 30 OP(illegal), OP(outl_p1_a), OP(outl_p2_a), OP(illegal), OP(movd_p4_a), OP(movd_p5_a), OP(movd_p6_a), OP(movd_p7_a), - OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 + OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), // 40 OP(orl_a_r0), OP(orl_a_r1), OP(orl_a_r2), OP(orl_a_r3), OP(orl_a_r4), OP(orl_a_r5), OP(orl_a_r6), OP(orl_a_r7), - OP(anl_a_xr0), OP(anl_a_xr1), OP(illegal), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 + OP(anl_a_xr0), OP(anl_a_xr1), OP(illegal), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), // 50 OP(anl_a_r0), OP(anl_a_r1), OP(anl_a_r2), OP(anl_a_r3), OP(anl_a_r4), OP(anl_a_r5), OP(anl_a_r6), OP(anl_a_r7), - OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 + OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), // 60 OP(add_a_r0), OP(add_a_r1), OP(add_a_r2), OP(add_a_r3), OP(add_a_r4), OP(add_a_r5), OP(add_a_r6), OP(add_a_r7), - OP(adc_a_xr0), OP(adc_a_xr1), OP(illegal), OP(illegal), OP(call_3), OP(illegal), OP(illegal), OP(rr_a), // 70 + OP(adc_a_xr0), OP(adc_a_xr1), OP(illegal), OP(illegal), OP(call_3), OP(illegal), OP(illegal), OP(rr_a), // 70 OP(adc_a_r0), OP(adc_a_r1), OP(adc_a_r2), OP(adc_a_r3), OP(adc_a_r4), OP(adc_a_r5), OP(adc_a_r6), OP(adc_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(illegal), OP(illegal), OP(illegal), // 80 + OP(illegal), OP(illegal), OP(illegal), OP(ret), OP(jmp_4), OP(illegal), OP(illegal), OP(illegal), // 80 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(orld_p4_a), OP(orld_p5_a), OP(orld_p6_a), OP(orld_p7_a), - OP(outl_p0_a), OP(illegal), OP(illegal), OP(retr), OP(call_4), OP(illegal), OP(jnz), OP(clr_c), // 90 + OP(outl_p0_a), OP(illegal), OP(illegal), OP(retr), OP(call_4), OP(illegal), OP(jnz), OP(clr_c), // 90 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(anld_p4_a), OP(anld_p5_a), OP(anld_p6_a), OP(anld_p7_a), - OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(illegal), OP(illegal), OP(cpl_c), // A0 + OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(illegal), OP(illegal), OP(cpl_c), // A0 OP(mov_r0_a), OP(mov_r1_a), OP(mov_r2_a), OP(mov_r3_a), OP(mov_r4_a), OP(mov_r5_a), OP(mov_r6_a), OP(mov_r7_a), - OP(mov_xr0_n), OP(mov_xr1_n), OP(illegal), OP(jmpp_xa), OP(call_5), OP(illegal), OP(illegal), OP(illegal), // B0 + OP(mov_xr0_n), OP(mov_xr1_n), OP(illegal), OP(jmpp_xa), OP(call_5), OP(illegal), OP(illegal), OP(illegal), // B0 OP(mov_r0_n), OP(mov_r1_n), OP(mov_r2_n), OP(mov_r3_n), OP(mov_r4_n), OP(mov_r5_n), OP(mov_r6_n), OP(mov_r7_n), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(illegal), OP(jz), OP(illegal), // C0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(illegal), OP(jz), OP(illegal), // C0 OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(illegal), - OP(xrl_a_xr0), OP(xrl_a_xr1), OP(illegal), OP(xrl_a_n), OP(call_6), OP(illegal), OP(illegal), OP(illegal), // D0 + OP(xrl_a_xr0), OP(xrl_a_xr1), OP(illegal), OP(xrl_a_n), OP(call_6), OP(illegal), OP(illegal), OP(illegal), // D0 OP(xrl_a_r0), OP(xrl_a_r1), OP(xrl_a_r2), OP(xrl_a_r3), OP(xrl_a_r4), OP(xrl_a_r5), OP(xrl_a_r6), OP(xrl_a_r7), - OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_7), OP(illegal), OP(jnc), OP(rl_a), // E0 + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_7), OP(illegal), OP(jnc), OP(rl_a), // E0 OP(djnz_r0), OP(djnz_r1), OP(djnz_r2), OP(djnz_r3), OP(djnz_r4), OP(djnz_r5), OP(djnz_r6), OP(djnz_r7), - OP(mov_a_xr0), OP(mov_a_xr1), OP(illegal), OP(illegal), OP(call_7), OP(illegal), OP(jc), OP(rlc_a), // F0 + OP(mov_a_xr0), OP(mov_a_xr1), OP(illegal), OP(illegal), OP(call_7), OP(illegal), OP(jc), OP(rlc_a), // F0 OP(mov_a_r0), OP(mov_a_r1), OP(mov_a_r2), OP(mov_a_r3), OP(mov_a_r4), OP(mov_a_r5), OP(mov_a_r6), OP(mov_a_r7) }; @@ -1307,7 +1307,7 @@ void mcs48_cpu_device::burn_cycles(int count) // if the timer is enabled, accumulate prescaler cycles if (m_timecount_enabled & TIMER_ENABLED) { - uint8_t oldtimer = m_timer; + u8 oldtimer = m_timer; m_prescaler += count; m_timer += m_prescaler >> 5; m_prescaler &= 0x1f; @@ -1381,7 +1381,7 @@ void mcs48_cpu_device::execute_run() read -------------------------------------------------*/ -uint8_t upi41_cpu_device::upi41_master_r(offs_t offset) +u8 upi41_cpu_device::upi41_master_r(offs_t offset) { // if just reading the status, return it if (offset & 1) @@ -1421,7 +1421,7 @@ TIMER_CALLBACK_MEMBER(upi41_cpu_device::master_callback) m_f1 = a0; } -void upi41_cpu_device::upi41_master_w(offs_t offset, uint8_t data) +void upi41_cpu_device::upi41_master_w(offs_t offset, u8 data) { machine().scheduler().synchronize(timer_expired_delegate(FUNC(upi41_cpu_device::master_callback), this), (offset << 8) | data); } @@ -1488,9 +1488,9 @@ void mcs48_cpu_device::state_string_export(const device_state_entry &entry, std: { case STATE_GENFLAGS: str = string_format("%c%c%c %c%c%c%c%c%c%c%c", - m_irq_state ? 'I':'.', - m_a11 ? 'M':'.', - m_f1 ? '1':'.', + m_irq_state ? 'I':'.', + m_a11 ? 'M':'.', + m_f1 ? '1':'.', m_psw & 0x80 ? 'C':'.', m_psw & 0x40 ? 'A':'.', m_psw & 0x20 ? '0':'.', diff --git a/src/devices/cpu/mcs48/mcs48.h b/src/devices/cpu/mcs48/mcs48.h index 8cb63aafb41..772a6c8db3d 100644 --- a/src/devices/cpu/mcs48/mcs48.h +++ b/src/devices/cpu/mcs48/mcs48.h @@ -123,8 +123,8 @@ public: // PROG line to 8243 expander auto prog_out_cb() { return m_prog_out_cb.bind(); } - uint8_t p1_r() { return m_p1; } - uint8_t p2_r() { return m_p2; } + u8 p1_r() { return m_p1; } + u8 p2_r() { return m_p2; } template void set_t0_clk_cb(T &&... args) { m_t0_clk_func.set(std::forward(args)...); } @@ -135,7 +135,7 @@ protected: typedef void (mcs48_cpu_device::*mcs48_ophandler)(); // construction/destruction - mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int rom_size, int ram_size, uint8_t feature_mask, const mcs48_ophandler *opcode_table); + mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int rom_size, int ram_size, u8 feature_mask, const mcs48_ophandler *opcode_table); // device-level overrides virtual void device_start() override; @@ -144,11 +144,11 @@ protected: virtual void device_post_load() override { update_regptr(); } // device_execute_interface overrides - virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 15 - 1) / 15; } - virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 15); } - virtual uint32_t execute_min_cycles() const noexcept override { return 1; } - virtual uint32_t execute_max_cycles() const noexcept override { return 2+2; } // opcode+irq - virtual uint32_t execute_input_lines() const noexcept override { return 2; } + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 15 - 1) / 15; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 15); } + virtual u32 execute_min_cycles() const noexcept override { return 1; } + virtual u32 execute_max_cycles() const noexcept override { return 2+2; } // opcode+irq + virtual u32 execute_input_lines() const noexcept override { return 2; } virtual void execute_run() override; virtual void execute_set_input(int inputnum, int state) override; @@ -177,49 +177,49 @@ protected: clock_update_delegate m_t0_clk_func; devcb_write_line m_prog_out_cb; - uint16_t m_prevpc; // 16-bit previous program counter - uint16_t m_pc; // 16-bit program counter - - uint8_t m_a; // 8-bit accumulator - uint8_t *m_regptr; // pointer to r0-r7 - uint8_t m_psw; // 8-bit PSW - bool m_f1; // F1 flag (F0 is in PSW) - uint16_t m_a11; // A11 value, either 0x000 or 0x800 - uint8_t m_p1; // 8-bit latched port 1 - uint8_t m_p2; // 8-bit latched port 2 - uint8_t m_ea; // 1-bit latched ea input - uint8_t m_timer; // 8-bit timer - uint8_t m_prescaler; // 5-bit timer prescaler - uint8_t m_t1_history; // 8-bit history of the T1 input - uint8_t m_sts; // 4-bit status register + OBF/IBF flags (UPI-41 only) - uint8_t m_dbbi; // 8-bit input data buffer (UPI-41 only) - uint8_t m_dbbo; // 8-bit output data buffer (UPI-41 only) - - bool m_irq_state; // true if the IRQ line is active - bool m_irq_polled; // true if last instruction was JNI (and not taken) - bool m_irq_in_progress; // true if an IRQ is in progress - bool m_timer_overflow; // true on a timer overflow; cleared by taking interrupt - bool m_timer_flag; // true on a timer overflow; cleared on JTF - bool m_tirq_enabled; // true if the timer IRQ is enabled - bool m_xirq_enabled; // true if the external IRQ is enabled - uint8_t m_timecount_enabled; // bitmask of timer/counter enabled - bool m_flags_enabled; // true if I/O flags have been enabled (UPI-41 only) - bool m_dma_enabled; // true if DMA has been enabled (UPI-41 only) - - int m_icount; + u16 m_prevpc; // 16-bit previous program counter + u16 m_pc; // 16-bit program counter + + u8 m_a; // 8-bit accumulator + u8 *m_regptr; // pointer to r0-r7 + u8 m_psw; // 8-bit PSW + bool m_f1; // F1 flag (F0 is in PSW) + u16 m_a11; // A11 value, either 0x000 or 0x800 + u8 m_p1; // 8-bit latched port 1 + u8 m_p2; // 8-bit latched port 2 + u8 m_ea; // 1-bit latched ea input + u8 m_timer; // 8-bit timer + u8 m_prescaler; // 5-bit timer prescaler + u8 m_t1_history; // 8-bit history of the T1 input + u8 m_sts; // 4-bit status register + OBF/IBF flags (UPI-41 only) + u8 m_dbbi; // 8-bit input data buffer (UPI-41 only) + u8 m_dbbo; // 8-bit output data buffer (UPI-41 only) + + bool m_irq_state; // true if the IRQ line is active + bool m_irq_polled; // true if last instruction was JNI (and not taken) + bool m_irq_in_progress; // true if an IRQ is in progress + bool m_timer_overflow; // true on a timer overflow; cleared by taking interrupt + bool m_timer_flag; // true on a timer overflow; cleared on JTF + bool m_tirq_enabled; // true if the timer IRQ is enabled + bool m_xirq_enabled; // true if the external IRQ is enabled + u8 m_timecount_enabled; // bitmask of timer/counter enabled + bool m_flags_enabled; // true if I/O flags have been enabled (UPI-41 only) + bool m_dma_enabled; // true if DMA has been enabled (UPI-41 only) + + int m_icount; // Memory spaces memory_access<12, 0, 0, ENDIANNESS_LITTLE>::cache m_program; memory_access<8, 0, 0, ENDIANNESS_LITTLE>::specific m_data; memory_access<8, 0, 0, ENDIANNESS_LITTLE>::specific m_io; - required_shared_ptr m_dataptr; + required_shared_ptr m_dataptr; - uint8_t m_feature_mask; // processor feature flags - uint16_t m_rom_size; // internal rom size - uint16_t m_ram_size; // internal ram size + u8 m_feature_mask; // processor feature flags + u16 m_rom_size; // internal rom size + u16 m_ram_size; // internal ram size - uint8_t m_rtemp; // temporary for import/export + u8 m_rtemp; // temporary for import/export static const mcs48_ophandler s_mcs48_opcodes[256]; static const mcs48_ophandler s_upi41_opcodes[256]; @@ -231,36 +231,36 @@ protected: void data_map(address_map &map); // ROM is mapped to AS_PROGRAM - uint8_t program_r(offs_t a) { return m_program.read_byte(a); } + u8 program_r(offs_t a) { return m_program.read_byte(a); } // RAM is mapped to AS_DATA - uint8_t ram_r(offs_t a) { return m_data.read_byte(a); } - void ram_w(offs_t a, uint8_t v) { m_data.write_byte(a, v); } + u8 ram_r(offs_t a) { return m_data.read_byte(a); } + void ram_w(offs_t a, u8 v) { m_data.write_byte(a, v); } // ports are mapped to AS_IO and callbacks - uint8_t ext_r(offs_t a) { return m_io.read_byte(a); } - void ext_w(offs_t a, uint8_t v) { m_io.write_byte(a, v); } - uint8_t port_r(offs_t a) { return m_port_in_cb[a - 1](); } - void port_w(offs_t a, uint8_t v) { m_port_out_cb[a - 1](v); } - int test_r(offs_t a) { return m_test_in_cb[a](); } - uint8_t bus_r() { return m_bus_in_cb(); } - void bus_w(uint8_t v) { m_bus_out_cb(v); } - void prog_w(int v) { m_prog_out_cb(v); } - - uint8_t opcode_fetch(); - uint8_t argument_fetch(); + u8 ext_r(offs_t a) { return m_io.read_byte(a); } + void ext_w(offs_t a, u8 v) { m_io.write_byte(a, v); } + u8 port_r(offs_t a) { return m_port_in_cb[a - 1](); } + void port_w(offs_t a, u8 v) { m_port_out_cb[a - 1](v); } + int test_r(offs_t a) { return m_test_in_cb[a](); } + u8 bus_r() { return m_bus_in_cb(); } + void bus_w(u8 v) { m_bus_out_cb(v); } + void prog_w(int v) { m_prog_out_cb(v); } + + u8 opcode_fetch(); + u8 argument_fetch(); void update_regptr(); void update_ea(); void push_pc_psw(); void pull_pc_psw(); void pull_pc(); - void execute_add(uint8_t dat); - void execute_addc(uint8_t dat); - void execute_jmp(uint16_t address); - void execute_call(uint16_t address); + void execute_add(u8 dat); + void execute_addc(u8 dat); + void execute_jmp(u16 address); + void execute_call(u16 address); void execute_jcc(bool result); - uint8_t p2_mask(); - void expander_operation(expander_op operation, uint8_t port); + u8 p2_mask(); + void expander_operation(expander_op operation, u8 port); void check_irqs(); void burn_cycles(int count); @@ -514,108 +514,108 @@ public: auto p0_out_cb() { return bus_out_cb(); } // construction/destruction - i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); protected: // device_execute_interface overrides - virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 30 - 1) / 30; } - virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 30); } + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 30 - 1) / 30; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 30); } }; class i8022_device : public mcs48_cpu_device { public: // construction/destruction - i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); protected: // device_execute_interface overrides - virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 30 - 1) / 30; } - virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 30); } + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 30 - 1) / 30; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 30); } }; class i8035_device : public mcs48_cpu_device { public: // construction/destruction - i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8048_device : public mcs48_cpu_device { public: // construction/destruction - i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8648_device : public mcs48_cpu_device { public: // construction/destruction - i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8748_device : public mcs48_cpu_device { public: // construction/destruction - i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8039_device : public mcs48_cpu_device { public: // construction/destruction - i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8049_device : public mcs48_cpu_device { public: // construction/destruction - i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8749_device : public mcs48_cpu_device { public: // construction/destruction - i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8040_device : public mcs48_cpu_device { public: // construction/destruction - i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8050_device : public mcs48_cpu_device { public: // construction/destruction - i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class mb8884_device : public mcs48_cpu_device { public: // construction/destruction - mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class n7751_device : public mcs48_cpu_device { public: // construction/destruction - n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class m58715_device : public mcs48_cpu_device { public: // construction/destruction - m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -623,12 +623,12 @@ class upi41_cpu_device : public mcs48_cpu_device { public: // functions for talking to the input/output buffers on the UPI41-class chips - uint8_t upi41_master_r(offs_t offset); - void upi41_master_w(offs_t offset, uint8_t data); + u8 upi41_master_r(offs_t offset); + void upi41_master_w(offs_t offset, u8 data); protected: // construction/destruction - upi41_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int rom_size, int ram_size); + upi41_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int rom_size, int ram_size); TIMER_CALLBACK_MEMBER(master_callback); }; @@ -637,56 +637,56 @@ class i8041a_device : public upi41_cpu_device { public: // construction/destruction - i8041a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8041a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8741a_device : public upi41_cpu_device { public: // construction/destruction - i8741a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8741a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8041ah_device : public upi41_cpu_device { public: // construction/destruction - i8041ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8041ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8741ah_device : public upi41_cpu_device { public: // construction/destruction - i8741ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8741ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8042_device : public upi41_cpu_device { public: // construction/destruction - i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8742_device : public upi41_cpu_device { public: // construction/destruction - i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8042ah_device : public upi41_cpu_device { public: // construction/destruction - i8042ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8042ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class i8742ah_device : public upi41_cpu_device { public: // construction/destruction - i8742ah_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + i8742ah_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; diff --git a/src/devices/cpu/mcs48/mcs48dsm.cpp b/src/devices/cpu/mcs48/mcs48dsm.cpp index 3434be06940..d35b18943a0 100644 --- a/src/devices/cpu/mcs48/mcs48dsm.cpp +++ b/src/devices/cpu/mcs48/mcs48dsm.cpp @@ -2,8 +2,6 @@ // copyright-holders:Aaron Giles /*************************************************************************** - mcs48dsm.c - Simple MCS-48/UPI-41 disassembler. Written by Aaron Giles diff --git a/src/devices/cpu/mcs48/mcs48dsm.h b/src/devices/cpu/mcs48/mcs48dsm.h index 38d6c899183..af437879212 100644 --- a/src/devices/cpu/mcs48/mcs48dsm.h +++ b/src/devices/cpu/mcs48/mcs48dsm.h @@ -2,14 +2,11 @@ // copyright-holders:Aaron Giles /*************************************************************************** - mcs48dsm.c - Simple MCS-48/UPI-41 disassembler. Written by Aaron Giles ***************************************************************************/ - #ifndef MAME_CPU_MCS48_MCS48DASM_H #define MAME_CPU_MCS48_MCS48DASM_H -- cgit v1.2.3