From 54859a237a3791356fc56c38ad75d17d67e6e1dc Mon Sep 17 00:00:00 2001 From: Vas Crabb Date: Sun, 12 May 2024 04:02:38 +1000 Subject: cpu/upd7725: Mask address for data RAM accesses. [dink] --- src/devices/cpu/upd7725/upd7725.cpp | 6 +++--- src/devices/cpu/upd7725/upd7725.h | 28 ++++++++++++++-------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/devices/cpu/upd7725/upd7725.cpp b/src/devices/cpu/upd7725/upd7725.cpp index 45f685c1370..c8d079cc84c 100644 --- a/src/devices/cpu/upd7725/upd7725.cpp +++ b/src/devices/cpu/upd7725/upd7725.cpp @@ -384,7 +384,7 @@ void necdsp_device::exec_op(uint32_t opcode) { case 12: regs.idb = bitswap<16>(regs.si, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); break; //LSB = first bit in from serial, 'reversed' SI register order case 13: regs.idb = regs.k; break; case 14: regs.idb = regs.l; break; - case 15: regs.idb = dataRAM[regs.dp]; break; + case 15: regs.idb = dataRAM[regs.dp & 0x07ff]; break; } if(alu) { @@ -573,10 +573,10 @@ void necdsp_device::exec_ld(uint32_t opcode) { case 9: regs.so = id; break; //MSB first output, output tapped at bit 15 shifting left case 10: regs.k = id; break; case 11: regs.k = id; regs.l = m_data.read_word(regs.rp); break; - case 12: regs.l = id; regs.k = dataRAM[regs.dp | 0x40]; break; + case 12: regs.l = id; regs.k = dataRAM[(regs.dp & 0x7ff) | 0x40]; break; case 13: regs.l = id; break; case 14: regs.trb = id; break; - case 15: dataRAM[regs.dp] = id; break; + case 15: dataRAM[regs.dp & 0x7ff] = id; break; } } diff --git a/src/devices/cpu/upd7725/upd7725.h b/src/devices/cpu/upd7725/upd7725.h index ed17af002eb..e1f7703c369 100644 --- a/src/devices/cpu/upd7725/upd7725.h +++ b/src/devices/cpu/upd7725/upd7725.h @@ -43,18 +43,18 @@ protected: // construction/destruction necdsp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t abits, uint32_t dbits); - // device-level overrides + // device_t implementation virtual void device_start() override; virtual void device_reset() override; - // device_execute_interface overrides + // device_execute_interface implementation virtual uint32_t execute_min_cycles() const noexcept override; virtual uint32_t execute_max_cycles() const noexcept override; virtual uint32_t execute_input_lines() const noexcept override; virtual void execute_run() override; virtual void execute_set_input(int inputnum, int state) override; - // device_memory_interface overrides + // device_memory_interface implementation virtual space_config_vector memory_space_config() const override; // device_state_interface overrides @@ -62,7 +62,7 @@ protected: virtual void state_export(const device_state_entry &entry) override; virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; - // device_disasm_interface overrides + // device_disasm_interface implementation virtual std::unique_ptr create_disassembler() override; // inline data @@ -75,12 +75,12 @@ private: { bool s1, s0, c, z, ov1, ov0; - inline operator unsigned() const + operator unsigned() const { - return (s1 << 5) + (s0 << 4) + (c << 3) + (z << 2) + (ov1 << 1) + (ov0 << 0); + return (s1 << 5) | (s0 << 4) | (c << 3) | (z << 2) | (ov1 << 1) | (ov0 << 0); } - inline unsigned operator=(unsigned d) + unsigned operator=(unsigned d) { s1 = d & 0x20; s0 = d & 0x10; c = d & 0x08; z = d & 0x04; ov1 = d & 0x02; ov0 = d & 0x01; return d; @@ -91,14 +91,14 @@ private: { bool rqm, usf1, usf0, drs, dma, drc, soc, sic, ei, p1, p0; - inline operator unsigned() const + operator unsigned() const { - return (rqm << 15) + (usf1 << 14) + (usf0 << 13) + (drs << 12) - + (dma << 11) + (drc << 10) + (soc << 9) + (sic << 8) - + (ei << 7) + (p1 << 1) + (p0 << 0); + return (rqm << 15) | (usf1 << 14) | (usf0 << 13) | (drs << 12) + | (dma << 11) | (drc << 10) | (soc << 9) | (sic << 8) + | (ei << 7) | (p1 << 1) | (p0 << 0); } - inline unsigned operator=(unsigned d) + unsigned operator=(unsigned d) { rqm = d & 0x8000; usf1 = d & 0x4000; usf0 = d & 0x2000; drs = d & 0x1000; dma = d & 0x0800; drc = d & 0x0400; soc = d & 0x0200; sic = d & 0x0100; @@ -175,8 +175,8 @@ public: // construction/destruction upd96050_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - uint16_t dataram_r(uint16_t addr) { return dataRAM[addr]; } - void dataram_w(uint16_t addr, uint16_t data) { dataRAM[addr] = data; } + uint16_t dataram_r(uint16_t addr) { return dataRAM[addr & 0x07ff]; } + void dataram_w(uint16_t addr, uint16_t data) { dataRAM[addr & 0x07ff] = data; } }; // device type definition -- cgit v1.2.3