From 39d8cf6ab2bb2a76eb5beb3fc21969e12667ba5f Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Tue, 4 Aug 2020 01:36:32 -0700 Subject: More documentation updates, cleanups --- src/lib/netlist/macro/nlm_ttl74xx.cpp | 1528 +++++++++++++++++++-------------- 1 file changed, 881 insertions(+), 647 deletions(-) diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp index f0fc0102900..c5b66252b41 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.cpp +++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp @@ -490,14 +490,14 @@ static NETLIST_START(TTL_7420_DIP) ) NETLIST_END() -//- Identifier: 54/7421 -//- Title: Dual 4-Input Positive AND Gate +//- Identifier: 54LS21/DM54LS21/DM74LS21 +//- Title: Dual 4-Input AND Gates //- Description: This device contains two independent 4-input gates each of which performs the logic AND function. //- Pinalias: A1,B1,NC,C1,D1,Y1,GND,Y2,A2,B2,NC,C2,D2,VCC //- Package: DIP -//- NamingConvention: Naming conventions follow National Semiconductor style +//- NamingConvention: Naming conventions follow National Semiconductor datasheet //- FunctionTable: -//- https://pdf1.alldatasheet.com/datasheet-pdf/view/124906/ETC1/7421.html +//- https://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006356.PDF //- //- +---+---+---+---++---+ //- | A | B | C | D || Y | @@ -610,64 +610,62 @@ static NETLIST_START(TTL_7427_DIP) ) NETLIST_END() -/* - * DM7430: 8-Input NAND Gate - * - * _______ - * Y = ABCDEFGH - * +---+---+---+---+---+---+---+---++---+ - * | A | B | C | D | E | F | G | H || Y | - * +===+===+===+===+===+===+===+===++===+ - * | X | X | X | X | X | X | X | 0 || 1 | - * | X | X | X | X | X | X | 0 | X || 1 | - * | X | X | X | X | X | 0 | X | X || 1 | - * | X | X | X | X | 0 | X | X | X || 1 | - * | X | X | X | 0 | X | X | X | X || 1 | - * | X | X | 0 | X | X | X | X | X || 1 | - * | X | 0 | X | X | X | X | X | X || 1 | - * | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || 0 | - * +---+---+---+---+---+---+---+---++---+ - * - * Naming conventions follow National Semiconductor datasheet - */ - +//- Identifier: 5430/DM5430/DM7430 +//- Title: 8-Input NAND Gate +//- Description: This device contains a single gate which performs the logic NAND function. +//- Pinalias: A,B,C,D,E,F,GND,Y,NC,NC,G,H,NC,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006510.PDF +//- +//- +---+---+---+---+---+---+---+---++---+ +//- | A | B | C | D | E | F | G | H || Y | +//- +===+===+===+===+===+===+===+===++===+ +//- | X | X | X | X | X | X | X | 0 || 1 | +//- | X | X | X | X | X | X | 0 | X || 1 | +//- | X | X | X | X | X | 0 | X | X || 1 | +//- | X | X | X | X | 0 | X | X | X || 1 | +//- | X | X | X | 0 | X | X | X | X || 1 | +//- | X | X | 0 | X | X | X | X | X || 1 | +//- | X | 0 | X | X | X | X | X | X || 1 | +//- | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || 0 | +//- +---+---+---+---+---+---+---+---++---+ +//- static NETLIST_START(TTL_7430_DIP) TTL_7430_GATE(A) + NC_PIN(NC) - NC_PIN(NC9) - NC_PIN(NC10) - NC_PIN(NC13) - - DIPPINS( /* +--------------+ */ - A.A, /* A |1 ++ 14| VCC */ A.VCC, - A.B, /* B |2 13| NC */ NC13.I, - A.C, /* C |3 12| H */ A.H, - A.D, /* D |4 7430 11| G */ A.G, - A.E, /* E |5 10| NC */ NC10.I, - A.F, /* F |6 9| NC */ NC9.I, - A.GND,/* GND |7 8| Y */ A.Q - /* +--------------+ */ + DIPPINS( /* +--------------+ */ + A.A, /* A |1 ++ 14| VCC */ A.VCC, + A.B, /* B |2 13| NC */ NC.I, + A.C, /* C |3 12| H */ A.H, + A.D, /* D |4 7430 11| G */ A.G, + A.E, /* E |5 10| NC */ NC.I, + A.F, /* F |6 9| NC */ NC.I, + A.GND, /* GND |7 8| Y */ A.Q + /* +--------------+ */ ) NETLIST_END() -/* - * DM7432: Quad 2-Input OR Gates - * - * __ - * Y = A+B - * +---+---++---+ - * | A | B || Y | - * +===+===++===+ - * | 0 | 0 || 0 | - * | 0 | 1 || 1 | - * | 1 | 0 || 1 | - * | 1 | 1 || 1 | - * +---+---++---+ - * - * Naming conventions follow National Semiconductor datasheet - * - */ - +//- Identifier: 5432/DM5432/DM7432 +//- Title: Quad 2-Input OR Gates +//- Description: This device contains four independent gates each of whichperforms the logic OR function. +//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006511.PDF +//- +//- +---+---++---+ +//- | A | B || Y | +//- +===+===++===+ +//- | 0 | 0 || 0 | +//- | 0 | 1 || 1 | +//- | 1 | 0 || 1 | +//- | 1 | 1 || 1 | +//- +---+---++---+ +//- static NETLIST_START(TTL_7432_DIP) TTL_7432_GATE(A) TTL_7432_GATE(B) @@ -677,39 +675,37 @@ static NETLIST_START(TTL_7432_DIP) NET_C(A.VCC, B.VCC, C.VCC, D.VCC) NET_C(A.GND, B.GND, C.GND, D.GND) - DIPPINS( /* +--------------+ */ - A.A, /* A1 |1 ++ 14| VCC */ A.VCC, - A.B, /* B1 |2 13| B4 */ D.B, - A.Q, /* Y1 |3 12| A4 */ D.A, - B.A, /* A2 |4 7400 11| Y4 */ D.Q, - B.B, /* B2 |5 10| B3 */ C.B, - B.Q, /* Y2 |6 9| A3 */ C.A, - A.GND,/* GND |7 8| Y3 */ C.Q - /* +--------------+ */ + DIPPINS( /* +--------------+ */ + A.A, /* A1 |1 ++ 14| VCC */ A.VCC, + A.B, /* B1 |2 13| B4 */ D.B, + A.Q, /* Y1 |3 12| A4 */ D.A, + B.A, /* A2 |4 7432 11| Y4 */ D.Q, + B.B, /* B2 |5 10| B3 */ C.B, + B.Q, /* Y2 |6 9| A3 */ C.A, + A.GND, /* GND |7 8| Y3 */ C.Q + /* +--------------+ */ ) NETLIST_END() - -/* - * DM7437: Quad 2-Input NAND Gates - * - * _ - * Y = AB - * +---+---++---+ - * | A | B || Y | - * +===+===++===+ - * | 0 | 0 || 1 | - * | 0 | 1 || 1 | - * | 1 | 0 || 1 | - * | 1 | 1 || 0 | - * +---+---++---+ - * - * Naming conventions follow National Semiconductor datasheet - * - * NOTE: Same as 7400, but drains higher output currents. - * Netlist currently does not model over currents (should it ever?) - */ - +//- Identifier: 5437/DM5437/DM7437 +//- Title: Quad 2-Input NAND Buffers +//- Description: This device contains four independent gates each of whichperforms the logic OR function. +//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- Limitations: Same as 7400, but drains higher output currents. Netlist currently does not model over currents (should it ever?) +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheets/105/236976_DS.pdf +//- +//- +---+---++---+ +//- | A | B || Y | +//- +===+===++===+ +//- | 0 | 0 || 1 | +//- | 0 | 1 || 1 | +//- | 1 | 0 || 1 | +//- | 1 | 1 || 0 | +//- +---+---++---+ +//- static NETLIST_START(TTL_7437_DIP) TTL_7437_GATE(A) TTL_7437_GATE(B) @@ -719,32 +715,143 @@ static NETLIST_START(TTL_7437_DIP) NET_C(A.VCC, B.VCC, C.VCC, D.VCC) NET_C(A.GND, B.GND, C.GND, D.GND) - DIPPINS( /* +--------------+ */ - A.A, /* A1 |1 ++ 14| VCC */ A.VCC, - A.B, /* B1 |2 13| B4 */ D.B, - A.Q, /* Y1 |3 12| A4 */ D.A, - B.A, /* A2 |4 7400 11| Y4 */ D.Q, - B.B, /* B2 |5 10| B3 */ C.B, - B.Q, /* Y2 |6 9| A3 */ C.A, - A.GND,/* GND |7 8| Y3 */ C.Q - /* +--------------+ */ + DIPPINS( /* +--------------+ */ + A.A, /* A1 |1 ++ 14| VCC */ A.VCC, + A.B, /* B1 |2 13| B4 */ D.B, + A.Q, /* Y1 |3 12| A4 */ D.A, + B.A, /* A2 |4 7437 11| Y4 */ D.Q, + B.B, /* B2 |5 10| B3 */ C.B, + B.Q, /* Y2 |6 9| A3 */ C.A, + A.GND, /* GND |7 8| Y3 */ C.Q + /* +--------------+ */ ) NETLIST_END() -/* - * DM7450: DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES (ONE GATE EXPANDABLE) - * - * +--------------+ - * 1A |1 ++ 14| VCC - * 2A |2 13| 1B - * 2B |3 12| 1XQ - * 2C |4 7450 11| 1X - * 2D |5 10| 1D - * 2Y |6 9| 1C - * GND |7 8| 1Y - * +--------------+ -*/ +//- Identifier: 5442A/DM5442A/DM7442A +//- Title: BCD to Decimal Decoders +//- Description: These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. +//- The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. +//- Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions. +//- Pinalias: 0,1,2,3,4,5,6,GND,7,8,9,D,C,B,A,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006516.PDF +//- +//- +---+---+---+---++---+---+---+---+---+---+---+---+---+---+ +//- | D | C | B | A || 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | +//- +===+===+===+===++===+===+===+===+===+===+===+===+===+===+ +//- | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 0 | 0 | 0 | 1 || 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 0 | 0 | 1 | 0 || 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 0 | 0 | 1 | 1 || 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 0 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | +//- | 0 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | +//- | 0 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | +//- | 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | +//- | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +//- | 1 | 0 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +//- | 1 | 0 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | 0 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- +---+---+---+---++---+---+---+---+---+---+---+---+---+---+ +//- +static NETLIST_START(TTL_7442_DIP) + NET_REGISTER_DEV(TTL_7442, A) + + DIPPINS( /* +--------------+ */ + A.Q0, /* 0 |1 ++ 16| VCC */ A.VCC, + A.Q1, /* 1 |2 15| A */ A.A, + A.Q2, /* 2 |3 14| B */ A.B, + A.Q3, /* 3 |4 13| C */ A.C, + A.Q4, /* 4 |5 7442 12| D */ A.D, + A.Q5, /* 5 |6 11| 9 */ A.Q9, + A.Q6, /* 6 |7 10| 8 */ A.Q8, + A.GND, /* GND |8 9| 7 */ A.Q7 + /* +--------------+ */ + ) +NETLIST_END() + +//- Identifier: DM74LS48 +//- Title: BCD to 7-Segment Decoder +//- Description: The ’LS48 translates four lines of BCD (8421) input data into the 7-segment numeral code and provides seven corresponding outputs having pull-up resistors, as opposed to totem pole pull-ups. +//- These outputs can serve as logic signals, with a HIGH output corresponding to a lighted lamp segment, or can provide a 1.3 mA base current to npn lamp driver transistors. +//- Auxiliary inputs provide lamp test, blanking and cascadable zero-suppression functions. +//- The ’LS48 decodes the input data in the pattern indicated in the Truth Table and the segment identification illustration. +//- Pinalias: A1,A2,LTQ,BIQ,RBIQ,A3,A0,GND,e,d,c,b,a,g,f,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS010172.PDF +//- +//- +-----+------+----+----+----+----++-----+---+---+---+---+---+---+---+ +//- | LTQ | RBIQ | A3 | A2 | A1 | A0 || BIQ | a | b | c | d | e | f | g | +//- +=====+======+====+====+====+====++=====+===+===+===+===+===+===+===+ +//- | 1 | 1 | 0 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +//- | 1 | X | 0 | 0 | 0 | 1 || 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | +//- | 1 | X | 0 | 0 | 1 | 0 || 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | +//- | 1 | X | 0 | 0 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +//- | 1 | X | 0 | 1 | 0 | 0 || 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | +//- | 1 | X | 0 | 1 | 0 | 1 || 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | +//- | 1 | X | 0 | 1 | 1 | 0 || 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | X | 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +//- | 1 | X | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- | 1 | X | 1 | 0 | 0 | 1 || 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | +//- | 1 | X | 1 | 0 | 1 | 0 || 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | +//- | 1 | X | 1 | 0 | 1 | 1 || 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | +//- | 1 | X | 1 | 1 | 0 | 0 || 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | +//- | 1 | X | 1 | 1 | 0 | 1 || 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | +//- | 1 | X | 1 | 1 | 1 | 0 || 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | +//- | 1 | X | 1 | 1 | 1 | 1 || 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +//- | X | X | X | X | X | X || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +//- | 1 | 0 | 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +//- | 0 | X | X | X | X | X || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +//- +-----+------+----+----+----+----++-----+---+---+---+---+---+---+---+ +//- +static NETLIST_START(TTL_7448_DIP) + +#if (NL_USE_TRUTHTABLE_7448) + NET_REGISTER_DEV(TTL_7448_TT, A) +#else + NET_REGISTER_DEV(TTL_7448, A) +#endif + + DIPPINS( /* +--------------+ */ + A.B, /* B |1 ++ 16| VCC */ A.VCC, + A.C, /* C |2 15| f */ A.f, + A.LTQ, /* LTQ |3 14| g */ A.g, + A.BIQ, /* BIQ |4 7448 13| a */ A.a, + A.RBIQ, /* RBIQ |5 12| b */ A.b, + A.D, /* D |6 11| c */ A.c, + A.A, /* A |7 10| d */ A.d, + A.GND, /* GND |8 9| e */ A.e + /* +--------------+ */ + ) +NETLIST_END() +//- Identifier: DM7450 +//- Title: Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate +//- Description: This device contains two independent combinations of gates, each of which perform the logic AND-OR-INVERT function. +//- One set of gates has an expander node. +//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- Limitations: Expander signal is not implemented +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheets/105/236976_DS.pdf +//- +//- +---+---++---+ +//- | A | B || Y | +//- +===+===++===+ +//- | 0 | 0 || 1 | +//- | 0 | 1 || 1 | +//- | 1 | 0 || 1 | +//- | 1 | 1 || 0 | +//- +---+---++---+ +//- static NETLIST_START(TTL_7450_DIP) TTL_7450_ANDORINVERT(A) TTL_7450_ANDORINVERT(B) @@ -753,33 +860,45 @@ static NETLIST_START(TTL_7450_DIP) NET_C(A.GND, B.GND) NC_PIN(NC) - DIPPINS( /* +--------------+ */ - A.A, /* 1A |1 ++ 14| VCC */ A.VCC, - B.A, /* 2A |2 13| 1B */ A.B, - B.B, /* 2B |3 12| 1XQ */ NC.I, - B.C, /* 2C |4 7450 11| 1X */ NC.I, - B.D, /* 2D |5 10| 1D */ A.D, - B.Q, /* 2Y |6 9| 1C */ A.C, - A.GND,/* GND |7 8| 1Y */ A.Q - /* +--------------+ */ + DIPPINS( /* +--------------+ */ + A.A, /* 1A |1 ++ 14| VCC */ A.VCC, + B.A, /* 2A |2 13| 1B */ A.B, + B.B, /* 2B |3 12| 1XQ */ NC.I, + B.C, /* 2C |4 7450 11| 1X */ NC.I, + B.D, /* 2D |5 10| 1D */ A.D, + B.Q, /* 2Y |6 9| 1C */ A.C, + A.GND, /* GND |7 8| 1Y */ A.Q + /* +--------------+ */ ) NETLIST_END() -/* - * 7473: Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs - * 7473A: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs - * - * +----------+ - * 1CLK |1 ++ 14| 1J - * 1CLRQ |2 13| 1QQ - * 1K |3 12| 1Q - * VCC |4 7473 11| GND - * 2CLK |5 10| 2K - * 2CLRQ |6 9| 2Q - * 2J |7 8| 2QQ - * +----------+ - */ - +//- Identifier: 5473/DM5473/DM7473 +//- Title: Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs +//- Description: This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. +//- The J and K data is processed by the flip-flops after a complete clock pulse. +//- While the clock is low the slave is isolated from the master. +//- On the positive transition of the clock, the data from the J and K inputs is transferred to teh master. +//- While the clock is high the J and K inputs are disabled. +//- On the negative transition of the clock, the data from the master is transferred to the slave. +//- The logic states of the J and K inputs must not be allowed to change while the clock is high. +//- Data transfers to the outputs on the falling edge of the clock pulse. +//- A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs. +//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1 +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- http://pdf.datasheetcatalog.com/datasheet_pdf/national-semiconductor/5473DMQB_to_DM7473N.pdf +//- +//- +-----+-------+---+---++---+----+ +//- | CLR | CLK | J | K || Q | QQ | +//- +=====+=======+===+===++===+====+ +//- | 0 | X | X | X || 0 | 1 | +//- | 1 | 0-1-0 | 0 | 0 || Q | QQ | +//- | 1 | 0-1-0 | 1 | 0 || 1 | 0 | +//- | 1 | 0-1-0 | 0 | 1 || 0 | 1 | +//- | 1 | 0-1-0 | 1 | 1 || Toggle | +//- +-----+-------+---+---++---+----+ +//- static NETLIST_START(TTL_7473_DIP) TTL_7473(A) TTL_7473(B) @@ -787,18 +906,42 @@ static NETLIST_START(TTL_7473_DIP) NET_C(A.VCC, B.VCC) NET_C(A.GND, B.GND) - DIPPINS( /* +----------+ */ - A.CLK, /* 1CLK |1 ++ 14| 1J */ A.J, - A.CLRQ, /* 1CLRQ |2 13| 1QQ */ A.QQ, - A.K, /* 1K |3 12| 1Q */ A.Q, - A.VCC, /* VCC |4 7473 11| GND */ A.GND, - B.CLK, /* 2CLK |5 10| 2K */ B.K, - B.CLRQ, /* 2CLRQ |6 9| 2Q */ B.Q, - B.J, /* 2J |7 8| 2QQ */ B.QQ - /* +----------+ */ + DIPPINS( /* +--------------+ */ + A.CLK, /* CLK1 |1 ++ 14| J1 */ A.J, + A.CLRQ, /* CLR1 |2 13| QQ1 */ A.QQ, + A.K, /* K1 |3 12| Q1 */ A.Q, + A.VCC, /* VCC |4 7473 11| GND */ A.GND, + B.CLK, /* CLK2 |5 10| K2 */ B.K, + B.CLRQ, /* CLR2 |6 9| Q2 */ B.Q, + B.J, /* J2 |7 8| QQ2 */ B.QQ + /* +--------------+ */ ) NETLIST_END() +//- Identifier: DM54LS73A/DM74LS73A +//- Title: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs +//- Description: This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. +//- The J and K data is processed by the flip-flops on the falling edge of the clock pulse. +// The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. +//- The data on the J and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated. +//- A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs. +//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1 +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semicouductor datasheet +//- FunctionTable: +//- https://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006372.PDF +//- +//- +-----+-----+---+---++---+----+ +//- | CLR | CLK | J | K || Q | QQ | +//- +=====+=====+===+===++===+====+ +//- | 0 | X | X | X || 0 | 1 | +//- | 1 | 1-0 | 0 | 0 || Q | QQ | +//- | 1 | 1-0 | 1 | 0 || 1 | 0 | +//- | 1 | 1-0 | 0 | 1 || 0 | 1 | +//- | 1 | 1-0 | 1 | 1 || Toggle | +//- | 1 | 1 | X | X || Q | QQ | +//- +-----+-----+---+---++---+----+ +//- static NETLIST_START(TTL_7473A_DIP) TTL_7473A(A) TTL_7473A(B) @@ -806,33 +949,42 @@ static NETLIST_START(TTL_7473A_DIP) NET_C(A.VCC, B.VCC) NET_C(A.GND, B.GND) - DIPPINS( /* +----------+ */ - A.CLK, /* 1CLK |1 ++ 14| 1J */ A.J, - A.CLRQ, /* 1CLRQ |2 13| 1QQ */ A.QQ, - A.K, /* 1K |3 12| 1Q */ A.Q, - A.VCC, /* VCC |4 7473A 11| GND */ A.GND, - B.CLK, /* 2CLK |5 10| 2K */ B.K, - B.CLRQ, /* 2CLRQ |6 9| 2Q */ B.Q, - B.J, /* 2J |7 8| 2QQ */ B.QQ - /* +----------+ */ + DIPPINS( /* +--------------+ */ + A.CLK, /* CLK1 |1 ++ 14| J1 */ A.J, + A.CLRQ, /* CLR1 |2 13| QQ1 */ A.QQ, + A.K, /* K1 |3 12| Q1 */ A.Q, + A.VCC, /* VCC |4 7473A 11| GND */ A.GND, + B.CLK, /* CLK2 |5 10| K2 */ B.K, + B.CLRQ, /* CLR2 |6 9| Q2 */ B.Q, + B.J, /* J2 |7 8| QQ2 */ B.QQ + /* +--------------+ */ ) NETLIST_END() -/* - * DM7474: Dual Positive-Edge-Triggered D Flip-Flops - * with Preset, Clear and Complementary Outputs - * - * +--------------+ - * CLR1 |1 ++ 14| VCC - * D1 |2 13| CLR2 - * CLK1 |3 12| D2 - * PR1 |4 7474 11| CLK2 - * Q1 |5 10| PR2 - * Q1Q |6 9| Q2 - * GND |7 8| Q2Q - * +--------------+ - */ - +//- Identifier: 5474/DM5474/DM7474 +//- Title: Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs +//- Description: This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. +//- The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. +//- The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. +//- The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated. +//- A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. +//- Pinalias: CLR1,D1,CLK1,PR1,Q1,QQ1,GND,QQ2,Q2,PR2,CLK2,D2,CLR2,VCC +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- https://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006526.PDF +//- +//- +----+-----+-----+---++---+----+ +//- | PR | CLR | CLK | D || Q | QQ | +//- +====+=====+=====+===++===+====+ +//- | 0 | 1 | X | X || 1 | 0 | +//- | 1 | 0 | X | X || 0 | 1 | +//- | 0 | 0 | X | X || 1 | 1 | (unstable) +//- | 1 | 1 | 0-1 | 1 || 1 | 0 | +//- | 1 | 1 | 0-1 | 0 || 0 | 1 | +//- | 1 | 1 | 0 | X || Q | QQ | +//- +----+-----+-----+---++---+----+ +//- static NETLIST_START(TTL_7474_DIP) TTL_7474(A) TTL_7474(B) @@ -846,28 +998,32 @@ static NETLIST_START(TTL_7474_DIP) A.CLK, /* CLK1 |3 12| D2 */ B.D, A.PREQ, /* PR1 |4 7474 11| CLK2 */ B.CLK, A.Q, /* Q1 |5 10| PR2 */ B.PREQ, - A.QQ, /* Q1Q |6 9| Q2 */ B.Q, - A.GND, /* GND |7 8| Q2Q */ B.QQ + A.QQ, /* QQ1 |6 9| Q2 */ B.Q, + A.GND, /* GND |7 8| QQ2 */ B.QQ /* +-------------+ */ ) NETLIST_END() -/* - * 7475: 4-Bit Bistable Latches with Complementary Outputs - * 7477: 4-Bit Bistable Latches - * - * +----------+ +----------+ - * 1QQ |1 ++ 16| 1Q 1D |1 ++ 14| 1Q - * 1D |2 15| 2Q 2D |2 13| 2Q - * 2D |3 14| 2QQ 3C4C |3 12| 1C2C - * 3C4C |4 7475 13| 1C2C VCC |4 7477 11| GND - * VCC |5 12| GND 3D |5 10| NC - * 3D |6 11| 3QQ 4D |6 9| 3Q - * 4D |7 10| 3Q NC |7 8| 4Q - * 4QQ |8 9| 4Q +----------+ - * +----------+ - */ - +//- Identifier: SN54/74LS75 +//- Title: 4-bit D Latch +//- Description: The TTL/MSI SN54/74LS75 latch is used as temporary storage for binary information between processing units and input/output or indicator units. +//- Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. +//- When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. +//- The SN54/74LS75 features complementary Q and QQ output from a 4-bit latch and is available in the 16-pin packages. +//- Pinalias: QQ0,D0,D1,E23,VCC,D2,D3,QQ3,Q3,Q2,QQ2,GND,E01,QQ1,Q1,Q0 +//- Package: DIP +//- NamingConvention: Naming conventions follow Motorola datasheet +//- FunctionTable: +//- https://pdf.datasheetcatalog.com/datasheet/motorola/SN74LS77.pdf +//- +//- +---+---++---+----+ +//- | D | G || Q | QQ | +//- +===+===++===+====+ +//- | 0 | 1 || 0 | 1 | +//- | 1 | 1 || 1 | 0 | +//- | X | 0 || Q | QQ | +//- +---+---++---+----+ +//- static NETLIST_START(TTL_7475_DIP) TTL_7475_GATE(A) TTL_7475_GATE(B) @@ -880,19 +1036,39 @@ static NETLIST_START(TTL_7475_DIP) NET_C(A.CLK, B.CLK) NET_C(C.CLK, D.CLK) - DIPPINS( /* +----------+ */ - A.QQ, /* 1QQ |1 ++ 16| 1Q */ A.Q, - A.D, /* 1D |2 15| 2Q */ B.Q, - B.D, /* 2D |3 14| 2QQ */ B.QQ, - C.CLK, /* 3C4C |4 7475 13| 1C2C */ A.CLK, - A.VCC, /* VCC |5 12| GND */ A.GND, - C.D, /* 3D |6 11| 3QQ */ C.QQ, - D.D, /* 4D |7 10| 3Q */ C.Q, - D.QQ, /* 4QQ |8 9| 4Q */ D.Q - /* +----------+ */ + DIPPINS( /* +--------------+ */ + A.QQ, /* QQ0 |1 ++ 16| Q0 */ A.Q, + A.D, /* D0 |2 15| Q1 */ B.Q, + B.D, /* D1 |3 14| QQ1 */ B.QQ, + C.CLK, /* E23 |4 7475 13| E01 */ A.CLK, + A.VCC, /* VCC |5 12| GND */ A.GND, + C.D, /* D2 |6 11| QQ2 */ C.QQ, + D.D, /* D3 |7 10| Q2 */ C.Q, + D.QQ, /* QQ3 |8 9| Q3 */ D.Q + /* +--------------+ */ ) NETLIST_END() +//- Identifier: SN54/74LS77 +//- Title: 4-bit D Latch +//- Description: The TTL/MSI SN54/74LS77 latch is used as temporary storage for binary information between processing units and input/output or indicator units. +//- Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. +//- When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. +//- For higher component density applications the SN54/74LS77 4-bit latch is available in the 14-pin package with QQ outputs omitted. +//- Pinalias: D0,D1,E23,VCC,D2,D3,NC,Q3,Q2,NC,GND,E01,Q1,Q0 +//- Package: DIP +//- NamingConvention: Naming conventions follow Motorola datasheet +//- FunctionTable: +//- https://pdf.datasheetcatalog.com/datasheet/motorola/SN74LS77.pdf +//- +//- +---+---++---+----+ +//- | D | G || Q | QQ | +//- +===+===++===+====+ +//- | 0 | 1 || 0 | 1 | +//- | 1 | 1 || 1 | 0 | +//- | X | 0 || Q | QQ | +//- +---+---++---+----+ +//- static NETLIST_START(TTL_7477_DIP) TTL_7477_GATE(A) TTL_7477_GATE(B) @@ -907,33 +1083,31 @@ static NETLIST_START(TTL_7477_DIP) NC_PIN(NC) - DIPPINS( /* +----------+ */ - A.D, /* 1D |1 ++ 14| 1Q */ A.Q, - B.D, /* 2D |2 13| 2Q */ B.Q, - C.CLK, /* 3C4C |3 12| 1C2C */ A.CLK, - A.VCC, /* VCC |4 7477 11| GND */ A.GND, - C.D, /* 3D |5 10| NC */ NC.I, - D.D, /* 4D |6 9| 3Q */ C.Q, - NC.I, /* NC |7 8| 4Q */ D.Q - /* +----------+ */ + DIPPINS( /* +--------------+ */ + A.D, /* D0 |1 ++ 14| Q0 */ A.Q, + B.D, /* D1 |2 13| Q1 */ B.Q, + C.CLK, /* E23 |3 12| E01 */ A.CLK, + A.VCC, /* VCC |4 7477 11| GND */ A.GND, + C.D, /* D2 |5 10| NC */ NC.I, + D.D, /* D3 |6 9| Q2 */ C.Q, + NC.I, /* NC |7 8| Q3 */ D.Q + /* +--------------+ */ ) NETLIST_END() -/* - * DM7483: 4-Bit Binary Adder with Fast Carry - * - * +--------------+ - * A4 |1 ++ 16| B4 - * S3 |2 15| S4 - * A3 |3 14| C4 - * B3 |4 7483 13| C0 - * VCC |5 12| GND - * S2 |6 11| B1 - * B2 |7 10| A1 - * A2 |8 9| S1 - * +--------------+ - */ - +//- Identifier: 54LS83A/DM54LS83A/DM74LS83A +//- Title: 4-bit Binary Adders With Fast Carry +//- Description: These full adders perform the addition of two 4-bit binary numbers. +//- The sum (S) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. +//- These adders feature full internal look ahead across all four bits. +//- This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation. +//- The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. +//- Pinalias: A4,S3,A3,B3,VCC,S2,B2,A2,S1,A1,B1,GND,C0,C4,S4,B4 +//- Package: DIP +//- NamingConvention: Naming conventions follow National Semiconductor datasheet +//- FunctionTable: +//- https://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006378.PDF +//- static NETLIST_START(TTL_7483_DIP) TTL_7483(A) @@ -950,56 +1124,55 @@ static NETLIST_START(TTL_7483_DIP) ) NETLIST_END() -/* - * DM7485: 4-bit Magnitude Comparators - * - * +------------+ - * B3 |1 ++ 16| VCC - * LTIN |2 15| A3 - * EQIN |3 14| B2 - * GTIN |4 7485 13| A2 - * GTOUT |5 12| A1 - * EQOUT |6 11| B1 - * LTOUT |7 10| A0 - * GND |8 9| B0 - * +------------+ - * - * Naming convention attempts to follow Texas Instruments datasheet - */ - +//- Identifier: 54LS85/DM54LS85/DM74LS85 +//- Title: 4-Bit Magnitude Comparators +//- Description: These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. +//- Three fully-decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. +//- These devices are fully expandable to any number of bits without external gates. +//- Words ofgreater length may be compared by connecting comparators in cascade. +//- The A>B, A