From 2b37fd59cdd7376eb6e40174222e85d1030e24c2 Mon Sep 17 00:00:00 2001 From: hap Date: Sat, 16 Nov 2024 15:32:39 +0100 Subject: docastle: do main-sub comms a bit differently (defer_access on subcpu was eating cycles), re-add logging --- src/mame/universal/docastle.cpp | 17 +++++------- src/mame/universal/docastle.h | 11 ++++---- src/mame/universal/docastle_m.cpp | 57 +++++++++++++++++++++------------------ 3 files changed, 43 insertions(+), 42 deletions(-) diff --git a/src/mame/universal/docastle.cpp b/src/mame/universal/docastle.cpp index 2f1b6faee54..3352816bbd8 100644 --- a/src/mame/universal/docastle.cpp +++ b/src/mame/universal/docastle.cpp @@ -234,7 +234,7 @@ void docastle_state::docastle_map(address_map &map) map(0x0000, 0x7fff).rom(); map(0x8000, 0x97ff).ram(); map(0x9800, 0x99ff).ram().share("spriteram"); - map(0xa000, 0xa000).mirror(0x07ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); + map(0xa000, 0xa7ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); map(0xa800, 0xa800).w("watchdog", FUNC(watchdog_timer_device::reset_w)); map(0xb000, 0xb3ff).mirror(0x0800).ram().w(FUNC(docastle_state::videoram_w)).share("videoram"); map(0xb400, 0xb7ff).mirror(0x0800).ram().w(FUNC(docastle_state::colorram_w)).share("colorram"); @@ -245,7 +245,7 @@ void docastle_state::docastle_map2(address_map &map) { map(0x0000, 0x3fff).rom(); map(0x8000, 0x87ff).ram(); - map(0xa000, 0xa000).mirror(0x07ff).rw(FUNC(docastle_state::sub_from_main_r), FUNC(docastle_state::sub_to_main_w)); + map(0xa000, 0xa7ff).rw(FUNC(docastle_state::sub_from_main_r), FUNC(docastle_state::sub_to_main_w)); map(0xc000, 0xc007).select(0x0080).rw(FUNC(docastle_state::inputs_flipscreen_r), FUNC(docastle_state::flipscreen_w)); map(0xe000, 0xe000).w(m_sn[0], FUNC(sn76489a_device::write)); map(0xe400, 0xe400).w(m_sn[1], FUNC(sn76489a_device::write)); @@ -275,7 +275,7 @@ void docastle_state::dorunrun_map(address_map &map) map(0x2000, 0x37ff).ram(); map(0x3800, 0x39ff).ram().share("spriteram"); map(0x4000, 0x9fff).rom(); - map(0xa000, 0xa000).mirror(0x07ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); + map(0xa000, 0xa7ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); map(0xa800, 0xa800).w("watchdog", FUNC(watchdog_timer_device::reset_w)); map(0xb000, 0xb3ff).ram().w(FUNC(docastle_state::videoram_w)).share("videoram"); map(0xb400, 0xb7ff).ram().w(FUNC(docastle_state::colorram_w)).share("colorram"); @@ -291,7 +291,7 @@ void docastle_state::dorunrun_map2(address_map &map) map(0xa800, 0xa800).w(m_sn[2], FUNC(sn76489a_device::write)); map(0xac00, 0xac00).w(m_sn[3], FUNC(sn76489a_device::write)); map(0xc000, 0xc007).select(0x0080).rw(FUNC(docastle_state::inputs_flipscreen_r), FUNC(docastle_state::flipscreen_w)); - map(0xe000, 0xe000).mirror(0x07ff).rw(FUNC(docastle_state::sub_from_main_r), FUNC(docastle_state::sub_to_main_w)); + map(0xe000, 0xe7ff).rw(FUNC(docastle_state::sub_from_main_r), FUNC(docastle_state::sub_to_main_w)); } @@ -301,7 +301,7 @@ void docastle_state::idsoccer_map(address_map &map) map(0x4000, 0x57ff).ram(); map(0x5800, 0x59ff).ram().share("spriteram"); map(0x6000, 0x9fff).rom(); - map(0xa000, 0xa000).mirror(0x07ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); + map(0xa000, 0xa7ff).rw(FUNC(docastle_state::main_from_sub_r), FUNC(docastle_state::main_to_sub_w)); map(0xa800, 0xa800).w("watchdog", FUNC(watchdog_timer_device::reset_w)); map(0xb000, 0xb3ff).mirror(0x0800).ram().w(FUNC(docastle_state::videoram_w)).share("videoram"); map(0xb400, 0xb7ff).mirror(0x0800).ram().w(FUNC(docastle_state::colorram_w)).share("colorram"); @@ -542,9 +542,7 @@ void docastle_state::machine_reset() m_adpcm_pos = m_adpcm_idle = 0; m_adpcm_data = -1; m_adpcm_status = 0; - - m_maincpu_defer_access = false; - m_subcpu_defer_access = false; + m_maincpu_wait = false; for (int i = 0; i < 2; i++) { @@ -564,8 +562,7 @@ void docastle_state::machine_start() save_item(NAME(m_adpcm_status)); save_item(NAME(m_shared_latch)); - save_item(NAME(m_maincpu_defer_access)); - save_item(NAME(m_subcpu_defer_access)); + save_item(NAME(m_maincpu_wait)); } void docastle_state::docastle(machine_config &config) diff --git a/src/mame/universal/docastle.h b/src/mame/universal/docastle.h index e2a0ce43fe9..77c42eed821 100644 --- a/src/mame/universal/docastle.h +++ b/src/mame/universal/docastle.h @@ -72,15 +72,14 @@ private: int m_adpcm_status = 0; uint8_t m_shared_latch = 0; - bool m_maincpu_defer_access = false; - bool m_subcpu_defer_access = false; + bool m_maincpu_wait = false; tilemap_t *m_do_tilemap = nullptr; - uint8_t main_from_sub_r(); - void main_to_sub_w(uint8_t data); - uint8_t sub_from_main_r(); - void sub_to_main_w(uint8_t data); + uint8_t main_from_sub_r(offs_t offset); + void main_to_sub_w(offs_t offset, uint8_t data); + uint8_t sub_from_main_r(offs_t offset); + void sub_to_main_w(offs_t offset, uint8_t data); void subcpu_nmi_w(uint8_t data); void videoram_w(offs_t offset, uint8_t data); void colorram_w(offs_t offset, uint8_t data); diff --git a/src/mame/universal/docastle_m.cpp b/src/mame/universal/docastle_m.cpp index 238c35ac7c2..3152ab997a6 100644 --- a/src/mame/universal/docastle_m.cpp +++ b/src/mame/universal/docastle_m.cpp @@ -11,6 +11,11 @@ #include "cpu/z80/z80.h" #include "docastle.h" +#define LOG_MAINSUB (1U << 1) + +#define VERBOSE (0) +#include "logmacro.h" + /* Communication between the two CPUs happens through a single bidirectional latch. @@ -23,68 +28,68 @@ timing needs to be cycle-accurate, both CPUs do LDIR opcodes in lockstep. */ -uint8_t docastle_state::main_from_sub_r() +uint8_t docastle_state::main_from_sub_r(offs_t offset) { if (!machine().side_effects_disabled()) { - m_maincpu_defer_access = !m_maincpu_defer_access; + m_maincpu_wait = !m_maincpu_wait; - if (m_maincpu_defer_access) + if (m_maincpu_wait) { + // steal 1 cycle ahead of WAIT to avoid race condition + m_maincpu->adjust_icount(-1); + machine().scheduler().perfect_quantum(attotime::from_usec(100)); m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, ASSERT_LINE); // defer access to let subcpu write the latch and clear WAIT m_maincpu->defer_access(); } + else + { + LOGMASKED(LOG_MAINSUB, "%dR%02X%c", offset, m_shared_latch, (offset == 8) ? '\n' : ' '); + + // give back stolen cycle + m_maincpu->adjust_icount(1); + } } return m_shared_latch; } -void docastle_state::main_to_sub_w(uint8_t data) +void docastle_state::main_to_sub_w(offs_t offset, uint8_t data) { + LOGMASKED(LOG_MAINSUB, "%dW%02X ", offset, data); + m_shared_latch = data; machine().scheduler().perfect_quantum(attotime::from_usec(100)); m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, ASSERT_LINE); } -uint8_t docastle_state::sub_from_main_r() +uint8_t docastle_state::sub_from_main_r(offs_t offset) { if (!machine().side_effects_disabled()) { - m_subcpu_defer_access = !m_subcpu_defer_access; - - if (m_subcpu_defer_access) - { - // defer access to let maincpu react first - m_subcpu->defer_access(); - } - else - m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, CLEAR_LINE); + LOGMASKED(LOG_MAINSUB, "%dr%02X%c", offset, m_shared_latch, (offset == 8) ? '\n' : ' '); + m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, CLEAR_LINE); } return m_shared_latch; } -void docastle_state::sub_to_main_w(uint8_t data) +void docastle_state::sub_to_main_w(offs_t offset, uint8_t data) { - m_subcpu_defer_access = !m_subcpu_defer_access; + LOGMASKED(LOG_MAINSUB, "%dw%02X ", offset, data); - if (m_subcpu_defer_access) - { - // defer access to let maincpu react first - m_subcpu->defer_access(); - } - else - { - m_shared_latch = data; - m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, CLEAR_LINE); - } + m_shared_latch = data; + m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, CLEAR_LINE); } void docastle_state::subcpu_nmi_w(uint8_t data) { + LOGMASKED(LOG_MAINSUB, "%s trigger subcpu NMI\n", machine().describe_context()); + + machine().scheduler().perfect_quantum(attotime::from_usec(100)); m_subcpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); } -- cgit v1.2.3