From 2a342ec7c9843debc6e8bf6955a94c09a6bf495f Mon Sep 17 00:00:00 2001 From: Vas Crabb Date: Tue, 11 Aug 2020 16:57:47 +1000 Subject: cpu/nec: use anonymous namespaces to avoid ODR violations with enums --- scripts/src/cpu.lua | 4 +- src/devices/cpu/nec/nec.cpp | 3 +- src/devices/cpu/nec/necpriv.h | 130 --------------------------- src/devices/cpu/nec/necpriv.ipp | 135 ++++++++++++++++++++++++++++ src/devices/cpu/nec/v25.cpp | 8 +- src/devices/cpu/nec/v25priv.h | 188 -------------------------------------- src/devices/cpu/nec/v25priv.ipp | 193 ++++++++++++++++++++++++++++++++++++++++ src/devices/cpu/nec/v25sfr.cpp | 2 +- src/devices/cpu/nec/v5x.cpp | 2 +- 9 files changed, 339 insertions(+), 326 deletions(-) delete mode 100644 src/devices/cpu/nec/necpriv.h create mode 100644 src/devices/cpu/nec/necpriv.ipp delete mode 100644 src/devices/cpu/nec/v25priv.h create mode 100644 src/devices/cpu/nec/v25priv.ipp diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index e2ed4badf4a..64814fd67d7 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -1883,10 +1883,10 @@ if (CPUS["NEC"]~=null) then MAME_DIR .. "src/devices/cpu/nec/nec80inst.hxx", MAME_DIR .. "src/devices/cpu/nec/necmacro.h", MAME_DIR .. "src/devices/cpu/nec/necmodrm.h", - MAME_DIR .. "src/devices/cpu/nec/necpriv.h", + MAME_DIR .. "src/devices/cpu/nec/necpriv.ipp", MAME_DIR .. "src/devices/cpu/nec/v25instr.h", MAME_DIR .. "src/devices/cpu/nec/v25instr.hxx", - MAME_DIR .. "src/devices/cpu/nec/v25priv.h", + MAME_DIR .. "src/devices/cpu/nec/v25priv.ipp", MAME_DIR .. "src/devices/cpu/nec/v25.cpp", MAME_DIR .. "src/devices/cpu/nec/v25.h", MAME_DIR .. "src/devices/cpu/nec/v25sfr.cpp", diff --git a/src/devices/cpu/nec/nec.cpp b/src/devices/cpu/nec/nec.cpp index 2a9546977c2..b46910bc4d9 100644 --- a/src/devices/cpu/nec/nec.cpp +++ b/src/devices/cpu/nec/nec.cpp @@ -107,6 +107,7 @@ #include "emu.h" #include "nec.h" #include "necdasm.h" + #include "debugger.h" typedef uint8_t BOOLEAN; @@ -114,7 +115,7 @@ typedef uint8_t BYTE; typedef uint16_t WORD; typedef uint32_t DWORD; -#include "necpriv.h" +#include "necpriv.ipp" DEFINE_DEVICE_TYPE(V20, v20_device, "v20", "NEC V20") DEFINE_DEVICE_TYPE(V30, v30_device, "v30", "NEC V30") diff --git a/src/devices/cpu/nec/necpriv.h b/src/devices/cpu/nec/necpriv.h deleted file mode 100644 index 474a95382dc..00000000000 --- a/src/devices/cpu/nec/necpriv.h +++ /dev/null @@ -1,130 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Bryan McPhail -/* Cpu types, steps of 8 to help the cycle count calculation */ -#define V33_TYPE 0 -#define V30_TYPE 8 -#define V20_TYPE 16 - -/* interrupt vectors */ -enum -{ - NEC_DIVIDE_VECTOR = 0, - NEC_TRAP_VECTOR = 1, - NEC_NMI_VECTOR = 2, - NEC_BRKV_VECTOR = 4, - NEC_CHKIND_VECTOR = 5 -}; - -/* interrupt sources */ -enum INTSOURCES -{ - BRK = 0, - INT_IRQ = 1, - NMI_IRQ = 2 -}; - - -enum SREGS { DS1=0, PS, SS, DS0 }; -enum WREGS { AW=0, CW, DW, BW, SP, BP, IX, IY }; -enum BREGS { - AL = NATIVE_ENDIAN_VALUE_LE_BE(0x0, 0x1), - AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1, 0x0), - CL = NATIVE_ENDIAN_VALUE_LE_BE(0x2, 0x3), - CH = NATIVE_ENDIAN_VALUE_LE_BE(0x3, 0x2), - DL = NATIVE_ENDIAN_VALUE_LE_BE(0x4, 0x5), - DH = NATIVE_ENDIAN_VALUE_LE_BE(0x5, 0x4), - BL = NATIVE_ENDIAN_VALUE_LE_BE(0x6, 0x7), - BH = NATIVE_ENDIAN_VALUE_LE_BE(0x7, 0x6) -}; - -#define Sreg(x) m_sregs[x] -#define Wreg(x) m_regs.w[x] -#define Breg(x) m_regs.b[x] - -#define PC() ((Sreg(PS)<<4)+m_ip) - -#define CF (m_CarryVal!=0) -#define SF (m_SignVal<0) -#define ZF (m_ZeroVal==0) -#define PF parity_table[(BYTE)m_ParityVal] -#define AF (m_AuxVal!=0) -#define OF (m_OverVal!=0) - -/************************************************************************/ - -#define read_mem_byte(a) m_program->read_byte(m_chip_type == V33_TYPE ? v33_translate(a) : (a)) -#define read_mem_word(a) m_program->read_word_unaligned(m_chip_type == V33_TYPE ? v33_translate(a) : (a)) -#define write_mem_byte(a,d) m_program->write_byte(m_chip_type == V33_TYPE ? v33_translate(a) : (a), (d)) -#define write_mem_word(a,d) m_program->write_word_unaligned(m_chip_type == V33_TYPE ? v33_translate(a) : (a), (d)) - -#define read_port_byte(a) io_read_byte(a) -#define read_port_word(a) io_read_word(a) -#define write_port_byte(a,d) io_write_byte((a),(d)) -#define write_port_word(a,d) io_write_word((a),(d)) - -/************************************************************************/ - -#define CHANGE_PC do { EMPTY_PREfetch(); } while (0) - -#define SegBase(Seg) (Sreg(Seg) << 4) - -#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4) - -#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off))) -#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off))) - -#define PutMemB(Seg,Off,x) { write_mem_byte(DefaultBase(Seg) + (Off), (x)); } -#define PutMemW(Seg,Off,x) { write_mem_word(DefaultBase(Seg) + (Off), (x)); } - -/* prefetch timing */ - -#define EMPTY_PREfetch() m_prefetch_reset = 1 - - -#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); } -#define POP(var) { Wreg(SP) += 2; var = read_mem_word(((Sreg(SS)<<4) + ((Wreg(SP)-2) & 0xffff))); } - -#define PUSH80(val) { Wreg(BP) -= 2; write_mem_word(((Sreg(DS0)<<4)+Wreg(BP)), val); } -#define POP80(var) { Wreg(BP) += 2; var = read_mem_word(((Sreg(DS0)<<4) + ((Wreg(BP)-2) & 0xffff))); } - -#define BRKXA(xa) { if (m_chip_type == V33_TYPE) { nec_brk(fetch()); m_xa = xa; } else logerror("%06x: %sXA instruction is V33 exclusive\n", PC(), xa ? "BRK" : "RET"); } -#define BRKEM { if (m_chip_type == V33_TYPE) logerror("%06x: BRKEM not supported on V33\n",PC()); else nec_brk(fetch()); } - -#define GetModRM uint32_t ModRM=fetch() - -/* Cycle count macros: - CLK - cycle count is the same on all processors - CLKS - cycle count differs between processors, list all counts - CLKW - cycle count for word read/write differs for odd/even source/destination address - CLKM - cycle count for reg/mem instructions - CLKR - cycle count for reg/mem instructions with different counts for odd/even addresses - - - Prefetch & buswait time is not emulated. - Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated. -*/ - -#define CLK(all) m_icount-=all -#define CLKS(v20,v30,v33) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; } -#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } -#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); } -#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } - -/************************************************************************/ -#define CompressFlags() (WORD)(int(CF) | 0x02 | (int(PF) << 2) | (int(AF) << 4) | (int(ZF) << 6) \ - | (int(SF) << 7) | (m_TF << 8) | (m_IF << 9) \ - | (m_DF << 10) | (int(OF) << 11) | 0x7000 | (m_MF << 15)) - -#define ExpandFlags(f) \ -{ \ - m_CarryVal = (f) & 0x0001; \ - m_ParityVal = !((f) & 0x0004); \ - m_AuxVal = (f) & 0x0010; \ - m_ZeroVal = !((f) & 0x0040); \ - m_SignVal = (f) & 0x0080 ? -1 : 0; \ - m_TF = ((f) & 0x0100) == 0x0100; \ - m_IF = ((f) & 0x0200) == 0x0200; \ - m_DF = ((f) & 0x0400) == 0x0400; \ - m_OverVal = (f) & 0x0800; \ - m_MF = (((f) & 0x8000) == 0x8000) || m_em; \ -} diff --git a/src/devices/cpu/nec/necpriv.ipp b/src/devices/cpu/nec/necpriv.ipp new file mode 100644 index 00000000000..d2b8bc5c4af --- /dev/null +++ b/src/devices/cpu/nec/necpriv.ipp @@ -0,0 +1,135 @@ +// license:BSD-3-Clause +// copyright-holders:Bryan McPhail + +namespace { + +/* Cpu types, steps of 8 to help the cycle count calculation */ +#define V33_TYPE 0 +#define V30_TYPE 8 +#define V20_TYPE 16 + +/* interrupt vectors */ +enum +{ + NEC_DIVIDE_VECTOR = 0, + NEC_TRAP_VECTOR = 1, + NEC_NMI_VECTOR = 2, + NEC_BRKV_VECTOR = 4, + NEC_CHKIND_VECTOR = 5 +}; + +/* interrupt sources */ +enum INTSOURCES +{ + BRK = 0, + INT_IRQ = 1, + NMI_IRQ = 2 +}; + + +enum SREGS { DS1=0, PS, SS, DS0 }; +enum WREGS { AW=0, CW, DW, BW, SP, BP, IX, IY }; +enum BREGS { + AL = NATIVE_ENDIAN_VALUE_LE_BE(0x0, 0x1), + AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1, 0x0), + CL = NATIVE_ENDIAN_VALUE_LE_BE(0x2, 0x3), + CH = NATIVE_ENDIAN_VALUE_LE_BE(0x3, 0x2), + DL = NATIVE_ENDIAN_VALUE_LE_BE(0x4, 0x5), + DH = NATIVE_ENDIAN_VALUE_LE_BE(0x5, 0x4), + BL = NATIVE_ENDIAN_VALUE_LE_BE(0x6, 0x7), + BH = NATIVE_ENDIAN_VALUE_LE_BE(0x7, 0x6) +}; + +#define Sreg(x) m_sregs[x] +#define Wreg(x) m_regs.w[x] +#define Breg(x) m_regs.b[x] + +#define PC() ((Sreg(PS)<<4)+m_ip) + +#define CF (m_CarryVal!=0) +#define SF (m_SignVal<0) +#define ZF (m_ZeroVal==0) +#define PF parity_table[(BYTE)m_ParityVal] +#define AF (m_AuxVal!=0) +#define OF (m_OverVal!=0) + +/************************************************************************/ + +#define read_mem_byte(a) m_program->read_byte(m_chip_type == V33_TYPE ? v33_translate(a) : (a)) +#define read_mem_word(a) m_program->read_word_unaligned(m_chip_type == V33_TYPE ? v33_translate(a) : (a)) +#define write_mem_byte(a,d) m_program->write_byte(m_chip_type == V33_TYPE ? v33_translate(a) : (a), (d)) +#define write_mem_word(a,d) m_program->write_word_unaligned(m_chip_type == V33_TYPE ? v33_translate(a) : (a), (d)) + +#define read_port_byte(a) io_read_byte(a) +#define read_port_word(a) io_read_word(a) +#define write_port_byte(a,d) io_write_byte((a),(d)) +#define write_port_word(a,d) io_write_word((a),(d)) + +/************************************************************************/ + +#define CHANGE_PC do { EMPTY_PREfetch(); } while (0) + +#define SegBase(Seg) (Sreg(Seg) << 4) + +#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4) + +#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off))) +#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off))) + +#define PutMemB(Seg,Off,x) { write_mem_byte(DefaultBase(Seg) + (Off), (x)); } +#define PutMemW(Seg,Off,x) { write_mem_word(DefaultBase(Seg) + (Off), (x)); } + +/* prefetch timing */ + +#define EMPTY_PREfetch() m_prefetch_reset = 1 + + +#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); } +#define POP(var) { Wreg(SP) += 2; var = read_mem_word(((Sreg(SS)<<4) + ((Wreg(SP)-2) & 0xffff))); } + +#define PUSH80(val) { Wreg(BP) -= 2; write_mem_word(((Sreg(DS0)<<4)+Wreg(BP)), val); } +#define POP80(var) { Wreg(BP) += 2; var = read_mem_word(((Sreg(DS0)<<4) + ((Wreg(BP)-2) & 0xffff))); } + +#define BRKXA(xa) { if (m_chip_type == V33_TYPE) { nec_brk(fetch()); m_xa = xa; } else logerror("%06x: %sXA instruction is V33 exclusive\n", PC(), xa ? "BRK" : "RET"); } +#define BRKEM { if (m_chip_type == V33_TYPE) logerror("%06x: BRKEM not supported on V33\n",PC()); else nec_brk(fetch()); } + +#define GetModRM uint32_t ModRM=fetch() + +/* Cycle count macros: + CLK - cycle count is the same on all processors + CLKS - cycle count differs between processors, list all counts + CLKW - cycle count for word read/write differs for odd/even source/destination address + CLKM - cycle count for reg/mem instructions + CLKR - cycle count for reg/mem instructions with different counts for odd/even addresses + + + Prefetch & buswait time is not emulated. + Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated. +*/ + +#define CLK(all) m_icount-=all +#define CLKS(v20,v30,v33) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; } +#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } +#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); } +#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } + +/************************************************************************/ +#define CompressFlags() (WORD)(int(CF) | 0x02 | (int(PF) << 2) | (int(AF) << 4) | (int(ZF) << 6) \ + | (int(SF) << 7) | (m_TF << 8) | (m_IF << 9) \ + | (m_DF << 10) | (int(OF) << 11) | 0x7000 | (m_MF << 15)) + +#define ExpandFlags(f) \ +{ \ + m_CarryVal = (f) & 0x0001; \ + m_ParityVal = !((f) & 0x0004); \ + m_AuxVal = (f) & 0x0010; \ + m_ZeroVal = !((f) & 0x0040); \ + m_SignVal = (f) & 0x0080 ? -1 : 0; \ + m_TF = ((f) & 0x0100) == 0x0100; \ + m_IF = ((f) & 0x0200) == 0x0200; \ + m_DF = ((f) & 0x0400) == 0x0400; \ + m_OverVal = (f) & 0x0800; \ + m_MF = (((f) & 0x8000) == 0x8000) || m_em; \ +} + +} // anonymous namespace diff --git a/src/devices/cpu/nec/v25.cpp b/src/devices/cpu/nec/v25.cpp index f4785ba9af0..8a44732d07d 100644 --- a/src/devices/cpu/nec/v25.cpp +++ b/src/devices/cpu/nec/v25.cpp @@ -35,6 +35,9 @@ ****************************************************************************/ #include "emu.h" +#include "v25.h" +#include "necdasm.h" + #include "debugger.h" typedef uint8_t BOOLEAN; @@ -42,9 +45,8 @@ typedef uint8_t BYTE; typedef uint16_t WORD; typedef uint32_t DWORD; -#include "v25.h" -#include "v25priv.h" -#include "necdasm.h" +#include "v25priv.ipp" + DEFINE_DEVICE_TYPE(V25, v25_device, "v25", "NEC V25") DEFINE_DEVICE_TYPE(V35, v35_device, "v35", "NEC V35") diff --git a/src/devices/cpu/nec/v25priv.h b/src/devices/cpu/nec/v25priv.h deleted file mode 100644 index e212314d1d9..00000000000 --- a/src/devices/cpu/nec/v25priv.h +++ /dev/null @@ -1,188 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Bryan McPhail, Alex W. Jackson -/* Cpu types, steps of 8 to help the cycle count calculation */ -#define V33_TYPE 0 -#define V30_TYPE 8 -#define V20_TYPE 16 - -/* interrupt vectors */ -enum -{ - NEC_DIVIDE_VECTOR = 0, - NEC_TRAP_VECTOR = 1, - NEC_NMI_VECTOR = 2, - NEC_BRKV_VECTOR = 4, - NEC_CHKIND_VECTOR = 5, - NEC_IBRK_VECTOR = 19, - NEC_INTTU0_VECTOR = 28, - NEC_INTTU1_VECTOR = 29, - NEC_INTTU2_VECTOR = 30, - NEC_INTD0_VECTOR = 20, - NEC_INTD1_VECTOR = 21, - NEC_INTP0_VECTOR = 24, - NEC_INTP1_VECTOR = 25, - NEC_INTP2_VECTOR = 26, - NEC_INTSER0_VECTOR = 12, - NEC_INTSR0_VECTOR = 13, - NEC_INTST0_VECTOR = 14, - NEC_INTSER1_VECTOR = 16, - NEC_INTSR1_VECTOR = 17, - NEC_INTST1_VECTOR = 18, - NEC_INTTB_VECTOR = 31 -}; - -/* interrupt sources */ -enum INTSOURCES -{ - BRK = 0, - INT_IRQ = 1, - NMI_IRQ = 1 << 1, - INTTU0 = 1 << 2, - INTTU1 = 1 << 3, - INTTU2 = 1 << 4, - INTD0 = 1 << 5, - INTD1 = 1 << 6, - INTP0 = 1 << 7, - INTP1 = 1 << 8, - INTP2 = 1 << 9, - INTSER0 = 1 << 10, - INTSR0 = 1 << 11, - INTST0 = 1 << 12, - INTSER1 = 1 << 13, - INTSR1 = 1 << 14, - INTST1 = 1 << 15, - INTTB = 1 << 16, - BRKN = 1 << 17, - BRKS = 1 << 18 -}; - -enum { - VECTOR_PC = 0x02/2, - PSW_SAVE = 0x04/2, - PC_SAVE = 0x06/2 -}; - -enum SREGS { - DS1 = 0x0E/2, - PS = 0x0C/2, - SS = 0x0A/2, - DS0 = 0x08/2 -}; - -enum WREGS { - AW = 0x1E/2, - CW = 0x1C/2, - DW = 0x1A/2, - BW = 0x18/2, - SP = 0x16/2, - BP = 0x14/2, - IX = 0x12/2, - IY = 0x10/2 -}; - -enum BREGS { - AL = NATIVE_ENDIAN_VALUE_LE_BE(0x1E, 0x1F), - AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1F, 0x1E), - CL = NATIVE_ENDIAN_VALUE_LE_BE(0x1C, 0x1D), - CH = NATIVE_ENDIAN_VALUE_LE_BE(0x1D, 0x1C), - DL = NATIVE_ENDIAN_VALUE_LE_BE(0x1A, 0x1B), - DH = NATIVE_ENDIAN_VALUE_LE_BE(0x1B, 0x1A), - BL = NATIVE_ENDIAN_VALUE_LE_BE(0x18, 0x19), - BH = NATIVE_ENDIAN_VALUE_LE_BE(0x19, 0x18) -}; - -#define SetRB(x) do { m_RBW = (x) << 4; m_RBB = (x) << 5; } while (0) - -#define Sreg(x) m_internal_ram[m_RBW + (x)] -#define Wreg(x) m_internal_ram[m_RBW + (x)] -#define Breg(x) reinterpret_cast(&m_internal_ram[0])[m_RBB + (x)] - -#define PC() ((Sreg(PS)<<4)+m_ip) - -#define CF (m_CarryVal!=0) -#define SF (m_SignVal<0) -#define ZF (m_ZeroVal==0) -#define PF parity_table[(BYTE)m_ParityVal] -#define AF (m_AuxVal!=0) -#define OF (m_OverVal!=0) -#define RB (m_RBW >> 4) - -/************************************************************************/ - -#define read_mem_byte(a) v25_read_byte((a)) -#define read_mem_word(a) v25_read_word((a)) -#define write_mem_byte(a,d) v25_write_byte((a),(d)) -#define write_mem_word(a,d) v25_write_word((a),(d)) - -#define read_port_byte(a) m_io->read_byte(a) -#define read_port_word(a) m_io->read_word_unaligned(a) -#define write_port_byte(a,d) m_io->write_byte((a),(d)) -#define write_port_word(a,d) m_io->write_word_unaligned((a),(d)) - -/************************************************************************/ - -#define CHANGE_PC do { EMPTY_PREfetch(); } while (0) - -#define SegBase(Seg) (Sreg(Seg) << 4) - -#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4) - -#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off))) -#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off))) - -#define PutMemB(Seg,Off,x) { write_mem_byte(DefaultBase(Seg) + (Off), (x)); } -#define PutMemW(Seg,Off,x) { write_mem_word(DefaultBase(Seg) + (Off), (x)); } - -/* prefetch timing */ - -#define EMPTY_PREfetch() m_prefetch_reset = 1 - - -#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); } -#define POP(var) { Wreg(SP) += 2; var = read_mem_word(((Sreg(SS)<<4) + ((Wreg(SP)-2) & 0xffff))); } - -#define BRKXA(xa) { logerror("%06x: %sXA instruction is V33 exclusive\n", PC(), xa ? "BRK" : "RET"); } -#define BRKEM - -#define GetModRM uint32_t ModRM=fetch() - -/* Cycle count macros: - CLK - cycle count is the same on all processors - CLKS - cycle count differs between processors, list all counts - CLKW - cycle count for word read/write differs for odd/even source/destination address - CLKM - cycle count for reg/mem instructions - CLKR - cycle count for reg/mem instructions with different counts for odd/even addresses - - - Prefetch & buswait time is not emulated. - Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated. -*/ - -#define CLK(all) m_icount-=all -#define CLKS(v20,v30,v33) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; } -#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } -#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); } -#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } - -/************************************************************************/ -#define CompressFlags() (WORD)(CF | (m_IBRK << 1) | (PF << 2) | (m_F0 << 3) | (AF << 4) \ - | (m_F1 << 5) | (ZF << 6) | (SF << 7) | (m_TF << 8) | (m_IF << 9) \ - | (m_DF << 10) | (OF << 11) | (RB << 12) | (m_MF << 15)) - -#define ExpandFlags(f) \ -{ \ - m_CarryVal = (f) & 0x0001; \ - m_IBRK = ((f) & 0x0002) == 0x0002; \ - m_ParityVal = !((f) & 0x0004); \ - m_F0 = ((f) & 0x0008) == 0x0008; \ - m_AuxVal = (f) & 0x0010; \ - m_F1 = ((f) & 0x0020) == 0x0020; \ - m_ZeroVal = !((f) & 0x0040); \ - m_SignVal = (f) & 0x0080 ? -1 : 0; \ - m_TF = ((f) & 0x0100) == 0x0100; \ - m_IF = ((f) & 0x0200) == 0x0200; \ - m_DF = ((f) & 0x0400) == 0x0400; \ - m_OverVal = (f) & 0x0800; \ - /* RB only changes on BRKCS/RETRBI/TSKSW, so skip it */ \ - m_MF = ((f) & 0x8000) == 0x8000; \ -} diff --git a/src/devices/cpu/nec/v25priv.ipp b/src/devices/cpu/nec/v25priv.ipp new file mode 100644 index 00000000000..9287344cb53 --- /dev/null +++ b/src/devices/cpu/nec/v25priv.ipp @@ -0,0 +1,193 @@ +// license:BSD-3-Clause +// copyright-holders:Bryan McPhail, Alex W. Jackson + +namespace { + +/* Cpu types, steps of 8 to help the cycle count calculation */ +#define V33_TYPE 0 +#define V30_TYPE 8 +#define V20_TYPE 16 + +/* interrupt vectors */ +enum +{ + NEC_DIVIDE_VECTOR = 0, + NEC_TRAP_VECTOR = 1, + NEC_NMI_VECTOR = 2, + NEC_BRKV_VECTOR = 4, + NEC_CHKIND_VECTOR = 5, + NEC_IBRK_VECTOR = 19, + NEC_INTTU0_VECTOR = 28, + NEC_INTTU1_VECTOR = 29, + NEC_INTTU2_VECTOR = 30, + NEC_INTD0_VECTOR = 20, + NEC_INTD1_VECTOR = 21, + NEC_INTP0_VECTOR = 24, + NEC_INTP1_VECTOR = 25, + NEC_INTP2_VECTOR = 26, + NEC_INTSER0_VECTOR = 12, + NEC_INTSR0_VECTOR = 13, + NEC_INTST0_VECTOR = 14, + NEC_INTSER1_VECTOR = 16, + NEC_INTSR1_VECTOR = 17, + NEC_INTST1_VECTOR = 18, + NEC_INTTB_VECTOR = 31 +}; + +/* interrupt sources */ +enum INTSOURCES +{ + BRK = 0, + INT_IRQ = 1, + NMI_IRQ = 1 << 1, + INTTU0 = 1 << 2, + INTTU1 = 1 << 3, + INTTU2 = 1 << 4, + INTD0 = 1 << 5, + INTD1 = 1 << 6, + INTP0 = 1 << 7, + INTP1 = 1 << 8, + INTP2 = 1 << 9, + INTSER0 = 1 << 10, + INTSR0 = 1 << 11, + INTST0 = 1 << 12, + INTSER1 = 1 << 13, + INTSR1 = 1 << 14, + INTST1 = 1 << 15, + INTTB = 1 << 16, + BRKN = 1 << 17, + BRKS = 1 << 18 +}; + +enum { + VECTOR_PC = 0x02/2, + PSW_SAVE = 0x04/2, + PC_SAVE = 0x06/2 +}; + +enum SREGS { + DS1 = 0x0E/2, + PS = 0x0C/2, + SS = 0x0A/2, + DS0 = 0x08/2 +}; + +enum WREGS { + AW = 0x1E/2, + CW = 0x1C/2, + DW = 0x1A/2, + BW = 0x18/2, + SP = 0x16/2, + BP = 0x14/2, + IX = 0x12/2, + IY = 0x10/2 +}; + +enum BREGS { + AL = NATIVE_ENDIAN_VALUE_LE_BE(0x1E, 0x1F), + AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1F, 0x1E), + CL = NATIVE_ENDIAN_VALUE_LE_BE(0x1C, 0x1D), + CH = NATIVE_ENDIAN_VALUE_LE_BE(0x1D, 0x1C), + DL = NATIVE_ENDIAN_VALUE_LE_BE(0x1A, 0x1B), + DH = NATIVE_ENDIAN_VALUE_LE_BE(0x1B, 0x1A), + BL = NATIVE_ENDIAN_VALUE_LE_BE(0x18, 0x19), + BH = NATIVE_ENDIAN_VALUE_LE_BE(0x19, 0x18) +}; + +#define SetRB(x) do { m_RBW = (x) << 4; m_RBB = (x) << 5; } while (0) + +#define Sreg(x) m_internal_ram[m_RBW + (x)] +#define Wreg(x) m_internal_ram[m_RBW + (x)] +#define Breg(x) reinterpret_cast(&m_internal_ram[0])[m_RBB + (x)] + +#define PC() ((Sreg(PS)<<4)+m_ip) + +#define CF (m_CarryVal!=0) +#define SF (m_SignVal<0) +#define ZF (m_ZeroVal==0) +#define PF parity_table[(BYTE)m_ParityVal] +#define AF (m_AuxVal!=0) +#define OF (m_OverVal!=0) +#define RB (m_RBW >> 4) + +/************************************************************************/ + +#define read_mem_byte(a) v25_read_byte((a)) +#define read_mem_word(a) v25_read_word((a)) +#define write_mem_byte(a,d) v25_write_byte((a),(d)) +#define write_mem_word(a,d) v25_write_word((a),(d)) + +#define read_port_byte(a) m_io->read_byte(a) +#define read_port_word(a) m_io->read_word_unaligned(a) +#define write_port_byte(a,d) m_io->write_byte((a),(d)) +#define write_port_word(a,d) m_io->write_word_unaligned((a),(d)) + +/************************************************************************/ + +#define CHANGE_PC do { EMPTY_PREfetch(); } while (0) + +#define SegBase(Seg) (Sreg(Seg) << 4) + +#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4) + +#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off))) +#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off))) + +#define PutMemB(Seg,Off,x) { write_mem_byte(DefaultBase(Seg) + (Off), (x)); } +#define PutMemW(Seg,Off,x) { write_mem_word(DefaultBase(Seg) + (Off), (x)); } + +/* prefetch timing */ + +#define EMPTY_PREfetch() m_prefetch_reset = 1 + + +#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); } +#define POP(var) { Wreg(SP) += 2; var = read_mem_word(((Sreg(SS)<<4) + ((Wreg(SP)-2) & 0xffff))); } + +#define BRKXA(xa) { logerror("%06x: %sXA instruction is V33 exclusive\n", PC(), xa ? "BRK" : "RET"); } +#define BRKEM + +#define GetModRM uint32_t ModRM=fetch() + +/* Cycle count macros: + CLK - cycle count is the same on all processors + CLKS - cycle count differs between processors, list all counts + CLKW - cycle count for word read/write differs for odd/even source/destination address + CLKM - cycle count for reg/mem instructions + CLKR - cycle count for reg/mem instructions with different counts for odd/even addresses + + + Prefetch & buswait time is not emulated. + Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated. +*/ + +#define CLK(all) m_icount-=all +#define CLKS(v20,v30,v33) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; } +#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } +#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const uint32_t ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); } +#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const uint32_t ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); } + +/************************************************************************/ +#define CompressFlags() (WORD)(CF | (m_IBRK << 1) | (PF << 2) | (m_F0 << 3) | (AF << 4) \ + | (m_F1 << 5) | (ZF << 6) | (SF << 7) | (m_TF << 8) | (m_IF << 9) \ + | (m_DF << 10) | (OF << 11) | (RB << 12) | (m_MF << 15)) + +#define ExpandFlags(f) \ +{ \ + m_CarryVal = (f) & 0x0001; \ + m_IBRK = ((f) & 0x0002) == 0x0002; \ + m_ParityVal = !((f) & 0x0004); \ + m_F0 = ((f) & 0x0008) == 0x0008; \ + m_AuxVal = (f) & 0x0010; \ + m_F1 = ((f) & 0x0020) == 0x0020; \ + m_ZeroVal = !((f) & 0x0040); \ + m_SignVal = (f) & 0x0080 ? -1 : 0; \ + m_TF = ((f) & 0x0100) == 0x0100; \ + m_IF = ((f) & 0x0200) == 0x0200; \ + m_DF = ((f) & 0x0400) == 0x0400; \ + m_OverVal = (f) & 0x0800; \ + /* RB only changes on BRKCS/RETRBI/TSKSW, so skip it */ \ + m_MF = ((f) & 0x8000) == 0x8000; \ +} + +} // anonymous namespace diff --git a/src/devices/cpu/nec/v25sfr.cpp b/src/devices/cpu/nec/v25sfr.cpp index 7c606a82afd..81d9d5569b0 100644 --- a/src/devices/cpu/nec/v25sfr.cpp +++ b/src/devices/cpu/nec/v25sfr.cpp @@ -8,7 +8,7 @@ #include "emu.h" #include "v25.h" -#include "v25priv.h" +#include "v25priv.ipp" void v25_common_device::ida_sfr_map(address_map &map) { diff --git a/src/devices/cpu/nec/v5x.cpp b/src/devices/cpu/nec/v5x.cpp index 9598d63ea2b..70a065db994 100644 --- a/src/devices/cpu/nec/v5x.cpp +++ b/src/devices/cpu/nec/v5x.cpp @@ -30,7 +30,7 @@ #include "emu.h" #include "v5x.h" -#include "necpriv.h" +#include "necpriv.ipp" #define VERBOSE 0 #include "logmacro.h" -- cgit v1.2.3