From 2507aea08241db36a0cbba8278c554d2bb5bfe2e Mon Sep 17 00:00:00 2001 From: AJR Date: Thu, 18 Jun 2020 21:32:26 -0400 Subject: tmp95c061, tmp95c063: Break up the register blocks (nw) --- src/devices/cpu/tlcs900/tlcs900.cpp | 16 +- src/devices/cpu/tlcs900/tlcs900.h | 2 +- src/devices/cpu/tlcs900/tmp95c061.cpp | 1183 +++++++++++++++-------- src/devices/cpu/tlcs900/tmp95c061.h | 152 ++- src/devices/cpu/tlcs900/tmp95c063.cpp | 1650 +++++++++++++++++++++------------ src/devices/cpu/tlcs900/tmp95c063.h | 181 +++- 6 files changed, 2232 insertions(+), 952 deletions(-) diff --git a/src/devices/cpu/tlcs900/tlcs900.cpp b/src/devices/cpu/tlcs900/tlcs900.cpp index a0f9d67d597..914257bee9e 100644 --- a/src/devices/cpu/tlcs900/tlcs900.cpp +++ b/src/devices/cpu/tlcs900/tlcs900.cpp @@ -108,7 +108,6 @@ void tlcs900h_device::device_start() save_item( NAME(m_dmad) ); save_item( NAME(m_dmac) ); save_item( NAME(m_dmam) ); - save_item( NAME(m_reg) ); save_item( NAME(m_timer_pre) ); save_item( NAME(m_timer) ); save_item( NAME(m_timer_change) ); @@ -166,6 +165,21 @@ void tlcs900h_device::device_start() set_icountptr(m_icount); } +void tlcs900h_device::device_reset() +{ + m_pc.b.l = RDMEM( 0xFFFF00 ); + m_pc.b.h = RDMEM( 0xFFFF01 ); + m_pc.b.h2 = RDMEM( 0xFFFF02 ); + m_pc.b.h3 = 0; + /* system mode, iff set to 111, max mode, register bank 0 */ + m_sr.d = 0xF800; + m_regbank = 0; + m_xssp.d = 0x0100; + m_halted = 0; + m_check_irqs = 0; + m_prefetch_clear = true; +} + void tlcs900h_device::state_string_export(const device_state_entry &entry, std::string &str) const { diff --git a/src/devices/cpu/tlcs900/tlcs900.h b/src/devices/cpu/tlcs900/tlcs900.h index 1007479c787..4bfc7aee4ca 100644 --- a/src/devices/cpu/tlcs900/tlcs900.h +++ b/src/devices/cpu/tlcs900/tlcs900.h @@ -52,6 +52,7 @@ protected: // device-level overrides virtual void device_start() override; + virtual void device_reset() override; // device_execute_interface overrides virtual uint32_t execute_min_cycles() const noexcept override { return 1; } /* FIXME */ @@ -100,7 +101,6 @@ protected: PAIR m_dmam[4]; /* Internal timers, irqs, etc */ - uint8_t m_reg[0xa0]; uint32_t m_timer_pre; uint8_t m_timer[6]; int m_timer_change[4]; diff --git a/src/devices/cpu/tlcs900/tmp95c061.cpp b/src/devices/cpu/tlcs900/tmp95c061.cpp index 9116078d036..5486263028e 100644 --- a/src/devices/cpu/tlcs900/tmp95c061.cpp +++ b/src/devices/cpu/tlcs900/tmp95c061.cpp @@ -29,13 +29,107 @@ tmp95c061_device::tmp95c061_device(const machine_config &mconfig, const char *ta m_porta_read(*this), m_porta_write(*this), m_portb_read(*this), - m_portb_write(*this) + m_portb_write(*this), + m_port_latch{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_port_control{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_port_function{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_trun(0), + m_t8_reg{ 0, 0, 0, 0 }, + m_t8_mode{ 0, 0 }, + m_t8_invert(0), + m_trdc(0), + m_to1(0), + m_to3(0), + m_t16_reg{ 0, 0, 0, 0 }, + m_t16_cap{ 0, 0, 0, 0 }, + m_t16_mode{ 0, 0 }, + m_t16_invert{ 0, 0 }, + m_t45cr(0), + m_pgreg{ 0, 0 }, + m_pg01cr(0), + m_watchdog_mode(0), + m_serial_control{ 0, 0 }, + m_serial_mode{ 0, 0 }, + m_baud_rate{ 0, 0 }, + m_od_enable(0), + m_ad_result{ 0, 0, 0, 0 }, + m_ad_mode(0), + m_int_reg{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_iimc(0), + m_dma_vector{ 0, 0, 0, 0 }, + m_block_cs{ 0, 0, 0, 0 }, + m_external_cs(0), + m_mem_start_reg{ 0, 0, 0, 0 }, + m_mem_start_mask{ 0, 0, 0, 0 }, + m_dram_refresh(0), + m_dram_access(0) { } void tmp95c061_device::internal_mem(address_map &map) { - map(0x000000, 0x00007f).rw(FUNC(tmp95c061_device::internal_r), FUNC(tmp95c061_device::internal_w)); + map(0x000001, 0x000001).rw(FUNC(tmp95c061_device::p1_r), FUNC(tmp95c061_device::p1_w)); + map(0x000004, 0x000004).w(FUNC(tmp95c061_device::p1cr_w)); + map(0x000006, 0x000006).rw(FUNC(tmp95c061_device::p2_r), FUNC(tmp95c061_device::p2_w)); + map(0x000009, 0x000009).w(FUNC(tmp95c061_device::p2fc_w)); + map(0x00000d, 0x00000d).rw(FUNC(tmp95c061_device::p5_r), FUNC(tmp95c061_device::p5_w)); + map(0x000010, 0x000010).w(FUNC(tmp95c061_device::p5cr_w)); + map(0x000011, 0x000011).w(FUNC(tmp95c061_device::p5fc_w)); + map(0x000012, 0x000012).rw(FUNC(tmp95c061_device::p6_r), FUNC(tmp95c061_device::p6_w)); + map(0x000013, 0x000013).rw(FUNC(tmp95c061_device::p7_r), FUNC(tmp95c061_device::p7_w)); + map(0x000015, 0x000015).w(FUNC(tmp95c061_device::p6fc_w)); + map(0x000016, 0x000016).w(FUNC(tmp95c061_device::p7cr_w)); + map(0x000017, 0x000017).w(FUNC(tmp95c061_device::p7fc_w)); + map(0x000018, 0x000018).rw(FUNC(tmp95c061_device::p8_r), FUNC(tmp95c061_device::p8_w)); + map(0x000019, 0x000019).r(FUNC(tmp95c061_device::p9_r)); + map(0x00001a, 0x00001a).w(FUNC(tmp95c061_device::p8cr_w)); + map(0x00001b, 0x00001b).w(FUNC(tmp95c061_device::p8fc_w)); + map(0x00001e, 0x00001e).rw(FUNC(tmp95c061_device::pa_r), FUNC(tmp95c061_device::pa_w)); + map(0x00001f, 0x00001f).rw(FUNC(tmp95c061_device::pb_r), FUNC(tmp95c061_device::pb_w)); + map(0x000020, 0x000020).rw(FUNC(tmp95c061_device::trun_r), FUNC(tmp95c061_device::trun_w)); + map(0x000022, 0x000023).w(FUNC(tmp95c061_device::treg01_w)); + map(0x000024, 0x000024).w(FUNC(tmp95c061_device::t01mod_w)); + map(0x000025, 0x000025).rw(FUNC(tmp95c061_device::tffcr_r), FUNC(tmp95c061_device::tffcr_w)); + map(0x000026, 0x000027).w(FUNC(tmp95c061_device::treg23_w)); + map(0x000028, 0x000028).w(FUNC(tmp95c061_device::t23mod_w)); + map(0x000029, 0x000029).rw(FUNC(tmp95c061_device::trdc_r), FUNC(tmp95c061_device::trdc_w)); + map(0x00002c, 0x00002c).w(FUNC(tmp95c061_device::pacr_w)); + map(0x00002d, 0x00002d).w(FUNC(tmp95c061_device::pafc_w)); + map(0x00002e, 0x00002e).w(FUNC(tmp95c061_device::pbcr_w)); + map(0x00002f, 0x00002f).w(FUNC(tmp95c061_device::pbfc_w)); + map(0x000030, 0x000033).w(FUNC(tmp95c061_device::treg45_w)); + map(0x000034, 0x000037).r(FUNC(tmp95c061_device::cap12_r)); + map(0x000038, 0x000038).rw(FUNC(tmp95c061_device::t4mod_r), FUNC(tmp95c061_device::t4mod_w)); + map(0x000039, 0x000039).rw(FUNC(tmp95c061_device::t4ffcr_r), FUNC(tmp95c061_device::t4ffcr_w)); + map(0x00003a, 0x00003a).rw(FUNC(tmp95c061_device::t45cr_r), FUNC(tmp95c061_device::t45cr_w)); + map(0x00003c, 0x00003f).rw(FUNC(tmp95c061_device::msar01_r), FUNC(tmp95c061_device::msar01_w)); + map(0x000040, 0x000043).w(FUNC(tmp95c061_device::treg67_w)); + map(0x000044, 0x000047).r(FUNC(tmp95c061_device::cap34_r)); + map(0x000048, 0x000048).rw(FUNC(tmp95c061_device::t5mod_r), FUNC(tmp95c061_device::t5mod_w)); + map(0x000049, 0x000049).rw(FUNC(tmp95c061_device::t5ffcr_r), FUNC(tmp95c061_device::t5ffcr_w)); + map(0x00004c, 0x00004d).rw(FUNC(tmp95c061_device::pgreg_r), FUNC(tmp95c061_device::pgreg_w)); + map(0x00004e, 0x00004e).rw(FUNC(tmp95c061_device::pg01cr_r), FUNC(tmp95c061_device::pg01cr_w)); + map(0x000050, 0x000050).rw(FUNC(tmp95c061_device::sc0buf_r), FUNC(tmp95c061_device::sc0buf_w)); + map(0x000051, 0x000051).rw(FUNC(tmp95c061_device::sc0cr_r), FUNC(tmp95c061_device::sc0cr_w)); + map(0x000052, 0x000052).rw(FUNC(tmp95c061_device::sc0mod_r), FUNC(tmp95c061_device::sc0mod_w)); + map(0x000053, 0x000053).rw(FUNC(tmp95c061_device::br0cr_r), FUNC(tmp95c061_device::br0cr_w)); + map(0x000054, 0x000054).rw(FUNC(tmp95c061_device::sc1buf_r), FUNC(tmp95c061_device::sc1buf_w)); + map(0x000055, 0x000055).rw(FUNC(tmp95c061_device::sc1cr_r), FUNC(tmp95c061_device::sc1cr_w)); + map(0x000056, 0x000056).rw(FUNC(tmp95c061_device::sc1mod_r), FUNC(tmp95c061_device::sc1mod_w)); + map(0x000057, 0x000057).rw(FUNC(tmp95c061_device::br1cr_r), FUNC(tmp95c061_device::br1cr_w)); + map(0x000058, 0x000058).rw(FUNC(tmp95c061_device::ode_r), FUNC(tmp95c061_device::ode_w)); + map(0x00005a, 0x00005a).rw(FUNC(tmp95c061_device::drefcr_r), FUNC(tmp95c061_device::drefcr_w)); + map(0x00005b, 0x00005b).rw(FUNC(tmp95c061_device::dmemcr_r), FUNC(tmp95c061_device::dmemcr_w)); + map(0x00005c, 0x00005f).rw(FUNC(tmp95c061_device::msar23_r), FUNC(tmp95c061_device::msar23_w)); + map(0x000060, 0x000067).r(FUNC(tmp95c061_device::adreg_r)); + map(0x000068, 0x00006b).w(FUNC(tmp95c061_device::bcs_w)); + map(0x00006c, 0x00006c).w(FUNC(tmp95c061_device::bexcs_w)); + map(0x00006d, 0x00006d).rw(FUNC(tmp95c061_device::admod_r), FUNC(tmp95c061_device::admod_w)); + map(0x00006e, 0x00006e).rw(FUNC(tmp95c061_device::wdmod_r), FUNC(tmp95c061_device::wdmod_w)); + map(0x00006f, 0x00006f).w(FUNC(tmp95c061_device::wdcr_w)); + map(0x000070, 0x00007a).rw(FUNC(tmp95c061_device::inte_r), FUNC(tmp95c061_device::inte_w)); + map(0x00007b, 0x00007b).w(FUNC(tmp95c061_device::iimc_w)); + map(0x00007c, 0x00007f).w(FUNC(tmp95c061_device::dmav_w)); } //------------------------------------------------- @@ -58,121 +152,43 @@ void tmp95c061_device::device_config_complete() -/* Internal register defines */ -#define TMP95C061_P1 0x01 -#define TMP95C061_P1CR 0x02 -#define TMP95C061_P2 0x06 -#define TMP95C061_P2FC 0x09 -#define TMP95C061_P5 0x0d -#define TMP95C061_P5CR 0x10 -#define TMP95C061_P5FC 0x11 -#define TMP95C061_P6 0x12 -#define TMP95C061_P7 0x13 -#define TMP95C061_P6FC 0x15 -#define TMP95C061_P7CR 0x16 -#define TMP95C061_P7FC 0x17 -#define TMP95C061_P8 0x18 -#define TMP95C061_P9 0x19 -#define TMP95C061_P8CR 0x1a -#define TMP95C061_P8FC 0x1b -#define TMP95C061_PA 0x1e -#define TMP95C061_PB 0x1f -#define TMP95C061_TRUN 0x20 -#define TMP95C061_TREG0 0x22 -#define TMP95C061_TREG1 0x23 -#define TMP95C061_T01MOD 0x24 -#define TMP95C061_TFFCR 0x25 -#define TMP95C061_TREG2 0x26 -#define TMP95C061_TREG3 0x27 -#define TMP95C061_T23MOD 0x28 -#define TMP95C061_TRDC 0x29 -#define TMP95C061_PACR 0x2c -#define TMP95C061_PAFC 0x2d -#define TMP95C061_PBCR 0x2e -#define TMP95C061_PBFC 0x2f -#define TMP95C061_TREG4L 0x30 -#define TMP95C061_TREG4H 0x31 -#define TMP95C061_TREG5L 0x32 -#define TMP95C061_TREG5H 0x33 -#define TMP95C061_CAP1L 0x34 -#define TMP95C061_CAP1H 0x35 -#define TMP95C061_CAP2L 0x36 -#define TMP95C061_CAP2H 0x37 -#define TMP95C061_T4MOD 0x38 -#define TMP95C061_T4FFCR 0x39 -#define TMP95C061_T45CR 0x3a -#define TMP95C061_MSAR0 0x3c -#define TMP95C061_MAMR0 0x3d -#define TMP95C061_MSAR1 0x3e -#define TMP95C061_MAMR1 0x3f -#define TMP95C061_TREG6L 0x40 -#define TMP95C061_TREG6H 0x41 -#define TMP95C061_TREG7L 0x42 -#define TMP95C061_TREG7H 0x43 -#define TMP95C061_CAP3L 0x44 -#define TMP95C061_CAP3H 0x45 -#define TMP95C061_CAP4L 0x46 -#define TMP95C061_CAP4H 0x47 -#define TMP95C061_T5MOD 0x48 -#define TMP95C061_T5FFCR 0x49 -#define TMP95C061_PG0REG 0x4c -#define TMP95C061_PG1REG 0x4d -#define TMP95C061_PG01CR 0x4e -#define TMP95C061_SC0BUF 0x50 -#define TMP95C061_SC0CR 0x51 -#define TMP95C061_SC0MOD 0x52 -#define TMP95C061_BR0CR 0x53 -#define TMP95C061_SC1BUF 0x54 -#define TMP95C061_SC1CR 0x55 -#define TMP95C061_SC1MOD 0x56 -#define TMP95C061_BR1CR 0x57 -#define TMP95C061_ODE 0x58 -#define TMP95C061_DREFCR 0x5a -#define TMP95C061_DMEMCR 0x5b -#define TMP95C061_MSAR2 0x5c -#define TMP95C061_MAMR2 0x5d -#define TMP95C061_MSAR3 0x5e -#define TMP95C061_MAMR3 0x5f -#define TMP95C061_ADREG0L 0x60 -#define TMP95C061_ADREG0H 0x61 -#define TMP95C061_ADREG1L 0x62 -#define TMP95C061_ADREG1H 0x63 -#define TMP95C061_ADREG2L 0x64 -#define TMP95C061_ADREG2H 0x65 -#define TMP95C061_ADREG3L 0x66 -#define TMP95C061_ADREG3H 0x67 -#define TMP95C061_B0CS 0x68 -#define TMP95C061_B1CS 0x69 -#define TMP95C061_B2CS 0x6a -#define TMP95C061_B3CS 0x6b -#define TMP95C061_BEXCS 0x6c -#define TMP95C061_ADMOD 0x6d -#define TMP95C061_WDMOD 0x6e -#define TMP95C061_WDCR 0x6f -#define TMP95C061_INTE0AD 0x70 -#define TMP95C061_INTE45 0x71 -#define TMP95C061_INTE67 0x72 -#define TMP95C061_INTET10 0x73 -#define TMP95C061_INTET32 0x74 -#define TMP95C061_INTET54 0x75 -#define TMP95C061_INTET76 0x76 -#define TMP95C061_INTES0 0x77 -#define TMP95C061_INTES1 0x78 -#define TMP95C061_INTETC10 0x79 -#define TMP95C061_INTETC32 0x7a -#define TMP95C061_IIMC 0x7b -#define TMP95C061_DMA0V 0x7c -#define TMP95C061_DMA1V 0x7d -#define TMP95C061_DMA2V 0x7e -#define TMP95C061_DMA3V 0x7f - - void tmp95c061_device::device_start() { tlcs900h_device::device_start(); - save_item( NAME(m_to1) ); - save_item( NAME(m_to3) ); + save_item(NAME(m_port_latch)); + save_item(NAME(m_port_control)); + save_item(NAME(m_port_function)); + save_item(NAME(m_trun)); + save_item(NAME(m_t8_reg)); + save_item(NAME(m_t8_mode)); + save_item(NAME(m_t8_invert)); + save_item(NAME(m_trdc)); + save_item(NAME(m_to1)); + save_item(NAME(m_to3)); + save_item(NAME(m_t16_reg)); + save_item(NAME(m_t16_cap)); + save_item(NAME(m_t16_mode)); + save_item(NAME(m_t16_invert)); + save_item(NAME(m_t45cr)); + save_item(NAME(m_pgreg)); + save_item(NAME(m_pg01cr)); + save_item(NAME(m_watchdog_mode)); + save_item(NAME(m_serial_control)); + save_item(NAME(m_serial_mode)); + save_item(NAME(m_baud_rate)); + save_item(NAME(m_od_enable)); + save_item(NAME(m_ad_result)); + save_item(NAME(m_ad_mode)); + save_item(NAME(m_int_reg)); + save_item(NAME(m_iimc)); + save_item(NAME(m_dma_vector)); + save_item(NAME(m_block_cs)); + save_item(NAME(m_external_cs)); + save_item(NAME(m_mem_start_reg)); + save_item(NAME(m_mem_start_mask)); + save_item(NAME(m_dram_refresh)); + save_item(NAME(m_dram_access)); m_port1_read.resolve_safe(0); m_port1_write.resolve_safe(); @@ -194,21 +210,11 @@ void tmp95c061_device::device_start() void tmp95c061_device::device_reset() { - int i; + tlcs900h_device::device_reset(); m_to1 = 0; m_to3 = 0; - m_pc.b.l = RDMEM( 0xFFFF00 ); - m_pc.b.h = RDMEM( 0xFFFF01 ); - m_pc.b.h2 = RDMEM( 0xFFFF02 ); - m_pc.b.h3 = 0; - /* system mode, iff set to 111, max mode, register bank 0 */ - m_sr.d = 0xF800; - m_regbank = 0; - m_xssp.d = 0x0100; - m_halted = 0; - m_check_irqs = 0; m_ad_cycles_left = 0; m_nmi_state = CLEAR_LINE; m_timer_pre = 0; @@ -217,75 +223,68 @@ void tmp95c061_device::device_reset() m_timer_change[2] = 0; m_timer_change[3] = 0; - memset(m_reg, 0x00, sizeof(m_reg)); - - m_reg[TMP95C061_P1] = 0x00; - m_reg[TMP95C061_P1CR] = 0x00; - m_reg[TMP95C061_P2] = 0xff; - m_reg[TMP95C061_P2FC] = 0x00; - m_reg[TMP95C061_P5] = 0x3d; - m_reg[TMP95C061_P5CR] = 0x00; - m_reg[TMP95C061_P5FC] = 0x00; - m_reg[TMP95C061_P6] = 0x3b; - m_reg[TMP95C061_P6FC] = 0x00; - m_reg[TMP95C061_P7] = 0xff; - m_reg[TMP95C061_P7CR] = 0x00; - m_reg[TMP95C061_P7FC] = 0x00; - m_reg[TMP95C061_P8] = 0x3f; - m_reg[TMP95C061_P8CR] = 0x00; - m_reg[TMP95C061_P8FC] = 0x00; - m_reg[TMP95C061_PA] = 0x0f; - m_reg[TMP95C061_PACR] = 0x0c; // HACK ngpc needs this but should be zero - m_reg[TMP95C061_PAFC] = 0x0c; // HACK ngpc needs this but should be zero - m_reg[TMP95C061_PB] = 0xff; - m_reg[TMP95C061_PBCR] = 0x00; - m_reg[TMP95C061_PBFC] = 0x00; - m_reg[TMP95C061_MSAR0] = 0xff; - m_reg[TMP95C061_MSAR1] = 0xff; - m_reg[TMP95C061_MSAR2] = 0xff; - m_reg[TMP95C061_MSAR3] = 0xff; - m_reg[TMP95C061_MAMR0] = 0xff; - m_reg[TMP95C061_MAMR1] = 0xff; - m_reg[TMP95C061_MAMR2] = 0xff; - m_reg[TMP95C061_MAMR3] = 0xff; - m_reg[TMP95C061_DREFCR] = 0x00; - m_reg[TMP95C061_DMEMCR] = 0x80; - m_reg[TMP95C061_T01MOD] = 0x00; - m_reg[TMP95C061_T23MOD] = 0x00; - m_reg[TMP95C061_TFFCR] = 0x00; - m_reg[TMP95C061_TRUN] = 0x00; - m_reg[TMP95C061_TRDC] = 0x00; - m_reg[TMP95C061_T4MOD] = 0x20; - m_reg[TMP95C061_T4FFCR] = 0x00; - m_reg[TMP95C061_T5MOD] = 0x20; - m_reg[TMP95C061_T5FFCR] = 0x00; - m_reg[TMP95C061_T45CR] = 0x00; - m_reg[TMP95C061_PG01CR] = 0x00; - m_reg[TMP95C061_PG0REG] = 0x00; - m_reg[TMP95C061_PG1REG] = 0x00; - m_reg[TMP95C061_SC0MOD] = 0x00; - m_reg[TMP95C061_SC0CR] = 0x00; - m_reg[TMP95C061_BR0CR] = 0x00; - m_reg[TMP95C061_SC1MOD] = 0x00; - m_reg[TMP95C061_SC1CR] = 0x00; - m_reg[TMP95C061_BR1CR] = 0x00; - m_reg[TMP95C061_P8FC] = 0x00; - m_reg[TMP95C061_ODE] = 0x00; - m_reg[TMP95C061_ADMOD] = 0x00; - m_reg[TMP95C061_ADREG0L] = 0x3f; - m_reg[TMP95C061_ADREG1L] = 0x3f; - m_reg[TMP95C061_ADREG2L] = 0x3f; - m_reg[TMP95C061_ADREG3L] = 0x3f; - m_reg[TMP95C061_WDMOD] = 0x80; - - for ( i = 0; i < TLCS900_NUM_INPUTS; i++ ) + m_port_latch[1] = 0x00; + m_port_latch[2] = 0xff; + m_port_latch[5] = 0x3d; + m_port_latch[6] = 0x3b; + m_port_latch[7] = 0xff; + m_port_latch[8] = 0x3f; + m_port_latch[0xa] = 0x0f; + m_port_latch[0xb] = 0xff; + std::fill_n(&m_port_control[0], 0xc, 0x00); + std::fill_n(&m_port_function[0], 0xc, 0x00); + m_port_control[0xa] = 0x0c; // HACK ngpc needs this but should be zero + m_port_function[0xa] = 0x0c; // HACK ngpc needs this but should be zero + m_trun = 0x00; + std::fill_n(&m_t8_mode[0], 2, 0x00); + m_t8_invert = 0xcc; + m_trdc = 0x00; + std::fill_n(&m_t16_mode[0], 2, 0x20); + std::fill_n(&m_t16_invert[0], 2, 0x00); + m_t45cr = 0x00; + m_pgreg[0] &= 0x0f; + m_pgreg[1] &= 0x0f; + m_pg01cr = 0x00; + m_watchdog_mode = 0x80; + for (int i = 0; i < 2; i++) + { + m_serial_control[i] &= 0x80; + m_serial_mode[i] &= 0x80; + m_baud_rate[i] = 0x00; + } + m_od_enable = 0x00; + m_ad_mode = 0x00; + std::fill_n(&m_int_reg[0], 0xb, 0x00); + m_iimc = 0x00; + std::fill_n(&m_dma_vector[0], 4, 0x00); + m_block_cs[0] = 0x00; + m_block_cs[1] = 0x00; + m_block_cs[2] = 0x10; + m_block_cs[3] = 0x00; + m_external_cs = 0x00; + std::fill_n(&m_mem_start_reg[0], 4, 0xff); + std::fill_n(&m_mem_start_mask[0], 4, 0xff); + m_dram_refresh = 0x00; + m_dram_access = 0x80; + + for (int i = 0; i < TLCS900_NUM_INPUTS; i++) { m_level[i] = CLEAR_LINE; } - m_prefetch_clear = true; } +#define TMP95C061_INTE0AD 0x0 +#define TMP95C061_INTE45 0x1 +#define TMP95C061_INTE67 0x2 +#define TMP95C061_INTET10 0x3 +#define TMP95C061_INTET32 0x4 +#define TMP95C061_INTET54 0x5 +#define TMP95C061_INTET76 0x6 +#define TMP95C061_INTES0 0x7 +#define TMP95C061_INTES1 0x8 +#define TMP95C061_INTETC10 0x9 +#define TMP95C061_INTETC32 0xa #define TMP95C061_NUM_MASKABLE_IRQS 22 static const struct { @@ -322,7 +321,7 @@ static const struct { int tmp95c061_device::tlcs900_process_hdma( int channel ) { - uint8_t vector = ( m_reg[0x7c + channel] & 0x1f ) << 2; + uint8_t vector = ( m_dma_vector[channel] & 0x1f ) << 2; /* Check if any HDMA actions should be performed */ if ( vector >= 0x28 && vector != 0x3C && vector < 0x74 ) @@ -333,7 +332,7 @@ int tmp95c061_device::tlcs900_process_hdma( int channel ) irq++; /* Check if our interrupt flip-flop is set */ - if ( irq < TMP95C061_NUM_MASKABLE_IRQS && m_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff ) + if ( irq < TMP95C061_NUM_MASKABLE_IRQS && m_int_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff ) { switch( m_dmam[channel].b.l & 0x1f ) { @@ -419,26 +418,26 @@ int tmp95c061_device::tlcs900_process_hdma( int channel ) if ( m_dmac[channel].w.l == 0 ) { - m_reg[0x7c + channel] = 0; + m_dma_vector[channel] = 0; switch( channel ) { case 0: - m_reg[TMP95C061_INTETC10] |= 0x08; + m_int_reg[TMP95C061_INTETC10] |= 0x08; break; case 1: - m_reg[TMP95C061_INTETC10] |= 0x80; + m_int_reg[TMP95C061_INTETC10] |= 0x80; break; case 2: - m_reg[TMP95C061_INTETC32] |= 0x08; + m_int_reg[TMP95C061_INTETC32] |= 0x08; break; case 3: - m_reg[TMP95C061_INTETC32] |= 0x80; + m_int_reg[TMP95C061_INTETC32] |= 0x80; break; } } /* Clear the interrupt flip-flop */ - m_reg[tmp95c061_irq_vector_map[irq].reg] &= ~tmp95c061_irq_vector_map[irq].iff; + m_int_reg[tmp95c061_irq_vector_map[irq].reg] &= ~tmp95c061_irq_vector_map[irq].iff; return 1; } @@ -494,15 +493,15 @@ void tmp95c061_device::tlcs900_check_irqs() /* Check regular irqs */ for( i = 0; i < TMP95C061_NUM_MASKABLE_IRQS; i++ ) { - if ( m_reg[tmp95c061_irq_vector_map[i].reg] & tmp95c061_irq_vector_map[i].iff ) + if ( m_int_reg[tmp95c061_irq_vector_map[i].reg] & tmp95c061_irq_vector_map[i].iff ) { switch( tmp95c061_irq_vector_map[i].iff ) { case 0x80: - irq_vectors[ ( m_reg[ tmp95c061_irq_vector_map[i].reg ] >> 4 ) & 0x07 ] = i; + irq_vectors[ ( m_int_reg[ tmp95c061_irq_vector_map[i].reg ] >> 4 ) & 0x07 ] = i; break; case 0x08: - irq_vectors[ m_reg[ tmp95c061_irq_vector_map[i].reg ] & 0x07 ] = i; + irq_vectors[ m_int_reg[ tmp95c061_irq_vector_map[i].reg ] & 0x07 ] = i; break; } } @@ -538,7 +537,7 @@ void tmp95c061_device::tlcs900_check_irqs() m_halted = 0; /* Clear taken IRQ */ - m_reg[ tmp95c061_irq_vector_map[irq].reg ] &= ~ tmp95c061_irq_vector_map[irq].iff; + m_int_reg[ tmp95c061_irq_vector_map[irq].reg ] &= ~ tmp95c061_irq_vector_map[irq].iff; } } @@ -551,11 +550,10 @@ void tmp95c061_device::tlcs900_handle_ad() if ( m_ad_cycles_left <= 0 ) { /* Store A/D converted value */ - switch( m_reg[TMP95C061_ADMOD] & 0x03 ) + switch( m_ad_mode & 0x03 ) { case 0x00: /* AN0 */ - m_reg[TMP95C061_ADREG0L] |= 0xc0; - m_reg[TMP95C061_ADREG0H] = 0xff; + m_ad_result[0] = 0x3ff; break; case 0x01: /* AN1 */ case 0x02: /* AN2 */ @@ -564,10 +562,10 @@ void tmp95c061_device::tlcs900_handle_ad() } /* Clear BUSY flag, set END flag */ - m_reg[TMP95C061_ADMOD] &= ~ 0x40; - m_reg[TMP95C061_ADMOD] |= 0x80; + m_ad_mode &= ~ 0x40; + m_ad_mode |= 0x80; - m_reg[TMP95C061_INTE0AD] |= 0x80; + m_int_reg[TMP95C061_INTE0AD] |= 0x80; m_check_irqs = 1; } } @@ -626,13 +624,13 @@ void tmp95c061_device::tlcs900_handle_timers() uint32_t old_pre = m_timer_pre; /* Is the pre-scaler active */ - if ( m_reg[TMP95C061_TRUN] & 0x80 ) + if ( m_trun & 0x80 ) m_timer_pre += m_cycles; /* Timer 0 */ - if ( m_reg[TMP95C061_TRUN] & 0x01 ) + if ( m_trun & 0x01 ) { - switch( m_reg[TMP95C061_T01MOD] & 0x03 ) + switch( m_t8_mode[0] & 0x03 ) { case 0x00: /* TIO */ break; @@ -649,29 +647,28 @@ void tmp95c061_device::tlcs900_handle_timers() for( ; m_timer_change[0] > 0; m_timer_change[0]-- ) { -//printf("timer0 = %02x, TREG0 = %02x\n", m_timer[0], m_reg[TREG0] ); m_timer[0] += 1; - if ( m_timer[0] == m_reg[TMP95C061_TREG0] ) + if ( m_timer[0] == m_t8_reg[0] ) { - if ( ( m_reg[TMP95C061_T01MOD] & 0x0c ) == 0x00 ) + if ( ( m_t8_mode[0] & 0x0c ) == 0x00 ) { m_timer_change[1] += 1; } /* In 16bit timer mode the timer should not be reset */ - if ( ( m_reg[TMP95C061_T01MOD] & 0xc0 ) != 0x40 ) + if ( ( m_t8_mode[0] & 0xc0 ) != 0x40 ) { m_timer[0] = 0; - m_reg[TMP95C061_INTET10] |= 0x08; + m_int_reg[TMP95C061_INTET10] |= 0x08; } } } } /* Timer 1 */ - if ( m_reg[TMP95C061_TRUN] & 0x02 ) + if ( m_trun & 0x02 ) { - switch( ( m_reg[TMP95C061_T01MOD] >> 2 ) & 0x03 ) + switch( ( m_t8_mode[0] >> 2 ) & 0x03 ) { case 0x00: /* TO0TRG */ break; @@ -689,18 +686,18 @@ void tmp95c061_device::tlcs900_handle_timers() for( ; m_timer_change[1] > 0; m_timer_change[1]-- ) { m_timer[1] += 1; - if ( m_timer[1] == m_reg[TMP95C061_TREG1] ) + if ( m_timer[1] == m_t8_reg[1] ) { m_timer[1] = 0; - m_reg[TMP95C061_INTET10] |= 0x80; + m_int_reg[TMP95C061_INTET10] |= 0x80; - if ( m_reg[TMP95C061_TFFCR] & 0x02 ) + if ( m_t8_invert & 0x02 ) { tlcs900_change_tff( 1, FF_INVERT ); } /* In 16bit timer mode also reset timer 0 */ - if ( ( m_reg[TMP95C061_T01MOD] & 0xc0 ) == 0x40 ) + if ( ( m_t8_mode[0] & 0xc0 ) == 0x40 ) { m_timer[0] = 0; } @@ -709,9 +706,9 @@ void tmp95c061_device::tlcs900_handle_timers() } /* Timer 2 */ - if ( m_reg[TMP95C061_TRUN] & 0x04 ) + if ( m_trun & 0x04 ) { - switch( m_reg[TMP95C061_T23MOD] & 0x03 ) + switch( m_t8_mode[1] & 0x03 ) { case 0x00: /* invalid */ case 0x01: /* T1 */ @@ -728,27 +725,27 @@ void tmp95c061_device::tlcs900_handle_timers() for( ; m_timer_change[2] > 0; m_timer_change[2]-- ) { m_timer[2] += 1; - if ( m_timer[2] == m_reg[TMP95C061_TREG2] ) + if ( m_timer[2] == m_t8_reg[2] ) { - if ( ( m_reg[TMP95C061_T23MOD] & 0x0c ) == 0x00 ) + if ( ( m_t8_mode[1] & 0x0c ) == 0x00 ) { m_timer_change[3] += 1; } /* In 16bit timer mode the timer should not be reset */ - if ( ( m_reg[TMP95C061_T23MOD] & 0xc0 ) != 0x40 ) + if ( ( m_t8_mode[1] & 0xc0 ) != 0x40 ) { m_timer[2] = 0; - m_reg[TMP95C061_INTET32] |= 0x08; + m_int_reg[TMP95C061_INTET32] |= 0x08; } } } } /* Timer 3 */ - if ( m_reg[TMP95C061_TRUN] & 0x08 ) + if ( m_trun & 0x08 ) { - switch( ( m_reg[TMP95C061_T23MOD] >> 2 ) & 0x03 ) + switch( ( m_t8_mode[1] >> 2 ) & 0x03 ) { case 0x00: /* TO2TRG */ break; @@ -766,18 +763,18 @@ void tmp95c061_device::tlcs900_handle_timers() for( ; m_timer_change[3] > 0; m_timer_change[3]-- ) { m_timer[3] += 1; - if ( m_timer[3] == m_reg[TMP95C061_TREG3] ) + if ( m_timer[3] == m_t8_reg[3] ) { m_timer[3] = 0; - m_reg[TMP95C061_INTET32] |= 0x80; + m_int_reg[TMP95C061_INTET32] |= 0x80; - if ( m_reg[TMP95C061_TFFCR] & 0x20 ) + if ( m_t8_invert & 0x20 ) { tlcs900_change_tff( 3, FF_INVERT ); } /* In 16bit timer mode also reset timer 2 */ - if ( ( m_reg[TMP95C061_T23MOD] & 0xc0 ) == 0x40 ) + if ( ( m_t8_mode[1] & 0xc0 ) == 0x40 ) { m_timer[2] = 0; } @@ -807,54 +804,54 @@ void tmp95c061_device::execute_set_input(int input, int level) case TLCS900_INT0: /* Is INT0 functionality enabled? */ - if ( m_reg[TMP95C061_IIMC] & 0x04 ) + if ( m_iimc & 0x04 ) { - if ( m_reg[TMP95C061_IIMC] & 0x02 ) + if ( m_iimc & 0x02 ) { /* Rising edge detect */ if ( m_level[TLCS900_INT0] == CLEAR_LINE && level == ASSERT_LINE ) { /* Leave HALT state */ m_halted = 0; - m_reg[TMP95C061_INTE0AD] |= 0x08; + m_int_reg[TMP95C061_INTE0AD] |= 0x08; } } else { /* Level detect */ if ( level == ASSERT_LINE ) - m_reg[TMP95C061_INTE0AD] |= 0x08; + m_int_reg[TMP95C061_INTE0AD] |= 0x08; else - m_reg[TMP95C061_INTE0AD] &= ~ 0x08; + m_int_reg[TMP95C061_INTE0AD] &= ~ 0x08; } } m_level[TLCS900_INT0] = level; break; case TLCS900_INT4: - if ( ! ( m_reg[TMP95C061_PBCR] & 0x01 ) ) + if ( ! ( m_port_control[0xb] & 0x01 ) ) { if ( m_level[TLCS900_INT4] == CLEAR_LINE && level == ASSERT_LINE ) { - m_reg[TMP95C061_INTE45] |= 0x08; + m_int_reg[TMP95C061_INTE45] |= 0x08; } } m_level[TLCS900_INT4] = level; break; case TLCS900_INT5: - if ( ! ( m_reg[TMP95C061_PBCR] & 0x02 ) ) + if ( ! ( m_port_control[0xb] & 0x02 ) ) { if ( m_level[TLCS900_INT5] == CLEAR_LINE && level == ASSERT_LINE ) { - m_reg[TMP95C061_INTE45] |= 0x80; + m_int_reg[TMP95C061_INTE45] |= 0x80; } } m_level[TLCS900_INT5] = level; break; case TLCS900_TIO: /* External timer input for timer 0 */ - if ( ( m_reg[TMP95C061_TRUN] & 0x01 ) && ( m_reg[TMP95C061_T01MOD] & 0x03 ) == 0x00 ) + if ( ( m_trun & 0x01 ) && ( m_t8_mode[0] & 0x03 ) == 0x00 ) { if ( m_level[TLCS900_TIO] == CLEAR_LINE && level == ASSERT_LINE ) { @@ -868,155 +865,609 @@ void tmp95c061_device::execute_set_input(int input, int level) } -uint8_t tmp95c061_device::internal_r(offs_t offset) +uint8_t tmp95c061_device::p1_r() { - switch (offset) - { - case TMP95C061_P1: m_reg[offset] = m_port1_read(0); break; - case TMP95C061_P5: m_reg[offset] = m_port5_read(0); break; - case TMP95C061_P6: m_reg[offset] = m_port6_read(0); break; - case TMP95C061_P7: m_reg[offset] = m_port7_read(0); break; - case TMP95C061_P8: m_reg[offset] = m_port8_read(0); break; - case TMP95C061_P9: m_reg[offset] = m_port9_read(0); break; - case TMP95C061_PA: m_reg[offset] = m_porta_read(0); break; - case TMP95C061_PB: m_reg[offset] = m_portb_read(0); break; - } - return m_reg[ offset ]; + return m_port1_read(0); +} + +void tmp95c061_device::p1_w(uint8_t data) +{ + m_port_latch[1] = data; + m_port1_write(0, data, 0xff); +} + +void tmp95c061_device::p1cr_w(uint8_t data) +{ + m_port_control[1] = data; +} + +uint8_t tmp95c061_device::p2_r() +{ + return m_port_latch[2]; +} + +void tmp95c061_device::p2_w(uint8_t data) +{ + m_port_latch[2] = data; + m_port2_write(0, data, 0xff); +} + +void tmp95c061_device::p2fc_w(uint8_t data) +{ + m_port_control[2] = data; +} + +uint8_t tmp95c061_device::p5_r() +{ + return m_port5_read(0); +} + +void tmp95c061_device::p5_w(uint8_t data) +{ + m_port_latch[5] = data; + m_port5_write(0, data, 0xff); +} + +void tmp95c061_device::p5cr_w(uint8_t data) +{ + m_port_control[5] = data; +} + +void tmp95c061_device::p5fc_w(uint8_t data) +{ + m_port_function[5] = data; +} + +uint8_t tmp95c061_device::p6_r() +{ + return m_port6_read(0); +} + +void tmp95c061_device::p6_w(uint8_t data) +{ + m_port_latch[6] = data; + m_port6_write(0, data, 0xff); +} + +void tmp95c061_device::p6fc_w(uint8_t data) +{ + m_port_function[6] = data; +} + +uint8_t tmp95c061_device::p7_r() +{ + return m_port7_read(0); +} + +void tmp95c061_device::p7_w(uint8_t data) +{ + m_port_latch[7] = data; + m_port7_write(0, data, 0xff); +} + +void tmp95c061_device::p7cr_w(uint8_t data) +{ + m_port_control[7] = data; +} + +void tmp95c061_device::p7fc_w(uint8_t data) +{ + m_port_function[7] = data; +} + +uint8_t tmp95c061_device::p8_r() +{ + return m_port8_read(0); +} + +void tmp95c061_device::p8_w(uint8_t data) +{ + m_port_latch[8] = data; + m_port8_write(0, data, 0xff); +} + +void tmp95c061_device::p8cr_w(uint8_t data) +{ + m_port_control[8] = data; +} + +void tmp95c061_device::p8fc_w(uint8_t data) +{ + m_port_function[8] = data; +} + +uint8_t tmp95c061_device::p9_r() +{ + return m_port9_read(0); +} + +uint8_t tmp95c061_device::pa_r() +{ + return m_porta_read(0); +} + +void tmp95c061_device::pa_w(uint8_t data) +{ + m_port_latch[0xa] = data; + update_porta(); } +void tmp95c061_device::pacr_w(uint8_t data) +{ + m_port_control[0xa] = data; + update_porta(); +} + +void tmp95c061_device::pafc_w(uint8_t data) +{ + m_port_function[0xa] = data; + update_porta(); +} void tmp95c061_device::update_porta() { int fc = (m_to1 << 2) | (m_to3 << 3); - m_porta_write(0, ((fc & m_reg[TMP95C061_PAFC]) | (m_reg[TMP95C061_PA] & ~m_reg[TMP95C061_PAFC])) & m_reg[TMP95C061_PACR], 0xff); + m_porta_write(0, ((fc & m_port_function[0xa]) | (m_port_latch[0xa] & ~m_port_function[0xa])) & m_port_control[0xa], 0xff); +} + +uint8_t tmp95c061_device::pb_r() +{ + return m_portb_read(0); +} + +void tmp95c061_device::pb_w(uint8_t data) +{ + m_port_latch[0xb] = data; + m_portb_write(0, data, 0xff); +} + +void tmp95c061_device::pbcr_w(uint8_t data) +{ + m_port_control[0xb] = data; +} + +void tmp95c061_device::pbfc_w(uint8_t data) +{ + m_port_function[0xb] = data; +} + + +uint8_t tmp95c061_device::trun_r() +{ + return m_trun; } -void tmp95c061_device::internal_w(offs_t offset, uint8_t data) +void tmp95c061_device::trun_w(uint8_t data) { - switch ( offset ) + if ( ! ( data & 0x01 ) ) { - case TMP95C061_TRUN: - if ( ! ( data & 0x01 ) ) - { - m_timer[0] = 0; - m_timer_change[0] = 0; - } - if ( ! ( data & 0x02 ) ) - { - m_timer[1] = 0; - m_timer_change[1] = 0; - } - if ( ! ( data & 0x04 ) ) - { - m_timer[2] = 0; - m_timer_change[2] = 0; - } - if ( ! ( data & 0x08 ) ) - { - m_timer[3] = 0; - m_timer_change[3] = 0; - } - if ( ! ( data & 0x10 ) ) - m_timer[4] = 0; - if ( ! ( data & 0x20 ) ) - m_timer[5] = 0; - break; + m_timer[0] = 0; + m_timer_change[0] = 0; + } + if ( ! ( data & 0x02 ) ) + { + m_timer[1] = 0; + m_timer_change[1] = 0; + } + if ( ! ( data & 0x04 ) ) + { + m_timer[2] = 0; + m_timer_change[2] = 0; + } + if ( ! ( data & 0x08 ) ) + { + m_timer[3] = 0; + m_timer_change[3] = 0; + } + if ( ! ( data & 0x10 ) ) + m_timer[4] = 0; + if ( ! ( data & 0x20 ) ) + m_timer[5] = 0; - case TMP95C061_TFFCR: - switch( data & 0x0c ) - { - case 0x00: - tlcs900_change_tff( 1, FF_INVERT ); - break; - case 0x04: - tlcs900_change_tff( 1, FF_SET ); - break; - case 0x08: - tlcs900_change_tff( 1, FF_CLEAR ); - break; - } - switch( data & 0xc0 ) - { - case 0x00: - tlcs900_change_tff( 3, FF_INVERT ); - break; - case 0x40: - tlcs900_change_tff( 3, FF_SET ); - break; - case 0x80: - tlcs900_change_tff( 3, FF_CLEAR ); - break; - } - break; - case TMP95C061_MSAR0: - case TMP95C061_MAMR0: - case TMP95C061_MSAR1: - case TMP95C061_MAMR1: - break; + m_trun = data; +} - case TMP95C061_SC0BUF: - // Fake finish sending data - m_reg[TMP95C061_INTES0] |= 0x80; - break; +void tmp95c061_device::treg01_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset] = data; +} - case TMP95C061_ADMOD: - /* Preserve read-only bits */ - data = ( m_reg[TMP95C061_ADMOD] & 0xc0 ) | ( data & 0x3f ); +void tmp95c061_device::t01mod_w(uint8_t data) +{ + m_t8_mode[0] = data; +} - /* Check for A/D request start */ - if ( data & 0x04 ) - { - data &= ~0x04; - data |= 0x40; - m_ad_cycles_left = ( data & 0x08 ) ? 640 : 320; - } - break; +uint8_t tmp95c061_device::tffcr_r() +{ + return m_t8_invert; +} - case TMP95C061_WDMOD: - case TMP95C061_WDCR: +void tmp95c061_device::tffcr_w(uint8_t data) +{ + switch( data & 0x0c ) + { + case 0x00: + tlcs900_change_tff( 1, FF_INVERT ); break; - - case TMP95C061_INTE0AD: - case TMP95C061_INTE45: - case TMP95C061_INTE67: - case TMP95C061_INTET10: - case TMP95C061_INTET32: - case TMP95C061_INTET54: - case TMP95C061_INTET76: - case TMP95C061_INTES0: - case TMP95C061_INTES1: - case TMP95C061_INTETC10: - case TMP95C061_INTETC32: - if ( data & 0x80 ) - data = ( data & 0x7f ) | ( m_reg[offset] & 0x80 ); - if ( data & 0x08 ) - data = ( data & 0xf7 ) | ( m_reg[offset] & 0x08 ); + case 0x04: + tlcs900_change_tff( 1, FF_SET ); break; - - case TMP95C061_IIMC: + case 0x08: + tlcs900_change_tff( 1, FF_CLEAR ); break; - - default: + } + switch( data & 0xc0 ) + { + case 0x00: + tlcs900_change_tff( 3, FF_INVERT ); + break; + case 0x40: + tlcs900_change_tff( 3, FF_SET ); + break; + case 0x80: + tlcs900_change_tff( 3, FF_CLEAR ); break; } - m_check_irqs = 1; - m_reg[ offset ] = data; + m_t8_invert = data | 0xcc; +} + +void tmp95c061_device::treg23_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset + 2] = data; +} + +void tmp95c061_device::t23mod_w(uint8_t data) +{ + m_t8_mode[1] = data; +} + +uint8_t tmp95c061_device::trdc_r() +{ + return m_trdc; +} + +void tmp95c061_device::trdc_w(uint8_t data) +{ + m_trdc = data; +} + +void tmp95c061_device::treg45_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_t16_reg[offset >> 1] = (m_t16_reg[offset >> 1] & 0x00ff) | uint16_t(data) << 8; + else + m_t16_reg[offset >> 1] = (m_t16_reg[offset >> 1] & 0xff00) | data; +} + +uint8_t tmp95c061_device::cap12_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_t16_cap[offset >> 1] >> 8; + else + return m_t16_cap[offset >> 1] & 0x00ff; +} + +uint8_t tmp95c061_device::t4mod_r() +{ + return m_t16_mode[0]; +} + +void tmp95c061_device::t4mod_w(uint8_t data) +{ + m_t16_mode[0] = data | 0x20; +} - switch(offset) +uint8_t tmp95c061_device::t4ffcr_r() +{ + return m_t16_invert[0]; +} + +void tmp95c061_device::t4ffcr_w(uint8_t data) +{ + m_t16_invert[0] = data | 0xc3; +} + +uint8_t tmp95c061_device::t45cr_r() +{ + return m_t45cr; +} + +void tmp95c061_device::t45cr_w(uint8_t data) +{ + m_t45cr = data; +} + +void tmp95c061_device::treg67_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_t16_reg[(offset >> 1) + 2] = (m_t16_reg[(offset >> 1) + 2] & 0x00ff) | uint16_t(data) << 8; + else + m_t16_reg[(offset >> 1) + 2] = (m_t16_reg[(offset >> 1) + 2] & 0xff00) | data; +} + +uint8_t tmp95c061_device::cap34_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_t16_cap[(offset >> 1) + 2] >> 8; + else + return m_t16_cap[(offset >> 1) + 2] & 0x00ff; +} + +uint8_t tmp95c061_device::t5mod_r() +{ + return m_t16_mode[1]; +} + +void tmp95c061_device::t5mod_w(uint8_t data) +{ + m_t16_mode[1] = data | 0x20; +} + +uint8_t tmp95c061_device::t5ffcr_r() +{ + return m_t16_invert[1]; +} + +void tmp95c061_device::t5ffcr_w(uint8_t data) +{ + m_t16_invert[1] = data | 0xc3; +} + + +uint8_t tmp95c061_device::pgreg_r(offs_t offset) +{ + return m_pgreg[offset]; +} + +void tmp95c061_device::pgreg_w(offs_t offset, uint8_t data) +{ + m_pgreg[offset] = data; +} + +uint8_t tmp95c061_device::pg01cr_r() +{ + return m_pg01cr; +} + +void tmp95c061_device::pg01cr_w(uint8_t data) +{ + m_pg01cr = data; +} + + +uint8_t tmp95c061_device::wdmod_r() +{ + return m_watchdog_mode; +} + +void tmp95c061_device::wdmod_w(uint8_t data) +{ + m_watchdog_mode = data; +} + +void tmp95c061_device::wdcr_w(uint8_t data) +{ +} + + +uint8_t tmp95c061_device::sc0buf_r() +{ + return 0; +} + +void tmp95c061_device::sc0buf_w(uint8_t data) +{ + // Fake finish sending data + m_int_reg[TMP95C061_INTES0] |= 0x80; +} + +uint8_t tmp95c061_device::sc0cr_r() +{ + uint8_t reg = m_serial_control[0]; + if (!machine().side_effects_disabled()) + m_serial_control[0] &= 0xe3; + return reg; +} + +void tmp95c061_device::sc0cr_w(uint8_t data) +{ + m_serial_control[0] = data; +} + +uint8_t tmp95c061_device::sc0mod_r() +{ + return m_serial_mode[0]; +} + +void tmp95c061_device::sc0mod_w(uint8_t data) +{ + m_serial_mode[0] = data; +} + +uint8_t tmp95c061_device::br0cr_r() +{ + return m_baud_rate[0]; +} + +void tmp95c061_device::br0cr_w(uint8_t data) +{ + m_baud_rate[0] = data; +} + +uint8_t tmp95c061_device::sc1buf_r() +{ + return 0; +} + +void tmp95c061_device::sc1buf_w(uint8_t data) +{ + // Fake finish sending data + m_int_reg[TMP95C061_INTES1] |= 0x80; +} + +uint8_t tmp95c061_device::sc1cr_r() +{ + uint8_t reg = m_serial_control[1]; + if (!machine().side_effects_disabled()) + m_serial_control[1] &= 0xe3; + return reg; +} + +void tmp95c061_device::sc1cr_w(uint8_t data) +{ + m_serial_control[1] = data; +} + +uint8_t tmp95c061_device::sc1mod_r() +{ + return m_serial_mode[1]; +} + +void tmp95c061_device::sc1mod_w(uint8_t data) +{ + m_serial_mode[1] = data; +} + +uint8_t tmp95c061_device::br1cr_r() +{ + return m_baud_rate[1]; +} + +void tmp95c061_device::br1cr_w(uint8_t data) +{ + m_baud_rate[1] = data; +} + +uint8_t tmp95c061_device::ode_r() +{ + return m_od_enable; +} + +void tmp95c061_device::ode_w(uint8_t data) +{ + m_od_enable = data; +} + + +uint8_t tmp95c061_device::adreg_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_ad_result[offset >> 1] >> 2; + else + return m_ad_result[offset >> 1] << 6 | 0x3f; +} + +uint8_t tmp95c061_device::admod_r() +{ + return m_ad_mode; +} + +void tmp95c061_device::admod_w(uint8_t data) +{ + // Preserve read-only bits + data = ( m_ad_mode & 0xc0 ) | ( data & 0x3f ); + + // Check for A/D request start */ + if ( data & 0x04 ) { - case TMP95C061_P1: m_port1_write(0, data, 0xff); break; - case TMP95C061_P2: m_port2_write(0, data, 0xff); break; - case TMP95C061_P5: m_port5_write(0, data, 0xff); break; - case TMP95C061_P6: m_port6_write(0, data, 0xff); break; - case TMP95C061_P7: m_port7_write(0, data, 0xff); break; - case TMP95C061_P8: m_port8_write(0, data, 0xff); break; - - case TMP95C061_PA: - case TMP95C061_PACR: - case TMP95C061_PAFC: - update_porta(); - break; + data &= ~0x04; + data |= 0x40; + m_ad_cycles_left = ( data & 0x08 ) ? 640 : 320; } + + m_ad_mode = data; +} + + +uint8_t tmp95c061_device::inte_r(offs_t offset) +{ + return m_int_reg[offset]; +} + +void tmp95c061_device::inte_w(offs_t offset, uint8_t data) +{ + if ( data & 0x80 ) + data = ( data & 0x7f ) | ( m_int_reg[offset] & 0x80 ); + if ( data & 0x08 ) + data = ( data & 0xf7 ) | ( m_int_reg[offset] & 0x08 ); + + m_int_reg[offset] = data; + m_check_irqs = 1; +} + +void tmp95c061_device::iimc_w(uint8_t data) +{ + m_iimc = data; + m_check_irqs = 1; +} + +void tmp95c061_device::dmav_w(offs_t offset, uint8_t data) +{ + m_dma_vector[offset] = data; +} + + +void tmp95c061_device::bcs_w(offs_t offset, uint8_t data) +{ + m_block_cs[offset] = data; +} + +void tmp95c061_device::bexcs_w(uint8_t data) +{ + m_external_cs = data; +} + +uint8_t tmp95c061_device::msar01_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_mem_start_mask[offset >> 1]; + else + return m_mem_start_reg[offset >> 1]; +} + +void tmp95c061_device::msar01_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_mem_start_mask[offset >> 1] = data; + else + m_mem_start_reg[offset >> 1] = data; +} + +uint8_t tmp95c061_device::msar23_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_mem_start_mask[(offset >> 1) + 2]; + else + return m_mem_start_reg[(offset >> 1) + 2]; +} + +void tmp95c061_device::msar23_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_mem_start_mask[(offset >> 1) + 2] = data; + else + m_mem_start_reg[(offset >> 1) + 2] = data; +} + + +uint8_t tmp95c061_device::drefcr_r() +{ + return m_dram_refresh; +} + +void tmp95c061_device::drefcr_w(uint8_t data) +{ + m_dram_refresh = data; +} + +uint8_t tmp95c061_device::dmemcr_r() +{ + return m_dram_access; +} + +void tmp95c061_device::dmemcr_w(uint8_t data) +{ + m_dram_access = data; } diff --git a/src/devices/cpu/tlcs900/tmp95c061.h b/src/devices/cpu/tlcs900/tmp95c061.h index bb10853dadd..10d8193f6e6 100644 --- a/src/devices/cpu/tlcs900/tmp95c061.h +++ b/src/devices/cpu/tlcs900/tmp95c061.h @@ -50,14 +50,105 @@ protected: void update_porta(); private: - uint8_t internal_r(offs_t offset); - void internal_w(offs_t offset, uint8_t data); + uint8_t p1_r(); + void p1_w(uint8_t data); + void p1cr_w(uint8_t data); + uint8_t p2_r(); + void p2_w(uint8_t data); + void p2fc_w(uint8_t data); + uint8_t p5_r(); + void p5_w(uint8_t data); + void p5cr_w(uint8_t data); + void p5fc_w(uint8_t data); + uint8_t p6_r(); + void p6_w(uint8_t data); + void p6fc_w(uint8_t data); + uint8_t p7_r(); + void p7_w(uint8_t data); + void p7cr_w(uint8_t data); + void p7fc_w(uint8_t data); + uint8_t p8_r(); + void p8_w(uint8_t data); + void p8cr_w(uint8_t data); + void p8fc_w(uint8_t data); + uint8_t p9_r(); + uint8_t pa_r(); + void pa_w(uint8_t data); + void pacr_w(uint8_t data); + void pafc_w(uint8_t data); + uint8_t pb_r(); + void pb_w(uint8_t data); + void pbcr_w(uint8_t data); + void pbfc_w(uint8_t data); + uint8_t trun_r(); + void trun_w(uint8_t data); + void treg01_w(offs_t offset, uint8_t data); + void t01mod_w(uint8_t data); + uint8_t tffcr_r(); + void tffcr_w(uint8_t data); + void treg23_w(offs_t offset, uint8_t data); + void t23mod_w(uint8_t data); + uint8_t trdc_r(); + void trdc_w(uint8_t data); + void treg45_w(offs_t offset, uint8_t data); + uint8_t cap12_r(offs_t offset); + uint8_t t4mod_r(); + void t4mod_w(uint8_t data); + uint8_t t4ffcr_r(); + void t4ffcr_w(uint8_t data); + uint8_t t45cr_r(); + void t45cr_w(uint8_t data); + void treg67_w(offs_t offset, uint8_t data); + uint8_t cap34_r(offs_t offset); + uint8_t t5mod_r(); + void t5mod_w(uint8_t data); + uint8_t t5ffcr_r(); + void t5ffcr_w(uint8_t data); + uint8_t pgreg_r(offs_t offset); + void pgreg_w(offs_t offset, uint8_t data); + uint8_t pg01cr_r(); + void pg01cr_w(uint8_t data); + uint8_t wdmod_r(); + void wdmod_w(uint8_t data); + void wdcr_w(uint8_t data); + uint8_t sc0buf_r(); + void sc0buf_w(uint8_t data); + uint8_t sc0cr_r(); + void sc0cr_w(uint8_t data); + uint8_t sc0mod_r(); + void sc0mod_w(uint8_t data); + uint8_t br0cr_r(); + void br0cr_w(uint8_t data); + uint8_t sc1buf_r(); + void sc1buf_w(uint8_t data); + uint8_t sc1cr_r(); + void sc1cr_w(uint8_t data); + uint8_t sc1mod_r(); + void sc1mod_w(uint8_t data); + uint8_t br1cr_r(); + void br1cr_w(uint8_t data); + uint8_t ode_r(); + void ode_w(uint8_t data); + uint8_t adreg_r(offs_t offset); + uint8_t admod_r(); + void admod_w(uint8_t data); + uint8_t inte_r(offs_t offset); + void inte_w(offs_t offset, uint8_t data); + void iimc_w(uint8_t data); + void dmav_w(offs_t offset, uint8_t data); + void bcs_w(offs_t offset, uint8_t data); + void bexcs_w(uint8_t data); + uint8_t msar01_r(offs_t offset); + void msar01_w(offs_t offset, uint8_t data); + uint8_t msar23_r(offs_t offset); + void msar23_w(offs_t offset, uint8_t data); + uint8_t drefcr_r(); + void drefcr_w(uint8_t data); + uint8_t dmemcr_r(); + void dmemcr_w(uint8_t data); void internal_mem(address_map &map); - uint8_t m_to1; - uint8_t m_to3; - // Port 1: 8 bit I/O. Shared with D8-D15 devcb_read8 m_port1_read; devcb_write8 m_port1_write; @@ -91,6 +182,57 @@ private: // Port B: 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6 devcb_read8 m_portb_read; devcb_write8 m_portb_write; + + // I/O Port Control + uint8_t m_port_latch[0xc]; + uint8_t m_port_control[0xc]; + uint8_t m_port_function[0xc]; + + // Timer Control + uint8_t m_trun; + uint8_t m_t8_reg[4]; + uint8_t m_t8_mode[2]; + uint8_t m_t8_invert; + uint8_t m_trdc; + uint8_t m_to1; + uint8_t m_to3; + uint16_t m_t16_reg[4]; + uint16_t m_t16_cap[4]; + uint8_t m_t16_mode[2]; + uint8_t m_t16_invert[2]; + uint8_t m_t45cr; + + // Pattern Generator + uint8_t m_pgreg[2]; + uint8_t m_pg01cr; + + // Watchdog Timer + uint8_t m_watchdog_mode; + + // Serial Channel + uint8_t m_serial_control[2]; + uint8_t m_serial_mode[2]; + uint8_t m_baud_rate[2]; + uint8_t m_od_enable; + + // A/D Converter Control + uint16_t m_ad_result[4]; + uint8_t m_ad_mode; + + // Interrupt Control + uint8_t m_int_reg[0xb]; + uint8_t m_iimc; + uint8_t m_dma_vector[4]; + + // Chip Select/Wait Control + uint8_t m_block_cs[4]; + uint8_t m_external_cs; + uint8_t m_mem_start_reg[4]; + uint8_t m_mem_start_mask[4]; + + // DRAM Control + uint8_t m_dram_refresh; + uint8_t m_dram_access; }; #endif // MAME_CPU_TLCS900_TMP95C061_H diff --git a/src/devices/cpu/tlcs900/tmp95c063.cpp b/src/devices/cpu/tlcs900/tmp95c063.cpp index 0bede30f7a2..d3ea2e08113 100644 --- a/src/devices/cpu/tlcs900/tmp95c063.cpp +++ b/src/devices/cpu/tlcs900/tmp95c063.cpp @@ -36,13 +36,126 @@ tmp95c063_device::tmp95c063_device(const machine_config &mconfig, const char *ta m_portd_write(*this), m_porte_read(*this), m_porte_write(*this), - m_an_read(*this) + m_an_read(*this), + m_port_latch{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_port_control{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_port_function{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_t8run(0), + m_t8_reg{ 0, 0, 0, 0, 0, 0, 0, 0 }, + m_t8_mode{ 0, 0, 0, 0 }, + m_t8_invert{ 0, 0 }, + m_trdc(0), + m_t16_reg{ 0, 0, 0, 0 }, + m_t16_cap{ 0, 0, 0, 0 }, + m_t16_mode{ 0, 0 }, + m_t16_invert{ 0, 0 }, + m_t89cr(0), + m_t16run(0), + m_pgreg{ 0, 0 }, + m_pg01cr(0), + m_watchdog_mode(0), + m_serial_control{ 0, 0 }, + m_serial_mode{ 0, 0 }, + m_baud_rate{ 0, 0 }, + m_od_enable(0), + m_ad_mode1(0), + m_ad_mode2(0), + m_ad_result{ 0, 0, 0, 0 }, + m_int_reg{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + m_iimc(0), + m_dma_vector{ 0, 0, 0, 0 }, + m_block_cs{ 0, 0, 0, 0 }, + m_external_cs(0), + m_mem_start_reg{ 0, 0, 0, 0 }, + m_mem_start_mask{ 0, 0, 0, 0 }, + m_dram_refresh{ 0, 0 }, + m_dram_access{ 0, 0 }, + m_da_drive(0) { } void tmp95c063_device::internal_mem(address_map &map) { - map(0x000000, 0x00009f).rw(FUNC(tmp95c063_device::internal_r), FUNC(tmp95c063_device::internal_w)); + map(0x000001, 0x000001).rw(FUNC(tmp95c063_device::p1_r), FUNC(tmp95c063_device::p1_w)); + map(0x000004, 0x000004).w(FUNC(tmp95c063_device::p1cr_w)); + map(0x000006, 0x000006).rw(FUNC(tmp95c063_device::p2_r), FUNC(tmp95c063_device::p2_w)); + map(0x000009, 0x000009).w(FUNC(tmp95c063_device::p2fc_w)); + map(0x00000d, 0x00000d).rw(FUNC(tmp95c063_device::p5_r), FUNC(tmp95c063_device::p5_w)); + map(0x000010, 0x000010).w(FUNC(tmp95c063_device::p5cr_w)); + map(0x000011, 0x000011).w(FUNC(tmp95c063_device::p5fc_w)); + map(0x000012, 0x000012).rw(FUNC(tmp95c063_device::p6_r), FUNC(tmp95c063_device::p6_w)); + map(0x000013, 0x000013).rw(FUNC(tmp95c063_device::p7_r), FUNC(tmp95c063_device::p7_w)); + map(0x000015, 0x000015).w(FUNC(tmp95c063_device::p6fc_w)); + map(0x000016, 0x000016).w(FUNC(tmp95c063_device::p7cr_w)); + map(0x000017, 0x000017).w(FUNC(tmp95c063_device::p7fc_w)); + map(0x000018, 0x000018).rw(FUNC(tmp95c063_device::p8_r), FUNC(tmp95c063_device::p8_w)); + map(0x000019, 0x000019).rw(FUNC(tmp95c063_device::p9_r), FUNC(tmp95c063_device::p9_w)); + map(0x00001a, 0x00001a).w(FUNC(tmp95c063_device::p8cr_w)); + map(0x00001b, 0x00001b).w(FUNC(tmp95c063_device::p8fc_w)); + map(0x00001c, 0x00001c).w(FUNC(tmp95c063_device::p9cr_w)); + map(0x00001d, 0x00001d).w(FUNC(tmp95c063_device::p9fc_w)); + map(0x00001e, 0x00001e).rw(FUNC(tmp95c063_device::pa_r), FUNC(tmp95c063_device::pa_w)); + map(0x00001f, 0x00001f).rw(FUNC(tmp95c063_device::pb_r), FUNC(tmp95c063_device::pb_w)); + map(0x000020, 0x000020).rw(FUNC(tmp95c063_device::t8run_r), FUNC(tmp95c063_device::t8run_w)); + map(0x000021, 0x000021).rw(FUNC(tmp95c063_device::trdc_r), FUNC(tmp95c063_device::trdc_w)); + map(0x000022, 0x000023).w(FUNC(tmp95c063_device::treg01_w)); + map(0x000024, 0x000024).rw(FUNC(tmp95c063_device::t01mod_r), FUNC(tmp95c063_device::t01mod_w)); + map(0x000025, 0x000025).rw(FUNC(tmp95c063_device::t02ffcr_r), FUNC(tmp95c063_device::t02ffcr_w)); + map(0x000026, 0x000027).w(FUNC(tmp95c063_device::treg23_w)); + map(0x000028, 0x000028).rw(FUNC(tmp95c063_device::t23mod_r), FUNC(tmp95c063_device::t23mod_w)); + map(0x000029, 0x00002a).w(FUNC(tmp95c063_device::treg45_w)); + map(0x00002b, 0x00002b).rw(FUNC(tmp95c063_device::t45mod_r), FUNC(tmp95c063_device::t45mod_w)); + map(0x00002c, 0x00002c).rw(FUNC(tmp95c063_device::t46ffcr_r), FUNC(tmp95c063_device::t46ffcr_w)); + map(0x00002d, 0x00002e).w(FUNC(tmp95c063_device::treg67_w)); + map(0x00002f, 0x00002f).rw(FUNC(tmp95c063_device::t67mod_r), FUNC(tmp95c063_device::t67mod_w)); + map(0x000030, 0x000033).w(FUNC(tmp95c063_device::treg89_w)); + map(0x000034, 0x000037).r(FUNC(tmp95c063_device::cap12_r)); + map(0x000038, 0x000038).rw(FUNC(tmp95c063_device::t8mod_r), FUNC(tmp95c063_device::t8mod_w)); + map(0x000039, 0x000039).rw(FUNC(tmp95c063_device::t8ffcr_r), FUNC(tmp95c063_device::t8ffcr_w)); + map(0x00003a, 0x00003a).rw(FUNC(tmp95c063_device::t89cr_r), FUNC(tmp95c063_device::t89cr_w)); + map(0x00003b, 0x00003b).rw(FUNC(tmp95c063_device::t16run_r), FUNC(tmp95c063_device::t16run_w)); + map(0x000040, 0x000043).w(FUNC(tmp95c063_device::tregab_w)); + map(0x000044, 0x000047).r(FUNC(tmp95c063_device::cap34_r)); + map(0x000048, 0x000048).rw(FUNC(tmp95c063_device::t9mod_r), FUNC(tmp95c063_device::t9mod_w)); + map(0x000049, 0x000049).rw(FUNC(tmp95c063_device::t9ffcr_r), FUNC(tmp95c063_device::t9ffcr_w)); + map(0x00004a, 0x00004b).w(FUNC(tmp95c063_device::dareg_w)); + map(0x00004c, 0x00004d).rw(FUNC(tmp95c063_device::pgreg_r), FUNC(tmp95c063_device::pgreg_w)); + map(0x00004e, 0x00004e).rw(FUNC(tmp95c063_device::pg01cr_r), FUNC(tmp95c063_device::pg01cr_w)); + map(0x00004f, 0x00004f).rw(FUNC(tmp95c063_device::dadrv_r), FUNC(tmp95c063_device::dadrv_w)); + map(0x000050, 0x000050).rw(FUNC(tmp95c063_device::sc0buf_r), FUNC(tmp95c063_device::sc0buf_w)); + map(0x000051, 0x000051).rw(FUNC(tmp95c063_device::sc0cr_r), FUNC(tmp95c063_device::sc0cr_w)); + map(0x000052, 0x000052).rw(FUNC(tmp95c063_device::sc0mod_r), FUNC(tmp95c063_device::sc0mod_w)); + map(0x000053, 0x000053).rw(FUNC(tmp95c063_device::br0cr_r), FUNC(tmp95c063_device::br0cr_w)); + map(0x000054, 0x000054).rw(FUNC(tmp95c063_device::sc1buf_r), FUNC(tmp95c063_device::sc1buf_w)); + map(0x000055, 0x000055).rw(FUNC(tmp95c063_device::sc1cr_r), FUNC(tmp95c063_device::sc1cr_w)); + map(0x000056, 0x000056).rw(FUNC(tmp95c063_device::sc1mod_r), FUNC(tmp95c063_device::sc1mod_w)); + map(0x000057, 0x000057).rw(FUNC(tmp95c063_device::br1cr_r), FUNC(tmp95c063_device::br1cr_w)); + map(0x000058, 0x000058).rw(FUNC(tmp95c063_device::ode_r), FUNC(tmp95c063_device::ode_w)); + map(0x00005a, 0x00005d).w(FUNC(tmp95c063_device::dmav_w)); + map(0x00005e, 0x00005e).rw(FUNC(tmp95c063_device::admod1_r), FUNC(tmp95c063_device::admod1_w)); + map(0x00005f, 0x00005f).rw(FUNC(tmp95c063_device::admod2_r), FUNC(tmp95c063_device::admod2_w)); + map(0x000060, 0x000067).r(FUNC(tmp95c063_device::adreg_r)); + //map(0x00006a, 0x00006d).rw(FUNC(tmp95c063_device::sdmacr_r), FUNC(tmp95c063_device::sdmacr_w)); + map(0x00006e, 0x00006e).rw(FUNC(tmp95c063_device::wdmod_r), FUNC(tmp95c063_device::wdmod_w)); + map(0x00006f, 0x00006f).w(FUNC(tmp95c063_device::wdcr_w)); + map(0x000070, 0x00007e).rw(FUNC(tmp95c063_device::inte_r), FUNC(tmp95c063_device::inte_w)); + map(0x00007f, 0x00007f).w(FUNC(tmp95c063_device::iimc_w)); + map(0x000080, 0x000080).w(FUNC(tmp95c063_device::pacr_w)); + map(0x000081, 0x000081).w(FUNC(tmp95c063_device::pafc_w)); + map(0x000082, 0x000082).w(FUNC(tmp95c063_device::pbcr_w)); + map(0x000083, 0x000083).w(FUNC(tmp95c063_device::pbfc_w)); + map(0x000084, 0x000084).r(FUNC(tmp95c063_device::pc_r)); + map(0x000085, 0x000085).rw(FUNC(tmp95c063_device::pd_r), FUNC(tmp95c063_device::pd_w)); + map(0x000088, 0x000088).w(FUNC(tmp95c063_device::pdcr_w)); + map(0x00008a, 0x00008a).rw(FUNC(tmp95c063_device::pe_r), FUNC(tmp95c063_device::pe_w)); + map(0x00008c, 0x00008c).w(FUNC(tmp95c063_device::pecr_w)); + map(0x00008f, 0x00008f).w(FUNC(tmp95c063_device::bexcs_w)); + map(0x000090, 0x000093).w(FUNC(tmp95c063_device::bcs_w)); + map(0x000094, 0x00009b).rw(FUNC(tmp95c063_device::msar_r), FUNC(tmp95c063_device::msar_w)); + map(0x00009c, 0x00009c).rw(FUNC(tmp95c063_device::drefcr1_r), FUNC(tmp95c063_device::drefcr1_w)); + map(0x00009d, 0x00009d).rw(FUNC(tmp95c063_device::dmemcr1_r), FUNC(tmp95c063_device::dmemcr1_w)); + map(0x00009e, 0x00009e).rw(FUNC(tmp95c063_device::drefcr3_r), FUNC(tmp95c063_device::drefcr3_w)); + map(0x00009f, 0x00009f).rw(FUNC(tmp95c063_device::dmemcr3_r), FUNC(tmp95c063_device::dmemcr3_w)); } //------------------------------------------------- @@ -64,143 +177,22 @@ void tmp95c063_device::device_config_complete() } -/* TMP95C063 Internal register defines */ - -#define TMP95C063_P1 0x01 -#define TMP95C063_P1CR 0x04 -#define TMP95C063_P2 0x06 -#define TMP95C063_P2FC 0x09 -#define TMP95C063_P5 0x0d -#define TMP95C063_P5CR 0x10 -#define TMP95C063_P5FC 0x11 -#define TMP95C063_P6 0x12 -#define TMP95C063_P7 0x13 -#define TMP95C063_P6FC 0x15 -#define TMP95C063_P7CR 0x16 -#define TMP95C063_P7FC 0x17 -#define TMP95C063_P8 0x18 -#define TMP95C063_P9 0x19 -#define TMP95C063_P8CR 0x1a -#define TMP95C063_P8FC 0x1b -#define TMP95C063_P9CR 0x1c -#define TMP95C063_P9FC 0x1d -#define TMP95C063_PA 0x1e -#define TMP95C063_PB 0x1f -#define TMP95C063_T8RUN 0x20 -#define TMP95C063_TRDC 0x21 -#define TMP95C063_TREG0 0x22 -#define TMP95C063_TREG1 0x23 -#define TMP95C063_T01MOD 0x24 -#define TMP95C063_T02FFCR 0x25 -#define TMP95C063_TREG2 0x26 -#define TMP95C063_TREG3 0x27 -#define TMP95C063_T23MOD 0x28 -#define TMP95C063_TREG4 0x29 -#define TMP95C063_TREG5 0x2a -#define TMP95C063_T45MOD 0x2b -#define TMP95C063_T46FFCR 0x2c -#define TMP95C063_TREG6 0x2d -#define TMP95C063_TREG7 0x2e -#define TMP95C063_T67MOD 0x2f -#define TMP95C063_TREG8L 0x30 -#define TMP95C063_TREG8H 0x31 -#define TMP95C063_TREG9L 0x32 -#define TMP95C063_TREG9H 0x33 -#define TMP95C063_CAP1L 0x34 -#define TMP95C063_CAP1H 0x35 -#define TMP95C063_CAP2L 0x36 -#define TMP95C063_CAP2H 0x37 -#define TMP95C063_T8MOD 0x38 -#define TMP95C063_T8FFCR 0x39 -#define TMP95C063_T89CR 0x3a -#define TMP95C063_T16RUN 0x3b -#define TMP95C063_TREGAL 0x40 -#define TMP95C063_TREGAH 0x41 -#define TMP95C063_TREGBL 0x42 -#define TMP95C063_TREGBH 0x43 -#define TMP95C063_CAP3L 0x44 -#define TMP95C063_CAP3H 0x45 -#define TMP95C063_CAP4L 0x46 -#define TMP95C063_CAP4H 0x47 -#define TMP95C063_T9MOD 0x48 -#define TMP95C063_T9FFCR 0x49 -#define TMP95C063_DAREG0 0x4a -#define TMP95C063_DAREG1 0x4b -#define TMP95C063_PG0REG 0x4c -#define TMP95C063_PG1REG 0x4d -#define TMP95C063_PG01CR 0x4e -#define TMP95C063_DADRV 0x4f -#define TMP95C063_SC0BUF 0x50 -#define TMP95C063_SC0CR 0x51 -#define TMP95C063_SC0MOD 0x52 -#define TMP95C063_BR0CR 0x53 -#define TMP95C063_SC1BUF 0x54 -#define TMP95C063_SC1CR 0x55 -#define TMP95C063_SC1MOD 0x56 -#define TMP95C063_BR1CR 0x57 -#define TMP95C063_ODE 0x58 -#define TMP95C063_DMA0V 0x5a -#define TMP95C063_DMA1V 0x5b -#define TMP95C063_DMA2V 0x5c -#define TMP95C063_DMA3V 0x5d -#define TMP95C063_ADMOD1 0x5e -#define TMP95C063_ADMOD2 0x5f -#define TMP95C063_ADREG04L 0x60 -#define TMP95C063_ADREG04H 0x61 -#define TMP95C063_ADREG15L 0x62 -#define TMP95C063_ADREG15H 0x63 -#define TMP95C063_ADREG26L 0x64 -#define TMP95C063_ADREG26H 0x65 -#define TMP95C063_ADREG37L 0x66 -#define TMP95C063_ADREG37H 0x67 -#define TMP95C063_SDMACR0 0x6a -#define TMP95C063_SDMACR1 0x6b -#define TMP95C063_SDMACR2 0x6c -#define TMP95C063_SDMACR3 0x6d -#define TMP95C063_WDMOD 0x6e -#define TMP95C063_WDCR 0x6f -#define TMP95C063_INTE0AD 0x70 -#define TMP95C063_INTE12 0x71 -#define TMP95C063_INTE34 0x72 -#define TMP95C063_INTE56 0x73 -#define TMP95C063_INTE78 0x74 -#define TMP95C063_INTET01 0x75 -#define TMP95C063_INTET23 0x76 -#define TMP95C063_INTET45 0x77 -#define TMP95C063_INTET67 0x78 -#define TMP95C063_INTET89 0x79 -#define TMP95C063_INTETAB 0x7a -#define TMP95C063_INTES0 0x7b -#define TMP95C063_INTES1 0x7c -#define TMP95C063_INTETC01 0x7d -#define TMP95C063_INTETC23 0x7e -#define TMP95C063_IIMC 0x7f -#define TMP95C063_PACR 0x80 -#define TMP95C063_PAFC 0x81 -#define TMP95C063_PBCR 0x82 -#define TMP95C063_PBFC 0x83 -#define TMP95C063_PC 0x84 -#define TMP95C063_PD 0x85 -#define TMP95C063_PDCR 0x88 -#define TMP95C063_PE 0x8a -#define TMP95C063_PECR 0x8c -#define TMP95C063_BEXCS 0x8f -#define TMP95C063_B0CS 0x90 -#define TMP95C063_B1CS 0x91 -#define TMP95C063_B2CS 0x92 -#define TMP95C063_B3CS 0x93 -#define TMP95C063_MSAR0 0x94 -#define TMP95C063_MAMR0 0x95 -#define TMP95C063_MSAR1 0x96 -#define TMP95C063_MAMR1 0x97 -#define TMP95C063_MSAR2 0x98 -#define TMP95C063_MAMR2 0x99 -#define TMP95C063_MSAR3 0x9a -#define TMP95C063_MAMR3 0x9b -#define TMP95C063_DREFCR1 0x9c -#define TMP95C063_DMEMCR1 0x9d -#define TMP95C063_DREFCR3 0x9e -#define TMP95C063_DMEMCR3 0x9f + +#define TMP95C063_INTE0AD 0x0 +#define TMP95C063_INTE12 0x1 +#define TMP95C063_INTE34 0x2 +#define TMP95C063_INTE56 0x3 +#define TMP95C063_INTE78 0x4 +#define TMP95C063_INTET01 0x5 +#define TMP95C063_INTET23 0x6 +#define TMP95C063_INTET45 0x7 +#define TMP95C063_INTET67 0x8 +#define TMP95C063_INTET89 0x9 +#define TMP95C063_INTETAB 0xa +#define TMP95C063_INTES0 0xb +#define TMP95C063_INTES1 0xc +#define TMP95C063_INTETC01 0xd +#define TMP95C063_INTETC23 0xe #define TMP95C063_NUM_MASKABLE_IRQS 30 @@ -250,13 +242,13 @@ void tmp95c063_device::tlcs900_handle_timers() uint32_t old_pre = m_timer_pre; /* Is the pre-scaler active */ - if ( m_reg[TMP95C063_T8RUN] & 0x80 ) + if ( m_t8run & 0x80 ) m_timer_pre += m_cycles; /* Timer 0 */ - if ( m_reg[TMP95C063_T8RUN] & 0x01 ) + if ( m_t8run & 0x01 ) { - switch( m_reg[TMP95C063_T01MOD] & 0x03 ) + switch( m_t8_mode[0] & 0x03 ) { case 0x00: /* TIO */ break; @@ -273,29 +265,28 @@ void tmp95c063_device::tlcs900_handle_timers() for( ; m_timer_change[0] > 0; m_timer_change[0]-- ) { -//printf("timer0 = %02x, TREG0 = %02x\n", m_timer[0], m_reg[TREG0] ); m_timer[0] += 1; - if ( m_timer[0] == m_reg[TMP95C063_TREG0] ) + if ( m_timer[0] == m_t8_reg[0] ) { - if ( ( m_reg[TMP95C063_T01MOD] & 0x0c ) == 0x00 ) + if ( ( m_t8_mode[0] & 0x0c ) == 0x00 ) { m_timer_change[1] += 1; } /* In 16bit timer mode the timer should not be reset */ - if ( ( m_reg[TMP95C063_T01MOD] & 0xc0 ) != 0x40 ) + if ( ( m_t8_mode[0] & 0xc0 ) != 0x40 ) { m_timer[0] = 0; - m_reg[TMP95C063_INTET01] |= 0x08; + m_int_reg[TMP95C063_INTET01] |= 0x08; } } } } /* Timer 1 */ - if ( m_reg[TMP95C063_T8RUN] & 0x02 ) + if ( m_t8run & 0x02 ) { - switch( ( m_reg[TMP95C063_T01MOD] >> 2 ) & 0x03 ) + switch( ( m_t8_mode[0] >> 2 ) & 0x03 ) { case 0x00: /* TO0TRG */ break; @@ -313,18 +304,18 @@ void tmp95c063_device::tlcs900_handle_timers() for( ; m_timer_change[1] > 0; m_timer_change[1]-- ) { m_timer[1] += 1; - if ( m_timer[1] == m_reg[TMP95C063_TREG1] ) + if ( m_timer[1] == m_t8_reg[1] ) { m_timer[1] = 0; - m_reg[TMP95C063_INTET01] |= 0x80; + m_int_reg[TMP95C063_INTET01] |= 0x80; - if ( m_reg[TMP95C063_T02FFCR] & 0x02 ) + if ( m_t8_invert[0] & 0x02 ) { //tlcs900_change_tff( 1, FF_INVERT ); } /* In 16bit timer mode also reset timer 0 */ - if ( ( m_reg[TMP95C063_T01MOD] & 0xc0 ) == 0x40 ) + if ( ( m_t8_mode[0] & 0xc0 ) == 0x40 ) { m_timer[0] = 0; } @@ -333,9 +324,9 @@ void tmp95c063_device::tlcs900_handle_timers() } /* Timer 2 */ - if ( m_reg[TMP95C063_T8RUN] & 0x04 ) + if ( m_t8run & 0x04 ) { - switch( m_reg[TMP95C063_T23MOD] & 0x03 ) + switch( m_t8_mode[1] & 0x03 ) { case 0x00: /* invalid */ case 0x01: /* T1 */ @@ -352,27 +343,27 @@ void tmp95c063_device::tlcs900_handle_timers() for( ; m_timer_change[2] > 0; m_timer_change[2]-- ) { m_timer[2] += 1; - if ( m_timer[2] == m_reg[TMP95C063_TREG2] ) + if ( m_timer[2] == m_t8_reg[2] ) { - if ( ( m_reg[TMP95C063_T23MOD] & 0x0c ) == 0x00 ) + if ( ( m_t8_mode[1] & 0x0c ) == 0x00 ) { m_timer_change[3] += 1; } /* In 16bit timer mode the timer should not be reset */ - if ( ( m_reg[TMP95C063_T23MOD] & 0xc0 ) != 0x40 ) + if ( ( m_t8_mode[1] & 0xc0 ) != 0x40 ) { m_timer[2] = 0; - m_reg[TMP95C063_INTET23] |= 0x08; + m_int_reg[TMP95C063_INTET23] |= 0x08; } } } } /* Timer 3 */ - if ( m_reg[TMP95C063_T8RUN] & 0x08 ) + if ( m_t8run & 0x08 ) { - switch( ( m_reg[TMP95C063_T23MOD] >> 2 ) & 0x03 ) + switch( ( m_t8_mode[1] >> 2 ) & 0x03 ) { case 0x00: /* TO2TRG */ break; @@ -390,18 +381,18 @@ void tmp95c063_device::tlcs900_handle_timers() for( ; m_timer_change[3] > 0; m_timer_change[3]-- ) { m_timer[3] += 1; - if ( m_timer[3] == m_reg[TMP95C063_TREG3] ) + if ( m_timer[3] == m_t8_reg[3] ) { m_timer[3] = 0; - m_reg[TMP95C063_INTET23] |= 0x80; + m_int_reg[TMP95C063_INTET23] |= 0x80; - if ( m_reg[TMP95C063_T02FFCR] & 0x20 ) + if ( m_t8_invert[1] & 0x20 ) { //tlcs900_change_tff( 3, FF_INVERT ); } /* In 16bit timer mode also reset timer 2 */ - if ( ( m_reg[TMP95C063_T23MOD] & 0xc0 ) == 0x40 ) + if ( ( m_t8_mode[1] & 0xc0 ) == 0x40 ) { m_timer[2] = 0; } @@ -445,15 +436,15 @@ void tmp95c063_device::tlcs900_check_irqs() /* Check regular irqs */ for( i = 0; i < TMP95C063_NUM_MASKABLE_IRQS; i++ ) { - if ( m_reg[tmp95c063_irq_vector_map[i].reg] & tmp95c063_irq_vector_map[i].iff ) + if ( m_int_reg[tmp95c063_irq_vector_map[i].reg] & tmp95c063_irq_vector_map[i].iff ) { switch( tmp95c063_irq_vector_map[i].iff ) { case 0x80: - irq_vectors[ ( m_reg[ tmp95c063_irq_vector_map[i].reg ] >> 4 ) & 0x07 ] = i; + irq_vectors[ ( m_int_reg[ tmp95c063_irq_vector_map[i].reg ] >> 4 ) & 0x07 ] = i; break; case 0x08: - irq_vectors[ m_reg[ tmp95c063_irq_vector_map[i].reg ] & 0x07 ] = i; + irq_vectors[ m_int_reg[ tmp95c063_irq_vector_map[i].reg ] & 0x07 ] = i; break; } } @@ -489,7 +480,7 @@ void tmp95c063_device::tlcs900_check_irqs() m_halted = 0; /* Clear taken IRQ */ - m_reg[ tmp95c063_irq_vector_map[irq].reg ] &= ~ tmp95c063_irq_vector_map[irq].iff; + m_int_reg[ tmp95c063_irq_vector_map[irq].reg ] &= ~ tmp95c063_irq_vector_map[irq].iff; } } @@ -501,143 +492,59 @@ void tmp95c063_device::tlcs900_handle_ad() m_ad_cycles_left -= m_cycles; if ( m_ad_cycles_left <= 0 ) { - int ad_value; - /* Store A/D converted value */ - if ((m_reg[TMP95C063_ADMOD1] & 0x10) == 0) // conversion channel fixed + if ((m_ad_mode1 & 0x10) == 0) // conversion channel fixed { - switch( m_reg[TMP95C063_ADMOD2] & 0x07 ) - { - case 0x00: // AN0 - ad_value = m_an_read[0](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - break; - case 0x01: // AN1 - ad_value = m_an_read[1](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - break; - case 0x02: // AN2 - ad_value = m_an_read[2](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; - break; - case 0x03: // AN3 - ad_value = m_an_read[3](0) & 0x3ff; - m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; - break; - case 0x04: // AN4 - ad_value = m_an_read[4](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - break; - case 0x05: // AN5 - ad_value = m_an_read[5](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - break; - case 0x06: // AN6 - ad_value = m_an_read[6](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; - break; - case 0x07: // AN7 - ad_value = m_an_read[7](0) & 0x3ff; - m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; - break; - } + m_ad_result[m_ad_mode2 & 0x03] = m_an_read[m_ad_mode2 & 0x07](0) & 0x3ff; } else // conversion channel sweep { - switch( m_reg[TMP95C063_ADMOD2] & 0x07 ) + switch( m_ad_mode2 & 0x07 ) { case 0x00: // AN0 - ad_value = m_an_read[0](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[0](0) & 0x3ff; break; case 0x01: // AN0 -> AN1 - ad_value = m_an_read[0](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[1](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[0](0) & 0x3ff; + m_ad_result[1] = m_an_read[1](0) & 0x3ff; break; case 0x02: // AN0 -> AN1 -> AN2 - ad_value = m_an_read[0](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[1](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[2](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[0](0) & 0x3ff; + m_ad_result[1] = m_an_read[1](0) & 0x3ff; + m_ad_result[2] = m_an_read[2](0) & 0x3ff; break; case 0x03: // AN0 -> AN1 -> AN2 -> AN3 - ad_value = m_an_read[0](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[1](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[2](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[3](0) & 0x3ff; - m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[0](0) & 0x3ff; + m_ad_result[1] = m_an_read[1](0) & 0x3ff; + m_ad_result[2] = m_an_read[2](0) & 0x3ff; + m_ad_result[3] = m_an_read[3](0) & 0x3ff; break; case 0x04: // AN4 - ad_value = m_an_read[4](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[4](0) & 0x3ff; break; case 0x05: // AN4 -> AN5 - ad_value = m_an_read[4](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[5](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[4](0) & 0x3ff; + m_ad_result[1] = m_an_read[5](0) & 0x3ff; break; case 0x06: // AN4 -> AN5 -> AN6 - ad_value = m_an_read[4](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[5](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[6](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[4](0) & 0x3ff; + m_ad_result[1] = m_an_read[5](0) & 0x3ff; + m_ad_result[2] = m_an_read[6](0) & 0x3ff; break; case 0x07: // AN4 -> AN5 -> AN6 -> AN7 - ad_value = m_an_read[4](0) & 0x3ff; - m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[5](0) & 0x3ff; - m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[6](0) & 0x3ff; - m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; - ad_value = m_an_read[7](0) & 0x3ff; - m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; - m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; + m_ad_result[0] = m_an_read[4](0) & 0x3ff; + m_ad_result[1] = m_an_read[5](0) & 0x3ff; + m_ad_result[2] = m_an_read[6](0) & 0x3ff; + m_ad_result[3] = m_an_read[7](0) & 0x3ff; break; } } /* Clear BUSY flag, set END flag */ - m_reg[TMP95C063_ADMOD1] &= ~ 0x40; - m_reg[TMP95C063_ADMOD1] |= 0x80; + m_ad_mode1 &= ~ 0x40; + m_ad_mode1 |= 0x80; - m_reg[TMP95C063_INTE0AD] |= 0x80; + m_int_reg[TMP95C063_INTE0AD] |= 0x80; m_check_irqs = 1; } } @@ -648,6 +555,41 @@ void tmp95c063_device::device_start() { tlcs900h_device::device_start(); + save_item(NAME(m_port_latch)); + save_item(NAME(m_port_control)); + save_item(NAME(m_port_function)); + save_item(NAME(m_t8run)); + save_item(NAME(m_t8_reg)); + save_item(NAME(m_t8_mode)); + save_item(NAME(m_t8_invert)); + save_item(NAME(m_trdc)); + save_item(NAME(m_t16_reg)); + save_item(NAME(m_t16_cap)); + save_item(NAME(m_t16_mode)); + save_item(NAME(m_t16_invert)); + save_item(NAME(m_t89cr)); + save_item(NAME(m_t16run)); + save_item(NAME(m_pgreg)); + save_item(NAME(m_pg01cr)); + save_item(NAME(m_watchdog_mode)); + save_item(NAME(m_serial_control)); + save_item(NAME(m_serial_mode)); + save_item(NAME(m_baud_rate)); + save_item(NAME(m_od_enable)); + save_item(NAME(m_ad_mode1)); + save_item(NAME(m_ad_mode2)); + save_item(NAME(m_ad_result)); + save_item(NAME(m_int_reg)); + save_item(NAME(m_iimc)); + save_item(NAME(m_dma_vector)); + save_item(NAME(m_block_cs)); + save_item(NAME(m_external_cs)); + save_item(NAME(m_mem_start_reg)); + save_item(NAME(m_mem_start_mask)); + save_item(NAME(m_dram_refresh)); + save_item(NAME(m_dram_access)); + save_item(NAME(m_da_drive)); + m_port1_read.resolve_safe(0); m_port1_write.resolve_safe(); m_port2_write.resolve_safe(); @@ -675,16 +617,8 @@ void tmp95c063_device::device_start() void tmp95c063_device::device_reset() { - m_pc.b.l = RDMEM( 0xFFFF00 ); - m_pc.b.h = RDMEM( 0xFFFF01 ); - m_pc.b.h2 = RDMEM( 0xFFFF02 ); - m_pc.b.h3 = 0; - /* system mode, iff set to 111, max mode, register bank 0 */ - m_sr.d = 0xF800; - m_regbank = 0; - m_xssp.d = 0x0100; - m_halted = 0; - m_check_irqs = 0; + tlcs900h_device::device_reset(); + m_ad_cycles_left = 0; m_nmi_state = CLEAR_LINE; m_timer_pre = 0; @@ -693,312 +627,874 @@ void tmp95c063_device::device_reset() m_timer_change[2] = 0; m_timer_change[3] = 0; - m_reg[TMP95C063_P1] = 0x00; - m_reg[TMP95C063_P1CR] = 0x00; - m_reg[TMP95C063_P2] = 0xff; - m_reg[TMP95C063_P2FC] = 0x00; - m_reg[TMP95C063_P5] = 0x3d; - m_reg[TMP95C063_P5CR] = 0x00; - m_reg[TMP95C063_P5FC] = 0x00; - m_reg[TMP95C063_P6] = 0x3b; - m_reg[TMP95C063_P6FC] = 0x00; - m_reg[TMP95C063_P7] = 0xff; - m_reg[TMP95C063_P7CR] = 0x00; - m_reg[TMP95C063_P7FC] = 0x00; - m_reg[TMP95C063_P8] = 0x3f; - m_reg[TMP95C063_P8CR] = 0x00; - m_reg[TMP95C063_P8FC] = 0x00; - m_reg[TMP95C063_PA] = 0x0f; - m_reg[TMP95C063_PACR] = 0x00; - m_reg[TMP95C063_PAFC] = 0x00; - m_reg[TMP95C063_PB] = 0xff; - m_reg[TMP95C063_PBCR] = 0x00; - m_reg[TMP95C063_PBFC] = 0x00; - m_reg[TMP95C063_MSAR0] = 0xff; - m_reg[TMP95C063_MSAR1] = 0xff; - m_reg[TMP95C063_MSAR2] = 0xff; - m_reg[TMP95C063_MSAR3] = 0xff; - m_reg[TMP95C063_MAMR0] = 0xff; - m_reg[TMP95C063_MAMR1] = 0xff; - m_reg[TMP95C063_MAMR2] = 0xff; - m_reg[TMP95C063_MAMR3] = 0xff; - m_reg[TMP95C063_DREFCR1] = 0x00; - m_reg[TMP95C063_DMEMCR1] = 0x80; - m_reg[TMP95C063_DREFCR3] = 0x00; - m_reg[TMP95C063_DMEMCR3] = 0x80; - m_reg[TMP95C063_T01MOD] = 0x00; - m_reg[TMP95C063_T23MOD] = 0x00; - m_reg[TMP95C063_T02FFCR] = 0x00; - m_reg[TMP95C063_T46FFCR] = 0x00; - m_reg[TMP95C063_T8RUN] = 0x00; - m_reg[TMP95C063_TRDC] = 0x00; - m_reg[TMP95C063_T45MOD] = 0x20; - m_reg[TMP95C063_T46FFCR] = 0x00; - m_reg[TMP95C063_PG01CR] = 0x00; - m_reg[TMP95C063_PG0REG] = 0x00; - m_reg[TMP95C063_PG1REG] = 0x00; - m_reg[TMP95C063_SC0MOD] = 0x00; - m_reg[TMP95C063_SC0CR] = 0x00; - m_reg[TMP95C063_BR0CR] = 0x00; - m_reg[TMP95C063_SC1MOD] = 0x00; - m_reg[TMP95C063_SC1CR] = 0x00; - m_reg[TMP95C063_BR1CR] = 0x00; - m_reg[TMP95C063_P8FC] = 0x00; - m_reg[TMP95C063_ODE] = 0x00; - m_reg[TMP95C063_ADMOD1] = 0x00; - m_reg[TMP95C063_ADMOD2] = 0x00; - m_reg[TMP95C063_ADREG04L] = 0x3f; - m_reg[TMP95C063_ADREG04H] = 0x00; - m_reg[TMP95C063_ADREG15L] = 0x3f; - m_reg[TMP95C063_ADREG15H] = 0x00; - m_reg[TMP95C063_ADREG26L] = 0x3f; - m_reg[TMP95C063_ADREG26H] = 0x00; - m_reg[TMP95C063_ADREG37L] = 0x3f; - m_reg[TMP95C063_ADREG37H] = 0x00; - m_reg[TMP95C063_WDMOD] = 0x80; + m_port_latch[1] = 0x00; + m_port_latch[2] = 0xff; + m_port_latch[5] = 0x3d; + m_port_latch[6] = 0x3b; + m_port_latch[7] = 0xff; + m_port_latch[8] = 0x3f; + m_port_latch[0xa] = 0x0f; + m_port_latch[0xb] = 0xff; + std::fill_n(&m_port_control[0], 0xc, 0x00); + std::fill_n(&m_port_function[0], 0xc, 0x00); + m_t8run = 0x00; + std::fill_n(&m_t8_mode[0], 4, 0x00); + std::fill_n(&m_t8_invert[0], 2, 0xcc); + m_trdc = 0x00; + std::fill_n(&m_t16_mode[0], 2, 0x20); + std::fill_n(&m_t16_invert[0], 2, 0x00); + m_t89cr = 0x00; + m_t16run = 0x00; + m_pgreg[0] &= 0x0f; + m_pgreg[1] &= 0x0f; + m_pg01cr = 0x00; + m_watchdog_mode = 0x80; + for (int i = 0; i < 2; i++) + { + m_serial_control[i] &= 0x80; + m_serial_mode[i] &= 0x80; + m_baud_rate[i] = 0x00; + } + m_od_enable = 0x00; + m_ad_mode1 = 0x00; + m_ad_mode2 = 0x00; + std::fill_n(&m_int_reg[0], 0xf, 0x00); + m_iimc = 0x00; + std::fill_n(&m_dma_vector[0], 4, 0x00); + m_block_cs[0] = 0x00; + m_block_cs[1] = 0x00; + m_block_cs[2] = 0x10; + m_block_cs[3] = 0x00; + m_external_cs = 0x00; + std::fill_n(&m_mem_start_reg[0], 4, 0xff); + std::fill_n(&m_mem_start_mask[0], 4, 0xff); + std::fill_n(&m_dram_refresh[0], 2, 0x00); + std::fill_n(&m_dram_access[0], 2, 0x80); + m_da_drive = 0x00; for (int i = 0; i < TLCS900_NUM_INPUTS; i++) m_level[i] = CLEAR_LINE; +} + + +uint8_t tmp95c063_device::p1_r() +{ + return m_port1_read(0); +} + +void tmp95c063_device::p1_w(uint8_t data) +{ + m_port_latch[1] = data; + m_port1_write(0, data, 0xff); +} + +void tmp95c063_device::p1cr_w(uint8_t data) +{ + m_port_control[1] = data; +} + +uint8_t tmp95c063_device::p2_r() +{ + return m_port_latch[2]; +} + +void tmp95c063_device::p2_w(uint8_t data) +{ + m_port_latch[2] = data; + m_port2_write(0, data, 0xff); +} + +void tmp95c063_device::p2fc_w(uint8_t data) +{ + m_port_control[2] = data; +} + +uint8_t tmp95c063_device::p5_r() +{ + return m_port5_read(0); +} + +void tmp95c063_device::p5_w(uint8_t data) +{ + m_port_latch[5] = data; + m_port5_write(0, data, 0xff); +} + +void tmp95c063_device::p5cr_w(uint8_t data) +{ + m_port_control[5] = data; +} + +void tmp95c063_device::p5fc_w(uint8_t data) +{ + m_port_function[5] = data; +} + +uint8_t tmp95c063_device::p6_r() +{ + return m_port6_read(0); +} + +void tmp95c063_device::p6_w(uint8_t data) +{ + m_port_latch[6] = data; + m_port6_write(0, data, 0xff); +} + +void tmp95c063_device::p6fc_w(uint8_t data) +{ + m_port_function[6] = data; +} + +uint8_t tmp95c063_device::p7_r() +{ + return m_port7_read(0); +} + +void tmp95c063_device::p7_w(uint8_t data) +{ + m_port_latch[7] = data; + m_port7_write(0, data, 0xff); +} + +void tmp95c063_device::p7cr_w(uint8_t data) +{ + m_port_control[7] = data; +} + +void tmp95c063_device::p7fc_w(uint8_t data) +{ + m_port_function[7] = data; +} + +uint8_t tmp95c063_device::p8_r() +{ + return m_port8_read(0); +} + +void tmp95c063_device::p8_w(uint8_t data) +{ + m_port_latch[8] = data; + m_port8_write(0, data, 0xff); +} + +void tmp95c063_device::p8cr_w(uint8_t data) +{ + m_port_control[8] = data; +} + +void tmp95c063_device::p8fc_w(uint8_t data) +{ + m_port_function[8] = data; +} + +uint8_t tmp95c063_device::p9_r() +{ + return m_port9_read(0); +} + +void tmp95c063_device::p9_w(uint8_t data) +{ + m_port_latch[0x9] = data; +} + +void tmp95c063_device::p9cr_w(uint8_t data) +{ + m_port_control[0x9] = data; +} + +void tmp95c063_device::p9fc_w(uint8_t data) +{ + m_port_function[0x9] = data; +} + +uint8_t tmp95c063_device::pa_r() +{ + return m_porta_read(0); +} + +void tmp95c063_device::pa_w(uint8_t data) +{ + m_port_latch[0xa] = data; +} + +void tmp95c063_device::pacr_w(uint8_t data) +{ + m_port_control[0xa] = data; +} + +void tmp95c063_device::pafc_w(uint8_t data) +{ + m_port_function[0xa] = data; +} + +uint8_t tmp95c063_device::pb_r() +{ + return m_portb_read(0); +} + +void tmp95c063_device::pb_w(uint8_t data) +{ + m_port_latch[0xb] = data; + m_portb_write(0, data, 0xff); +} + +void tmp95c063_device::pbcr_w(uint8_t data) +{ + m_port_control[0xb] = data; +} + +void tmp95c063_device::pbfc_w(uint8_t data) +{ + m_port_function[0xb] = data; +} + +uint8_t tmp95c063_device::pc_r() +{ + return m_portc_read(0); +} + +uint8_t tmp95c063_device::pd_r() +{ + return m_portd_read(0); +} + +void tmp95c063_device::pd_w(uint8_t data) +{ + m_port_latch[0xd] = data; + m_portd_write(0, data, 0xff); +} + +void tmp95c063_device::pdcr_w(uint8_t data) +{ + m_port_control[0xd] = data; +} + +uint8_t tmp95c063_device::pe_r() +{ + return m_porte_read(0); +} + +void tmp95c063_device::pe_w(uint8_t data) +{ + m_port_latch[0xe] = data; + m_porte_write(0, data, 0xff); +} - m_prefetch_clear = true; +void tmp95c063_device::pecr_w(uint8_t data) +{ + m_port_control[0xe] = data; } -uint8_t tmp95c063_device::internal_r(offs_t offset) +uint8_t tmp95c063_device::t8run_r() +{ + return m_t8run; +} + +void tmp95c063_device::t8run_w(uint8_t data) { - switch (offset) + if ( ! ( data & 0x01 ) ) { - case TMP95C063_P1: m_reg[offset] = m_port1_read(0); break; - case TMP95C063_P5: m_reg[offset] = m_port5_read(0); break; - case TMP95C063_P6: m_reg[offset] = m_port6_read(0); break; - case TMP95C063_P7: m_reg[offset] = m_port7_read(0); break; - case TMP95C063_P8: m_reg[offset] = m_port8_read(0); break; - case TMP95C063_P9: m_reg[offset] = m_port9_read(0); break; - case TMP95C063_PA: m_reg[offset] = m_porta_read(0); break; - case TMP95C063_PB: m_reg[offset] = m_portb_read(0); break; - case TMP95C063_PC: m_reg[offset] = m_portc_read(0); break; - case TMP95C063_PD: m_reg[offset] = m_portd_read(0); break; - case TMP95C063_PE: m_reg[offset] = m_porte_read(0); break; + m_timer[0] = 0; + m_timer_change[0] = 0; } - return m_reg[ offset ]; + if ( ! ( data & 0x02 ) ) + { + m_timer[1] = 0; + m_timer_change[1] = 0; + } + if ( ! ( data & 0x04 ) ) + { + m_timer[2] = 0; + m_timer_change[2] = 0; + } + if ( ! ( data & 0x08 ) ) + { + m_timer[3] = 0; + m_timer_change[3] = 0; + } + if ( ! ( data & 0x10 ) ) + m_timer[4] = 0; + if ( ! ( data & 0x20 ) ) + m_timer[5] = 0; + + m_t8run = data; } +void tmp95c063_device::treg01_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset] = data; +} + +uint8_t tmp95c063_device::t01mod_r() +{ + return m_t8_mode[0]; +} -void tmp95c063_device::internal_w(offs_t offset, uint8_t data) +void tmp95c063_device::t01mod_w(uint8_t data) { - switch ( offset ) + m_t8_mode[0] = data; +} + +uint8_t tmp95c063_device::t02ffcr_r() +{ + return m_t8_invert[0]; +} + +void tmp95c063_device::t02ffcr_w(uint8_t data) +{ + switch( data & 0x0c ) { - case TMP95C063_T8RUN: - if ( ! ( data & 0x01 ) ) - { - m_timer[0] = 0; - m_timer_change[0] = 0; - } - if ( ! ( data & 0x02 ) ) - { - m_timer[1] = 0; - m_timer_change[1] = 0; - } - if ( ! ( data & 0x04 ) ) - { - m_timer[2] = 0; - m_timer_change[2] = 0; - } - if ( ! ( data & 0x08 ) ) - { - m_timer[3] = 0; - m_timer_change[3] = 0; - } - if ( ! ( data & 0x10 ) ) - m_timer[4] = 0; - if ( ! ( data & 0x20 ) ) - m_timer[5] = 0; + case 0x00: + //tlcs900_change_tff( 1, FF_INVERT ); break; - - case TMP95C063_T02FFCR: - switch( data & 0x0c ) - { - case 0x00: - //tlcs900_change_tff( 1, FF_INVERT ); - break; - case 0x04: - //tlcs900_change_tff( 1, FF_SET ); - break; - case 0x08: - //tlcs900_change_tff( 1, FF_CLEAR ); - break; - } - switch( data & 0xc0 ) - { - case 0x00: - //tlcs900_change_tff( 3, FF_INVERT ); - break; - case 0x40: - //tlcs900_change_tff( 3, FF_SET ); - break; - case 0x80: - //tlcs900_change_tff( 3, FF_CLEAR ); - break; - } + case 0x04: + //tlcs900_change_tff( 1, FF_SET ); break; - - case TMP95C063_T46FFCR: - switch( data & 0x0c ) - { - case 0x00: - //tlcs900_change_tff( 5, FF_INVERT ); - break; - case 0x04: - //tlcs900_change_tff( 5, FF_SET ); - break; - case 0x08: - //tlcs900_change_tff( 5, FF_CLEAR ); - break; - } - switch( data & 0xc0 ) - { - case 0x00: - //tlcs900_change_tff( 7, FF_INVERT ); - break; - case 0x40: - //tlcs900_change_tff( 7, FF_SET ); - break; - case 0x80: - //tlcs900_change_tff( 7, FF_CLEAR ); - break; - } + case 0x08: + //tlcs900_change_tff( 1, FF_CLEAR ); break; - - case TMP95C063_T8FFCR: - switch( data & 0x03 ) - { - case 0x00: - //tlcs900_change_tff( 8, FF_INVERT ); - break; - case 0x01: - //tlcs900_change_tff( 8, FF_SET ); - break; - case 0x02: - //tlcs900_change_tff( 8, FF_CLEAR ); - break; - } - switch( data & 0xc0 ) - { - case 0x00: - //tlcs900_change_tff( 9, FF_INVERT ); - break; - case 0x40: - //tlcs900_change_tff( 9, FF_SET ); - break; - case 0x80: - //tlcs900_change_tff( 9, FF_CLEAR ); - break; - } + } + switch( data & 0xc0 ) + { + case 0x00: + //tlcs900_change_tff( 3, FF_INVERT ); break; - - case TMP95C063_T9FFCR: - switch( data & 0x03 ) - { - case 0x00: - //tlcs900_change_tff( 0xa, FF_INVERT ); - break; - case 0x01: - //tlcs900_change_tff( 0xa, FF_SET ); - break; - case 0x02: - //tlcs900_change_tff( 0xa, FF_CLEAR ); - break; - } - switch( data & 0xc0 ) - { - case 0x00: - //tlcs900_change_tff( 0xb, FF_INVERT ); - break; - case 0x40: - //tlcs900_change_tff( 0xb, FF_SET ); - break; - case 0x80: - //tlcs900_change_tff( 0xb, FF_CLEAR ); - break; - } + case 0x40: + //tlcs900_change_tff( 3, FF_SET ); break; - - case TMP95C063_MSAR0: - case TMP95C063_MAMR0: - case TMP95C063_MSAR1: - case TMP95C063_MAMR1: + case 0x80: + //tlcs900_change_tff( 3, FF_CLEAR ); break; + } - case TMP95C063_WDMOD: - case TMP95C063_WDCR: - break; + m_t8_invert[0] = data | 0xcc; +} - case TMP95C063_INTE0AD: - case TMP95C063_INTE12: - case TMP95C063_INTE34: - case TMP95C063_INTE56: - case TMP95C063_INTE78: - case TMP95C063_INTET01: - case TMP95C063_INTET23: - case TMP95C063_INTET45: - case TMP95C063_INTET67: - case TMP95C063_INTET89: - case TMP95C063_INTETAB: - case TMP95C063_INTES0: - case TMP95C063_INTES1: - case TMP95C063_INTETC01: - case TMP95C063_INTETC23: - if ( data & 0x80 ) - data = ( data & 0x7f ) | ( m_reg[offset] & 0x80 ); - if ( data & 0x08 ) - data = ( data & 0xf7 ) | ( m_reg[offset] & 0x08 ); - break; +void tmp95c063_device::treg23_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset + 2] = data; +} - case TMP95C063_IIMC: - break; +uint8_t tmp95c063_device::t23mod_r() +{ + return m_t8_mode[1]; +} - case TMP95C063_ADMOD1: - // conversion start - if (data & 0x04) - { - data &= ~0x04; - data |= 0x40; +void tmp95c063_device::t23mod_w(uint8_t data) +{ + m_t8_mode[1] = data; +} - switch ((m_reg[TMP95C063_ADMOD2] >> 4) & 3) - { - case 0: m_ad_cycles_left = 160; break; - case 1: m_ad_cycles_left = 320; break; - case 2: m_ad_cycles_left = 640; break; - case 3: m_ad_cycles_left = 1280; break; - } - } +uint8_t tmp95c063_device::trdc_r() +{ + return m_trdc; +} + +void tmp95c063_device::trdc_w(uint8_t data) +{ + m_trdc = data; +} + +void tmp95c063_device::treg45_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset + 4] = data; +} + +uint8_t tmp95c063_device::t45mod_r() +{ + return m_t8_mode[2]; +} + +void tmp95c063_device::t45mod_w(uint8_t data) +{ + m_t8_mode[2] = data; +} + +uint8_t tmp95c063_device::t46ffcr_r() +{ + return m_t8_invert[1]; +} + +void tmp95c063_device::t46ffcr_w(uint8_t data) +{ + switch( data & 0x0c ) + { + case 0x00: + //tlcs900_change_tff( 5, FF_INVERT ); + break; + case 0x04: + //tlcs900_change_tff( 5, FF_SET ); + break; + case 0x08: + //tlcs900_change_tff( 5, FF_CLEAR ); + break; + } + switch( data & 0xc0 ) + { + case 0x00: + //tlcs900_change_tff( 7, FF_INVERT ); + break; + case 0x40: + //tlcs900_change_tff( 7, FF_SET ); + break; + case 0x80: + //tlcs900_change_tff( 7, FF_CLEAR ); break; + } + + m_t8_invert[1] = data | 0xcc; +} + +void tmp95c063_device::treg67_w(offs_t offset, uint8_t data) +{ + m_t8_reg[offset + 6] = data; +} + +uint8_t tmp95c063_device::t67mod_r() +{ + return m_t8_mode[3]; +} + +void tmp95c063_device::t67mod_w(uint8_t data) +{ + m_t8_mode[3] = data; +} + +void tmp95c063_device::treg89_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_t16_reg[offset >> 1] = (m_t16_reg[offset >> 1] & 0x00ff) | uint16_t(data) << 8; + else + m_t16_reg[offset >> 1] = (m_t16_reg[offset >> 1] & 0xff00) | data; +} - case TMP95C063_ADMOD2: +uint8_t tmp95c063_device::cap12_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_t16_cap[offset >> 1] >> 8; + else + return m_t16_cap[offset >> 1] & 0x00ff; +} + +uint8_t tmp95c063_device::t8mod_r() +{ + return m_t16_mode[0]; +} + +void tmp95c063_device::t8mod_w(uint8_t data) +{ + m_t16_mode[0] = data | 0x20; +} + +uint8_t tmp95c063_device::t8ffcr_r() +{ + return m_t16_invert[0]; +} + +void tmp95c063_device::t8ffcr_w(uint8_t data) +{ + switch( data & 0x03 ) + { + case 0x00: + //tlcs900_change_tff( 8, FF_INVERT ); break; + case 0x01: + //tlcs900_change_tff( 8, FF_SET ); + break; + case 0x02: + //tlcs900_change_tff( 8, FF_CLEAR ); + break; + } + switch( data & 0xc0 ) + { + case 0x00: + //tlcs900_change_tff( 9, FF_INVERT ); + break; + case 0x40: + //tlcs900_change_tff( 9, FF_SET ); + break; + case 0x80: + //tlcs900_change_tff( 9, FF_CLEAR ); + break; + } + + m_t16_invert[0] = data | 0xc3; +} + +uint8_t tmp95c063_device::t89cr_r() +{ + return m_t89cr; +} + +void tmp95c063_device::t89cr_w(uint8_t data) +{ + m_t89cr = data; +} - default: +uint8_t tmp95c063_device::t16run_r() +{ + return m_t16run; +} + +void tmp95c063_device::t16run_w(uint8_t data) +{ + m_t16run = data; +} + +void tmp95c063_device::tregab_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_t16_reg[(offset >> 1) + 2] = (m_t16_reg[(offset >> 1) + 2] & 0x00ff) | uint16_t(data) << 8; + else + m_t16_reg[(offset >> 1) + 2] = (m_t16_reg[(offset >> 1) + 2] & 0xff00) | data; +} + +uint8_t tmp95c063_device::cap34_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_t16_cap[(offset >> 1) + 2] >> 8; + else + return m_t16_cap[(offset >> 1) + 2] & 0x00ff; +} + +uint8_t tmp95c063_device::t9mod_r() +{ + return m_t16_mode[1]; +} + +void tmp95c063_device::t9mod_w(uint8_t data) +{ + m_t16_mode[1] = data | 0x20; +} + +uint8_t tmp95c063_device::t9ffcr_r() +{ + return m_t16_invert[1]; +} + +void tmp95c063_device::t9ffcr_w(uint8_t data) +{ + switch( data & 0x03 ) + { + case 0x00: + //tlcs900_change_tff( 0xa, FF_INVERT ); + break; + case 0x01: + //tlcs900_change_tff( 0xa, FF_SET ); + break; + case 0x02: + //tlcs900_change_tff( 0xa, FF_CLEAR ); + break; + } + switch( data & 0xc0 ) + { + case 0x00: + //tlcs900_change_tff( 0xb, FF_INVERT ); + break; + case 0x40: + //tlcs900_change_tff( 0xb, FF_SET ); + break; + case 0x80: + //tlcs900_change_tff( 0xb, FF_CLEAR ); break; } - m_check_irqs = 1; - m_reg[ offset ] = data; + m_t16_invert[1] = data | 0xc3; +} + + +uint8_t tmp95c063_device::pgreg_r(offs_t offset) +{ + return m_pgreg[offset]; +} + +void tmp95c063_device::pgreg_w(offs_t offset, uint8_t data) +{ + m_pgreg[offset] = data; +} + +uint8_t tmp95c063_device::pg01cr_r() +{ + return m_pg01cr; +} + +void tmp95c063_device::pg01cr_w(uint8_t data) +{ + m_pg01cr = data; +} + + +uint8_t tmp95c063_device::wdmod_r() +{ + return m_watchdog_mode; +} + +void tmp95c063_device::wdmod_w(uint8_t data) +{ + m_watchdog_mode = data; +} + +void tmp95c063_device::wdcr_w(uint8_t data) +{ +} + + +uint8_t tmp95c063_device::sc0buf_r() +{ + return 0; +} + +void tmp95c063_device::sc0buf_w(uint8_t data) +{ + // Fake finish sending data + m_int_reg[TMP95C063_INTES0] |= 0x80; +} + +uint8_t tmp95c063_device::sc0cr_r() +{ + uint8_t reg = m_serial_control[0]; + if (!machine().side_effects_disabled()) + m_serial_control[0] &= 0xe3; + return reg; +} + +void tmp95c063_device::sc0cr_w(uint8_t data) +{ + m_serial_control[0] = data; +} + +uint8_t tmp95c063_device::sc0mod_r() +{ + return m_serial_mode[0]; +} + +void tmp95c063_device::sc0mod_w(uint8_t data) +{ + m_serial_mode[0] = data; +} - switch (offset) +uint8_t tmp95c063_device::br0cr_r() +{ + return m_baud_rate[0]; +} + +void tmp95c063_device::br0cr_w(uint8_t data) +{ + m_baud_rate[0] = data; +} + +uint8_t tmp95c063_device::sc1buf_r() +{ + return 0; +} + +void tmp95c063_device::sc1buf_w(uint8_t data) +{ + // Fake finish sending data + m_int_reg[TMP95C063_INTES1] |= 0x80; +} + +uint8_t tmp95c063_device::sc1cr_r() +{ + uint8_t reg = m_serial_control[1]; + if (!machine().side_effects_disabled()) + m_serial_control[1] &= 0xe3; + return reg; +} + +void tmp95c063_device::sc1cr_w(uint8_t data) +{ + m_serial_control[1] = data; +} + +uint8_t tmp95c063_device::sc1mod_r() +{ + return m_serial_mode[1]; +} + +void tmp95c063_device::sc1mod_w(uint8_t data) +{ + m_serial_mode[1] = data; +} + +uint8_t tmp95c063_device::br1cr_r() +{ + return m_baud_rate[1]; +} + +void tmp95c063_device::br1cr_w(uint8_t data) +{ + m_baud_rate[1] = data; +} + +uint8_t tmp95c063_device::ode_r() +{ + return m_od_enable; +} + +void tmp95c063_device::ode_w(uint8_t data) +{ + m_od_enable = data; +} + + +uint8_t tmp95c063_device::admod1_r() +{ + return m_ad_mode1; +} + +void tmp95c063_device::admod1_w(uint8_t data) +{ + // Preserve read-only bits + data = ( m_ad_mode1 & 0xc0 ) | ( data & 0x34 ); + + // Check for A/D conversion start + if (data & 0x04) { - case TMP95C063_P1: m_port1_write(0, data, 0xff); break; - case TMP95C063_P2: m_port2_write(0, data, 0xff); break; - case TMP95C063_P5: m_port5_write(0, data, 0xff); break; - case TMP95C063_P6: m_port6_write(0, data, 0xff); break; - case TMP95C063_P7: m_port7_write(0, data, 0xff); break; - case TMP95C063_P8: m_port8_write(0, data, 0xff); break; - case TMP95C063_P9: m_port9_write(0, data, 0xff); break; - case TMP95C063_PA: m_porta_write(0, data, 0xff); break; - case TMP95C063_PB: m_portb_write(0, data, 0xff); break; - //case TMP95C063_PC: m_portc_write(0, data, 0xff); break; - case TMP95C063_PD: m_portd_write(0, data, 0xff); break; - case TMP95C063_PE: m_porte_write(0, data, 0xff); break; + data &= ~0x04; + data |= 0x40; + + switch ((m_ad_mode2 >> 4) & 3) + { + case 0: m_ad_cycles_left = 160; break; + case 1: m_ad_cycles_left = 320; break; + case 2: m_ad_cycles_left = 640; break; + case 3: m_ad_cycles_left = 1280; break; + } } + + m_ad_mode1 = data; +} + +uint8_t tmp95c063_device::admod2_r() +{ + return m_ad_mode2; +} + +void tmp95c063_device::admod2_w(uint8_t data) +{ + m_ad_mode2 = data; +} + +uint8_t tmp95c063_device::adreg_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_ad_result[offset >> 1] >> 2; + else + return m_ad_result[offset >> 1] << 6 | 0x3f; +} + + +uint8_t tmp95c063_device::inte_r(offs_t offset) +{ + return m_int_reg[offset]; +} + +void tmp95c063_device::inte_w(offs_t offset, uint8_t data) +{ + if ( data & 0x80 ) + data = ( data & 0x7f ) | ( m_int_reg[offset] & 0x80 ); + if ( data & 0x08 ) + data = ( data & 0xf7 ) | ( m_int_reg[offset] & 0x08 ); + + m_int_reg[offset] = data; + m_check_irqs = 1; +} + +void tmp95c063_device::iimc_w(uint8_t data) +{ + m_iimc = data; + m_check_irqs = 1; +} + +void tmp95c063_device::dmav_w(offs_t offset, uint8_t data) +{ + m_dma_vector[offset] = data; +} + + +void tmp95c063_device::bcs_w(offs_t offset, uint8_t data) +{ + m_block_cs[offset] = data; +} + +void tmp95c063_device::bexcs_w(uint8_t data) +{ + m_external_cs = data; +} + +uint8_t tmp95c063_device::msar_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_mem_start_mask[offset >> 1]; + else + return m_mem_start_reg[offset >> 1]; +} + +void tmp95c063_device::msar_w(offs_t offset, uint8_t data) +{ + if (BIT(offset, 0)) + m_mem_start_mask[offset >> 1] = data; + else + m_mem_start_reg[offset >> 1] = data; +} + + +uint8_t tmp95c063_device::drefcr1_r() +{ + return m_dram_refresh[0]; +} + +void tmp95c063_device::drefcr1_w(uint8_t data) +{ + m_dram_refresh[0] = data; +} + +uint8_t tmp95c063_device::dmemcr1_r() +{ + return m_dram_access[0]; +} + +void tmp95c063_device::dmemcr1_w(uint8_t data) +{ + m_dram_access[0] = data; +} + +uint8_t tmp95c063_device::drefcr3_r() +{ + return m_dram_refresh[1]; +} + +void tmp95c063_device::drefcr3_w(uint8_t data) +{ + m_dram_refresh[1] = data; +} + +uint8_t tmp95c063_device::dmemcr3_r() +{ + return m_dram_access[1]; +} + +void tmp95c063_device::dmemcr3_w(uint8_t data) +{ + m_dram_access[1] = data; +} + + +uint8_t tmp95c063_device::dadrv_r() +{ + return m_da_drive; +} + +void tmp95c063_device::dadrv_w(uint8_t data) +{ + m_da_drive = data; +} + +void tmp95c063_device::dareg_w(offs_t offset, uint8_t data) +{ } @@ -1020,25 +1516,25 @@ void tmp95c063_device::execute_set_input(int input, int level) case TLCS900_INT0: /* Is INT0 functionality enabled? */ - if (m_reg[TMP95C063_IIMC] & 0x04) + if (m_iimc & 0x04) { - if (m_reg[TMP95C063_IIMC] & 0x02) + if (m_iimc & 0x02) { /* Rising edge detect */ if (m_level[TLCS900_INT0] == CLEAR_LINE && level == ASSERT_LINE) { /* Leave HALT state */ m_halted = 0; - m_reg[TMP95C063_INTE0AD] |= 0x08; + m_int_reg[TMP95C063_INTE0AD] |= 0x08; } } else { /* Level detect */ if (level == ASSERT_LINE) - m_reg[TMP95C063_INTE0AD] |= 0x08; + m_int_reg[TMP95C063_INTE0AD] |= 0x08; else - m_reg[TMP95C063_INTE0AD] &= ~ 0x08; + m_int_reg[TMP95C063_INTE0AD] &= ~ 0x08; } } m_level[TLCS900_INT0] = level; @@ -1047,11 +1543,11 @@ void tmp95c063_device::execute_set_input(int input, int level) case TLCS900_INT1: if (m_level[TLCS900_INT1] == CLEAR_LINE && level == ASSERT_LINE) { - m_reg[TMP95C063_INTE12] |= 0x08; + m_int_reg[TMP95C063_INTE12] |= 0x08; } else if (m_level[TLCS900_INT1] == ASSERT_LINE && level == CLEAR_LINE) { - m_reg[TMP95C063_INTE12] &= ~0x08; + m_int_reg[TMP95C063_INTE12] &= ~0x08; } m_level[TLCS900_INT1] = level; break; @@ -1059,11 +1555,11 @@ void tmp95c063_device::execute_set_input(int input, int level) case TLCS900_INT2: if (m_level[TLCS900_INT2] == CLEAR_LINE && level == ASSERT_LINE) { - m_reg[TMP95C063_INTE12] |= 0x80; + m_int_reg[TMP95C063_INTE12] |= 0x80; } else if (m_level[TLCS900_INT2] == ASSERT_LINE && level == CLEAR_LINE) { - m_reg[TMP95C063_INTE12] &= ~0x80; + m_int_reg[TMP95C063_INTE12] &= ~0x80; } m_level[TLCS900_INT2] = level; break; @@ -1071,32 +1567,32 @@ void tmp95c063_device::execute_set_input(int input, int level) case TLCS900_INT3: if (m_level[TLCS900_INT3] == CLEAR_LINE && level == ASSERT_LINE) { - m_reg[TMP95C063_INTE34] |= 0x08; + m_int_reg[TMP95C063_INTE34] |= 0x08; } else if (m_level[TLCS900_INT3] == ASSERT_LINE && level == CLEAR_LINE) { - m_reg[TMP95C063_INTE34] &= ~0x08; + m_int_reg[TMP95C063_INTE34] &= ~0x08; } m_level[TLCS900_INT3] = level; break; case TLCS900_INT4: - if ( ! ( m_reg[TMP95C063_PBCR] & 0x01 ) ) + if ( ! ( m_port_control[0xb] & 0x01 ) ) { if ( m_level[TLCS900_INT4] == CLEAR_LINE && level == ASSERT_LINE ) { - m_reg[TMP95C063_INTE34] |= 0x80; + m_int_reg[TMP95C063_INTE34] |= 0x80; } } m_level[TLCS900_INT4] = level; break; case TLCS900_INT5: - if ( ! ( m_reg[TMP95C063_PBCR] & 0x02 ) ) + if ( ! ( m_port_control[0xb] & 0x02 ) ) { if ( m_level[TLCS900_INT5] == CLEAR_LINE && level == ASSERT_LINE ) { - m_reg[TMP95C063_INTE56] |= 0x08; + m_int_reg[TMP95C063_INTE56] |= 0x08; } } m_level[TLCS900_INT5] = level; @@ -1105,17 +1601,17 @@ void tmp95c063_device::execute_set_input(int input, int level) case TLCS900_INT6: if (m_level[TLCS900_INT6] == CLEAR_LINE && level == ASSERT_LINE) { - m_reg[TMP95C063_INTE56] |= 0x80; + m_int_reg[TMP95C063_INTE56] |= 0x80; } else if (m_level[TLCS900_INT6] == ASSERT_LINE && level == CLEAR_LINE) { - m_reg[TMP95C063_INTE56] &= ~0x80; + m_int_reg[TMP95C063_INTE56] &= ~0x80; } m_level[TLCS900_INT6] = level; break; case TLCS900_TIO: /* External timer input for timer 0 */ - if ( ( m_reg[TMP95C063_T8RUN] & 0x01 ) && ( m_reg[TMP95C063_T01MOD] & 0x03 ) == 0x00 ) + if ( ( m_t8run & 0x01 ) && ( m_t8_mode[0] & 0x03 ) == 0x00 ) { if ( m_level[TLCS900_TIO] == CLEAR_LINE && level == ASSERT_LINE ) { diff --git a/src/devices/cpu/tlcs900/tmp95c063.h b/src/devices/cpu/tlcs900/tmp95c063.h index d331a837767..4c9c05bb433 100644 --- a/src/devices/cpu/tlcs900/tmp95c063.h +++ b/src/devices/cpu/tlcs900/tmp95c063.h @@ -54,8 +54,131 @@ protected: virtual void tlcs900_handle_timers() override; private: - uint8_t internal_r(offs_t offset); - void internal_w(offs_t offset, uint8_t data); + uint8_t p1_r(); + void p1_w(uint8_t data); + void p1cr_w(uint8_t data); + uint8_t p2_r(); + void p2_w(uint8_t data); + void p2fc_w(uint8_t data); + uint8_t p5_r(); + void p5_w(uint8_t data); + void p5cr_w(uint8_t data); + void p5fc_w(uint8_t data); + uint8_t p6_r(); + void p6_w(uint8_t data); + void p6fc_w(uint8_t data); + uint8_t p7_r(); + void p7_w(uint8_t data); + void p7cr_w(uint8_t data); + void p7fc_w(uint8_t data); + uint8_t p8_r(); + void p8_w(uint8_t data); + void p8cr_w(uint8_t data); + void p8fc_w(uint8_t data); + uint8_t p9_r(); + void p9_w(uint8_t data); + void p9cr_w(uint8_t data); + void p9fc_w(uint8_t data); + uint8_t pa_r(); + void pa_w(uint8_t data); + void pacr_w(uint8_t data); + void pafc_w(uint8_t data); + uint8_t pb_r(); + void pb_w(uint8_t data); + void pbcr_w(uint8_t data); + void pbfc_w(uint8_t data); + uint8_t pc_r(); + uint8_t pd_r(); + void pd_w(uint8_t data); + void pdcr_w(uint8_t data); + uint8_t pe_r(); + void pe_w(uint8_t data); + void pecr_w(uint8_t data); + uint8_t t8run_r(); + void t8run_w(uint8_t data); + void treg01_w(offs_t offset, uint8_t data); + uint8_t t01mod_r(); + void t01mod_w(uint8_t data); + uint8_t t02ffcr_r(); + void t02ffcr_w(uint8_t data); + void treg23_w(offs_t offset, uint8_t data); + uint8_t t23mod_r(); + void t23mod_w(uint8_t data); + uint8_t trdc_r(); + void trdc_w(uint8_t data); + void treg45_w(offs_t offset, uint8_t data); + uint8_t t45mod_r(); + void t45mod_w(uint8_t data); + uint8_t t46ffcr_r(); + void t46ffcr_w(uint8_t data); + void treg67_w(offs_t offset, uint8_t data); + uint8_t t67mod_r(); + void t67mod_w(uint8_t data); + void treg89_w(offs_t offset, uint8_t data); + uint8_t cap12_r(offs_t offset); + uint8_t t8mod_r(); + void t8mod_w(uint8_t data); + uint8_t t8ffcr_r(); + void t8ffcr_w(uint8_t data); + uint8_t t89cr_r(); + void t89cr_w(uint8_t data); + uint8_t t16run_r(); + void t16run_w(uint8_t data); + void tregab_w(offs_t offset, uint8_t data); + uint8_t cap34_r(offs_t offset); + uint8_t t9mod_r(); + void t9mod_w(uint8_t data); + uint8_t t9ffcr_r(); + void t9ffcr_w(uint8_t data); + uint8_t pgreg_r(offs_t offset); + void pgreg_w(offs_t offset, uint8_t data); + uint8_t pg01cr_r(); + void pg01cr_w(uint8_t data); + uint8_t wdmod_r(); + void wdmod_w(uint8_t data); + void wdcr_w(uint8_t data); + uint8_t sc0buf_r(); + void sc0buf_w(uint8_t data); + uint8_t sc0cr_r(); + void sc0cr_w(uint8_t data); + uint8_t sc0mod_r(); + void sc0mod_w(uint8_t data); + uint8_t br0cr_r(); + void br0cr_w(uint8_t data); + uint8_t sc1buf_r(); + void sc1buf_w(uint8_t data); + uint8_t sc1cr_r(); + void sc1cr_w(uint8_t data); + uint8_t sc1mod_r(); + void sc1mod_w(uint8_t data); + uint8_t br1cr_r(); + void br1cr_w(uint8_t data); + uint8_t ode_r(); + void ode_w(uint8_t data); + uint8_t admod1_r(); + void admod1_w(uint8_t data); + uint8_t admod2_r(); + void admod2_w(uint8_t data); + uint8_t adreg_r(offs_t offset); + uint8_t inte_r(offs_t offset); + void inte_w(offs_t offset, uint8_t data); + void iimc_w(uint8_t data); + void dmav_w(offs_t offset, uint8_t data); + void bcs_w(offs_t offset, uint8_t data); + void bexcs_w(uint8_t data); + uint8_t msar_r(offs_t offset); + void msar_w(offs_t offset, uint8_t data); + uint8_t drefcr1_r(); + void drefcr1_w(uint8_t data); + uint8_t dmemcr1_r(); + void dmemcr1_w(uint8_t data); + uint8_t drefcr3_r(); + void drefcr3_w(uint8_t data); + uint8_t dmemcr3_r(); + void dmemcr3_w(uint8_t data); + uint8_t dadrv_r(); + void dadrv_w(uint8_t data); + void dareg_w(offs_t offset, uint8_t data); void internal_mem(address_map &map); @@ -107,6 +230,60 @@ private: // analogue inputs, sampled at 10 bits devcb_read16::array<8> m_an_read; + + // I/O Port Control + uint8_t m_port_latch[0xf]; + uint8_t m_port_control[0xf]; + uint8_t m_port_function[0xf]; + + // Timer Control + uint8_t m_t8run; + uint8_t m_t8_reg[8]; + uint8_t m_t8_mode[4]; + uint8_t m_t8_invert[2]; + uint8_t m_trdc; + uint16_t m_t16_reg[4]; + uint16_t m_t16_cap[4]; + uint8_t m_t16_mode[2]; + uint8_t m_t16_invert[2]; + uint8_t m_t89cr; + uint8_t m_t16run; + + // Pattern Generator + uint8_t m_pgreg[2]; + uint8_t m_pg01cr; + + // Watchdog Timer + uint8_t m_watchdog_mode; + + // Serial Channel + uint8_t m_serial_control[2]; + uint8_t m_serial_mode[2]; + uint8_t m_baud_rate[2]; + uint8_t m_od_enable; + + // A/D Converter Control + uint8_t m_ad_mode1; + uint8_t m_ad_mode2; + uint16_t m_ad_result[4]; + + // Interrupt Control + uint8_t m_int_reg[0xf]; + uint8_t m_iimc; + uint8_t m_dma_vector[4]; + + // Chip Select/Wait Control + uint8_t m_block_cs[4]; + uint8_t m_external_cs; + uint8_t m_mem_start_reg[4]; + uint8_t m_mem_start_mask[4]; + + // DRAM Control + uint8_t m_dram_refresh[2]; + uint8_t m_dram_access[2]; + + // D/A Converter Control + uint8_t m_da_drive; }; #endif // MAME_CPU_TLCS900_TMP95C063_H -- cgit v1.2.3