From 02595ddf2ebacefc6393a137abb34aa8f1c05377 Mon Sep 17 00:00:00 2001 From: angelosa Date: Thu, 8 Aug 2024 11:54:54 +0200 Subject: m6502/om65ce02.lst: fix dew_zpg, phw_aba, phw_iw2 [smf] * allows commodore/c65 BASIC to be workable --- src/devices/cpu/m6502/om65ce02.lst | 8 ++++---- src/mame/commodore/c65.cpp | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/devices/cpu/m6502/om65ce02.lst b/src/devices/cpu/m6502/om65ce02.lst index c498744b2a7..800ce84488d 100644 --- a/src/devices/cpu/m6502/om65ce02.lst +++ b/src/devices/cpu/m6502/om65ce02.lst @@ -672,12 +672,12 @@ dew_zpg TMP2++; TMP = set_h(TMP, read(B|TMP2)); P &= ~(F_N|F_Z); - TMP++; + TMP--; if(!TMP) P |= F_Z; else if(TMP & 0x8000) P |= F_N; - TMP2++; + TMP2--; write(B|TMP2, TMP); TMP2++; write(B|TMP2, TMP >> 8); @@ -1198,10 +1198,10 @@ phw_aba PC++; TMP3 = read(TMP); TMP3 = set_h(TMP3, read(TMP+1)); - dec_SP_ce(); write(SP, TMP3); dec_SP_ce(); write(SP, TMP3 >> 8); + dec_SP_ce(); prefetch(); phw_iw2 @@ -1209,10 +1209,10 @@ phw_iw2 PC++; TMP = set_h(TMP, read_pc()); PC++; - dec_SP_ce(); write(SP, TMP); dec_SP_ce(); write(SP, TMP >> 8); + dec_SP_ce(); prefetch(); phx_ce_imp diff --git a/src/mame/commodore/c65.cpp b/src/mame/commodore/c65.cpp index 99abcbcf5aa..dda23c0e0b2 100644 --- a/src/mame/commodore/c65.cpp +++ b/src/mame/commodore/c65.cpp @@ -5,10 +5,9 @@ C=65 / C=64DX (c) 1991 Commodore TODO: -- Fails interpreting BASIC commands, CPU core bug? - DDR/port support from M4510; - Complete memory model; -\- rom8 / roma and rome all causes issues if hooked up (needs the CPU DDR port?) +\- rom8 / roma / rome all causes bootstrap issues if hooked up (needs the CPU DDR port?) \- Work RAM should really use a memory_share_creator, VIC-III can potentially access the full range. \- CRAM is really just RAM that bitplane mode can access as-is; - Complete interrupts; -- cgit v1.2.3