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* Updates "2017" strings to "2018" where relevant. Jonathan Holt2018-01-061-1/+1
* Updates "2016" strings to "2017 where relevant. Stiletto2017-01-241-1/+1
* coretmpl: add an associative LRU cache with map-like behaviour Vas Crabb2016-12-151-3/+4
* Few more characters (nw) Vas Crabb2016-11-211-3/+160
* Add typographical characters to uismall.bdf, including the hair space used by... Vas Crabb2016-11-211-1/+353
* uismall.bdf: improve legibility of Russian at small sizes Vas Crabb2016-07-081-49/+48
* uismall.bdf: add monotonic Greek (and a couple of archaic Cyrillic characters) Vas Crabb2016-07-051-1/+1051
* Fix advance of some cyrillic characters Vas Crabb2016-07-011-8/+8
* uismall.bdf: add half-width katakana and some more Cyrillic characters Vas Crabb2016-07-011-3/+1640
* uismall.bdf: Add most of Latin-B, some IPA extensions, and many additional Cy... Vas Crabb2016-07-011-15/+4971
* Add the rest of Latin B and some archaic Cyrillic characters to uismall.bdf Vas Crabb2016-06-301-21/+1494
* Add 96 Cyrillic characters to uismall.bdf - covers at least Russian, Ukrainia... Vas Crabb2016-06-301-3/+1323
* Add first 48 Latin-1 Supplement characters to uismall.bdf Vas Crabb2016-06-301-3/+746
* Use Adobe standard glyph names where possible Vas Crabb2016-03-211-87/+87
* Whoops, forgot one character Vas Crabb2016-03-211-1/+17
* tag uismall with ISO-8859-1 encoding, add copyright comment Vas Crabb2016-03-211-3/+4
* Make a proper BDF out of uismall font - no need to try and load an orphaned BDC Vas Crabb2016-03-211-0/+2650
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/******************************************************************************

  GOLDEN GAMES / C+M TECHNICS AG
  ------------------------------

  Driver by Roberto Fresca.


  Games running on this hardware:

  * Swiss Poker ('50 SG-.10', V2.5), 1990, Golden Games / C+M Technics AG.
  * Movie Card,                      1998, Golden Games / C+M Technics AG.


*******************************************************************************


  Hardware Notes:
  ---------------

  Swiss Card CPU Board...
  Stickered "GOLDEN GAMES 288"

  CPU: 1x MC68000P8.               [IC2]
  SND: 1x Microchip AY38910A.      [IC18]
       1x LM380N (audio amp).

  RAM: 2x HM62256LP-10             [IC4, IC5]

  OTHER:
  1x EF6840P (timer)               [IC3]
  1x unknown GAL labeled "CM 1.2"  [IC8]
  1x 8.000 MHz Xtal.               [Q1]


  CPU Board layout:
  ,----------------------------------------------------------------------------------------.
  |  |!!!!!!!!|   |!!!!!!!!|    |!!!!!!!!|   |!!!!!!!!|    |!!!!!!!!!!|     |||||||||||    |
  |  '--------'   '--------'    '--------'   '--------'    '----------'     '---------'    |
  |                                                                                        |
  |                                                                                  .--.  |
  | .--------.    .--------.   .--------.    .--------.                              |LM|  |
  | |ULN2803A|    |ULN2803A|   |ULN2803A|    |ULN2803A|                              |38|  |
  | '--------'    '--------'   '--------'    '--------'                              |0N|  |
  |  .---------.     .---------.       .---------.  .--------. .--------. .--------. '--'  |
  |  |74HC273AP|     |74HC251AP|       |74HC273AP|  |ULN2003A| |ULN2803A| |HC251AP |       |
  |  '---------'     '---------'       '---------'  '--------' '--------' '--------'       |
  |                                                   .--------.  .---------.   .--------. |
  |                                                   |HC259AP |  |74HC273AP|   |ZH 436 E| |
  |                                                   '--------'  '---------'   '--------' |
  |                      GOLDEN GAMES 238                                                  |
  |                         CPU 68000                                     .--------------. |
  |                      .----.  .--.    .--.       .--------. .--.       |              | |
  |                      |ICL1|  |74|    |74|       |        | |..|       |  AY38912A/P  | |
  |                      '----'  |HC|    |HC|       |        | |..|       |              | |
  |  .---------. .---------..--. |13|    |14|       |        | |..|       '--------------' |
  |  |74HC273P | |74HC273AP||74| |8A|    |B1|       |        | |..|                        |
  |  '---------' '---------'|HC| |N |    |  |       |        | |..|       .--------------. |
  |                         |13| '--'    '--'       |        | |..|       |              | |
  |  .---------.            |8A|                    | MC     | |..|       | HM62256LP_10 | |
  |  |ULN2803A |            |N |         .--.       |        | |..|       |              | |
  |  '---------'            '--' .--.    |74|       | 68000  | |..|       '--------------' |
  |             .------.         |G |    |HC|       |        | |..|                        |
  |             |HC238B|    .--. |A |    |20|       |    P8  | |..|                        |
  |             '------'    |74| |L |    |P |       |        | |..|                        |
  |                         |HC| |  |    '--'       |        | |..|                        |
  |                         |13| |20|               |        | |..|       .--------------. |
  |                         |9N| |V8|    .--.       |        | |..|       |              | |
  |                         '--' |  |    |74|       |        | |..|       | HM62256LP_10 | |
  |                              '--'    |HC|       |        | |..|       |              | |
  |                                      |05|       |        | |..|       '--------------' |
  |                                      '--'       |        | |..|                        |
  |                       .--.                      |        | |..|       .--------------. |
  |                       |HC|   .------.           |        | |..|       |              | |
  |                       |16|   |HC32AP|           |        | |..|       |   EF6840P    | |
  |                       |1A|   '------'           '--------' '--'       |              | |
  |                       '--'   .------.                                 '--------------' |
  |                              |HC4066|   .-------.                                      |
  |                              '------'   |HC251AP|    .--.  .-------.                   |
  |                     .------. .------.   '-------'    |SG|  |74HC93P|    .------------. |
  |                     |HC251A| |HC251A|                |51|  '-------'    |            | |
  |                     '------' '------'                |  |               |  MC6850P   | |
  |                                                      '--'  .-------.    |            | |
  |                                                            |74HC08A|    '------------' |
  |                                                            '-------'    .---.          |
  |                                         .--------.                      |DS1|          |
  |                                         |HC244AP |                      '---'          |
  |                                         '--------'                                     |
  |   .------------------.   .---------.   .----------.   .---------.    .----------.      |
  |   |!!!!!!!!!!!!!!!!!!|   |!!!!!!!!!|   |!!!!!!!!!!|   |!!!!!!!!!|    |!!!!!!!!!!|      |
  '----------------------------------------------------------------------------------------'

  ICL1 = ICL7673CPA
  DS1  = DS1232
  SG51 = SG51K 0382 80000 MHz



  Swiss Card Graphics Board...
  Stickered "960210"

  2x Xilinx XC7336-15
  3x TC551001BPL-70L (128K x 8 static RAM).
  2x ROMs.
  1x 3x32 Female connector.
  1x 6.000 MHz. Xtal.


  Graphics Board layout:

  .-------------------------------------------------------------------------.
  |                                                                         |
  |                                                               .-------. |
  | .--. .---------.                                              |V2.5_HI| |
  | |74| | XILINX  |                                              |.PR    | |
  | |HC| |XC7336-15|                                              |       | |
  | |12| |  PC44C  |                                              |       | |
  | |5N| | X64654M |  .-----------------------------------------. |       | |
  | |  | | ACG9539 |  |:::::::::::::::::::::::::::::::::::::::::| |       | |
  | '--' '---------'  '-----------------------------------------' |       | |
  |                                                               |       | |
  |      .--.                                                     |27C256 | |
  |      |74|                                                     '-------' |
  |      |HC|                                                               |
  |.--.  |27|         .---------.    .--. .--.  .--. .--.                   |
  ||..|  |3N|         |IQXO-100C|    |74| |74|  |74| |74|         .-------. |
  ||..|  |  |         |6.000 MHz|    |HC| |HC|  |HC| |HC|         |V2.5_LO| |
  ||..|  |  |         '---------'    |24| |24|  |24| |24|         |.PR    | |
  ||..|  |  |                        |4N| |5N|  |4N| |5N|         |       | |
  |'--'  '--'                   .--. |  | |  |  |  | |  |  .--.   |       | |
  |                             |74| |  | |  |  |  | |  |  |74|   |       | |
  | .-------.   .---------.     |HC| '--' '--'  '--' '--'  |HC|   |       | |
  | |TOSHIBA|   | XILINX  |     |24|                       |24|   |       | |
  | |       |   |XC7336-15|     |4N|   .-------..-------.  |4N|   |       | |
  | |TC     |   |  PC44C  |     |  |   |TOSHIBA||TOSHIBA|  |  |   |27C256 | |
  | |551001 |   | A40490A |     |  |   |       ||       |  '--'   '-------' |
  | |BPL-70L|   | ACG9541 |     '--'   |TC     ||TC     |                   |
  | |       |   '---------'            |551001 ||551001 |                   |
  | |       |                   .--.   |BPL-70L||BPL-70L|  .--.             |
  | |       |                   |74|   |       ||       |  |74|             |
  | |       |                   |HC|   |       ||       |  |HC|             |
  | |       |                   |24|   |       ||       |  |24|             |
  | |       |                   |4N|   |       ||       |  |4N|             |
  | '-------'                   |  |   |       ||       |  |  |             |
  |                             |  |   |       ||       |  |  |             |
  |                             '--'   '-------''-------'  '--'             |
  '-------------------------------------------------------------------------'


  Swiss Card Program Module...

  2x (LO-HI) ROMs.
  1x PALC22V10D.
  1x 3x32 Male connector.

  Program Board layout
  .--------------------------------------.
  |                                      |
  | .--------------.    .--------------. |
  | |V1.0_LO.GR    |    |V1.0_HI.GR    | |
  | |              |    |              | |
  | |        27C512|    |        27C512| |
  | '--------------'    '--------------' |
  |                                      |
  |          .---------------.           |
  |    LOW   |PALC22V10D-15PC|    HIGH   |
  |          '---------------'           |
  |--------------------------------------|
  ||||||||||||||||||||||||||||||||||||||||
  '--------------------------------------'


*******************************************************************************


  Movie Card CPU Board...
  Etched: "Golden Games"
  Stickered "JQ 6.01"

  CPU: 1x MC68000P8.
  SND: 1x YM2149F.
       1x LM380N (audio amp).

  RAM: 2x 84256A-10

  OTHER:
  1x EF6840P (timer)
  1x Xilinx XC9572 PC84AEM9917 (In-System Programmable CPLD)
  2x Philips SCN68681C1A44 (Dual asynchronous receiver/transmitter)

  1x DS1307

  1x 8.000 MHz Xtal.
  1x Unreadable Xtal.
  1x Unreadable Xtal.


*******************************************************************************


  *** Game Notes ***




*******************************************************************************

  --------------------
  ***  Memory Map  ***
  --------------------


*******************************************************************************


  DRIVER UPDATES:


  [2010-09-12]

  - Initial release.
  - Added technical notes.


  TODO:



*******************************************************************************/


#define MASTER_CLOCK	XTAL_8MHz	/* from CPU Board */
#define SECONDARY_CLOCK	XTAL_6MHz	/* from GFX Board */

#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "sound/ay8910.h"


class goldngam_state : public driver_device
{
public:
	goldngam_state(const machine_config &mconfig, device_type type, const char *tag)
		: driver_device(mconfig, type, tag) ,
		m_videoram(*this, "videoram"){ }

	required_shared_ptr<UINT16> m_videoram;
	DECLARE_READ16_MEMBER(unk_r);
	virtual void video_start();
	virtual void palette_init();
	UINT32 screen_update_goldngam(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};


/*************************
*     Video Hardware     *
*************************/

void goldngam_state::video_start()
{

}

UINT32 goldngam_state::screen_update_goldngam(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{

	int x, y;

	// ERROR: This cast is NOT endian-safe without the use of BYTE/WORD/DWORD_XOR_* macros!
	UINT8 *tmp = reinterpret_cast<UINT8 *>(m_videoram.target());
	int index = 0;

	for(y = 0; y < 512; ++y)
	{
		for(x = 0; x < 384; ++x)
		{
		  bitmap.pix16(y, x) = tmp[index ^ 1]; /* swapped bytes in 16 bit word */
			++index;
		}
	}

	return 0;
}


void goldngam_state::palette_init()
{

}



/*************************
* Memory Map Information *
*************************/

READ16_MEMBER(goldngam_state::unk_r)
{
    int test1 = (machine().rand() & 0xae00);
//  popmessage("VAL = %02x", test1);

	return test1;
}

static ADDRESS_MAP_START( swisspkr_map, AS_PROGRAM, 16, goldngam_state )
	AM_RANGE(0x000000, 0x03ffff) AM_ROM
	AM_RANGE(0x200000, 0x20ffff) AM_RAM
	AM_RANGE(0x400002, 0x400003) AM_NOP // hopper status read ?
	AM_RANGE(0x40000c, 0x40000d) AM_READ(unk_r)
	AM_RANGE(0x40000e, 0x40000f) AM_READ_PORT("DSW2")	// not sure...
	AM_RANGE(0x402000, 0x402001) AM_DEVREAD8_LEGACY("aysnd", ay8910_r, 0x00ff)
	AM_RANGE(0x402000, 0x402003) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_data_w, 0x00ff) //wrong

	AM_RANGE(0xc00000, 0xc3ffff) AM_RAM AM_SHARE("videoram")
	AM_RANGE(0x500200, 0x50020f) AM_RAM //?
	AM_RANGE(0x503000, 0x503001) AM_RAM //int ack ?
	AM_RANGE(0x503002, 0x503003) AM_RAM //int ack ?
	AM_RANGE(0x503006, 0x503007) AM_RAM //int ack ?
ADDRESS_MAP_END


/* unknown R/W:

'maincpu' (0000C8): unmapped program memory word write to 501500 = 0040 & 00FF
'maincpu' (01BDB6): unmapped program memory word write to 401000 = 0300 & FF00
'maincpu' (01BDBE): unmapped program memory word write to 401000 = 5500 & FF00
'maincpu' (01BDC4): unmapped program memory word read from 401002 & FF00
'maincpu' (01BB82): unmapped program memory word write to 402000 = 0008 & 00FF
'maincpu' (01BB88): unmapped program memory word write to 402002 = 0000 & 00FF
'maincpu' (01BB82): unmapped program memory word write to 402000 = 0009 & 00FF
'maincpu' (01BB88): unmapped program memory word write to 402002 = 0000 & 00FF
'maincpu' (01BB82): unmapped program memory word write to 402000 = 000A & 00FF
'maincpu' (01BB88): unmapped program memory word write to 402002 = 0000 & 00FF
'maincpu' (01BA5E): unmapped program memory word write to 402000 = 0007 & 00FF
'maincpu' (01BA66): unmapped program memory word write to 402002 = 007F & 00FF
'maincpu' (01C072): unmapped program memory word write to 400002 = 0100 & FF00
'maincpu' (01C076): unmapped program memory word write to 400000 = 8200 & FF00
'maincpu' (01C07E): unmapped program memory word write to 400004 = 0B00 & FF00
'maincpu' (01C07E): unmapped program memory word write to 400006 = B700 & FF00
'maincpu' (01C084): unmapped program memory word write to 400002 = 0000 & FF00
'maincpu' (01C088): unmapped program memory word write to 400000 = 8300 & FF00
'maincpu' (01C090): unmapped program memory word write to 40000C = FF00 & FF00
'maincpu' (01C090): unmapped program memory word write to 40000E = FF00 & FF00
'maincpu' (01C096): unmapped program memory word write to 400002 = C200 & FF00
'maincpu' (01C09E): unmapped program memory word write to 400008 = 0600 & FF00
'maincpu' (01C09E): unmapped program memory word write to 40000A = 4000 & FF00
'maincpu' (0160DC): unmapped program memory word write to 501500 = 0040 & 00FF
'maincpu' (015102): unmapped program memory word read from 500400 & 00FF
'maincpu' (0151BE): unmapped program memory word write to 401000 = 0300 & FF00
'maincpu' (0151C6): unmapped program memory word write to 401000 = 1500 & FF00
'maincpu' (0151CC): unmapped program memory word read from 401002 & FF00

*/

static ADDRESS_MAP_START( moviecrd_map, AS_PROGRAM, 16, goldngam_state )
	AM_RANGE(0x000000, 0x07ffff) AM_ROM
	AM_RANGE(0x200000, 0x20ffff) AM_RAM
	AM_RANGE(0xc00000, 0xc3ffff) AM_RAM AM_SHARE("videoram")
	AM_RANGE(0x503000, 0x5031ff) AM_RAM //int ack ?
ADDRESS_MAP_END

/*

  502100-502102  YM2149?


*/

/*************************
*      Input Ports       *
*************************/

static INPUT_PORTS_START( goldngam )

	PORT_START("IN0")
	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("IN0-0001")
	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("IN0-0002")
	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("IN0-0004")
	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("IN0-0008")
	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("IN0-0010")
	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("IN0-0020")
	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("IN0-0040")
	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("IN0-0080")
	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("IN0-0100")
	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("IN0-0200")
	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("IN0-0400")
	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) PORT_NAME("IN0-0800")
	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("IN0-1000")
	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("IN0-2000")
	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("IN0-4000")
	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("IN0-8000")

	PORT_START("IN1")
	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("IN1-0001")
	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("IN1-0002")
	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("IN1-0004")
	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("IN1-0008")
	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("IN1-0010")
	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("IN1-0020")
	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) PORT_NAME("IN1-0040")
	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("IN1-0080")
	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("IN1-0100")
	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("IN1-0200")
	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("IN1-0400")
	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("IN1-0800")
	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("IN1-1000")
	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("IN1-2000")
	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("IN1-4000")
	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("IN1-8000")

	PORT_START("DSW1")
	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0001, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0002, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0004, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0008, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0010, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0020, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0040, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0100, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0400, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0800, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x4000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )

	PORT_START("DSW2")
	PORT_DIPNAME( 0x0001, 0x0001, "switch 2" )
	PORT_DIPSETTING(      0x0001, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0002, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0004, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0008, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0010, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0020, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0040, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0100, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0400, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x0800, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x4000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
	PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )

INPUT_PORTS_END


/*************************
*    Graphics Layouts    *
*************************/

/* Used 1bpp gfx just to see the tiles.
   See tiles 1d30 onward...
*/

static const gfx_layout charlayout =
{
	8, 8,
	RGN_FRAC(1,2),
	1,
	{ 0 },
	{ 0, 1, 2, 3, 4, 5, 6, 7 },
	{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
	8*8	/* every char takes 8 consecutive bytes */
};


/******************************
* Graphics Decode Information *
******************************/

static GFXDECODE_START( goldngam )
	GFXDECODE_ENTRY( "maincpu", 0, charlayout, 0, 16 )
GFXDECODE_END


/*************************
*    Machine Drivers     *
*************************/


static const ay8910_interface goldngam_ay8910_interface =
{
	AY8910_LEGACY_OUTPUT,
	AY8910_DEFAULT_LOADS,
	DEVCB_NULL, //r
	DEVCB_NULL, //r
	DEVCB_NULL,
	DEVCB_NULL
};

static MACHINE_CONFIG_START( swisspkr, goldngam_state )

	/* basic machine hardware */
	MCFG_CPU_ADD("maincpu", M68000, MASTER_CLOCK)
	MCFG_CPU_PROGRAM_MAP(swisspkr_map)
	MCFG_CPU_VBLANK_INT_DRIVER("screen", goldngam_state,  irq2_line_hold)

	/* video hardware */
	MCFG_SCREEN_ADD("screen", RASTER)
	MCFG_SCREEN_REFRESH_RATE(60)
	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	MCFG_SCREEN_SIZE(64*8, 64*8)
	MCFG_SCREEN_VISIBLE_AREA(4*8, 43*8-1, 1*8, 37*8-1)	// 312x288
	MCFG_SCREEN_UPDATE_DRIVER(goldngam_state, screen_update_goldngam)

	MCFG_GFXDECODE(goldngam)

	MCFG_PALETTE_LENGTH(512)


	/* sound hardware */
	MCFG_SPEAKER_STANDARD_MONO("mono")

	MCFG_SOUND_ADD("aysnd", AY8910, MASTER_CLOCK/4)
	MCFG_SOUND_CONFIG(goldngam_ay8910_interface)
	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
MACHINE_CONFIG_END


static MACHINE_CONFIG_DERIVED( moviecrd, swisspkr )

	/* basic machine hardware */
	MCFG_CPU_MODIFY("maincpu")
	MCFG_CPU_PROGRAM_MAP(moviecrd_map)
MACHINE_CONFIG_END


/*************************
*        Rom Load        *
*************************/

ROM_START( swisspkr )
	ROM_REGION( 0x40000, "maincpu", 0 ) /* 68000 code */
	ROM_LOAD16_BYTE( "v2.5_hi.pr", 0x00000, 0x10000, CRC(a7f85661) SHA1(aa307bcfe0dfb07120b9711d65916b8689626b00) )
	ROM_LOAD16_BYTE( "v2.5_lo.pr", 0x00001, 0x10000, CRC(142db5d0) SHA1(cc6481a206ed1b0f19cccaab7d6158e81e483c9b) )

	ROM_REGION( 0x40000, "gfx1", 0 )	/* The following ROMs have code for 'Super Cherry' */
	ROM_LOAD16_BYTE( "v1.0_hi.gr", 0x20000, 0x10000, CRC(ea750ab1) SHA1(d1284e7f2628c3aa3de9246e475d45e6be48890e) )
	ROM_LOAD16_BYTE( "v1.0_lo.gr", 0x20001, 0x10000, CRC(d885b965) SHA1(5f2ae3e21cf4e0d20c99cec2dfd3a6f72358535a) )
ROM_END

ROM_START( moviecrd )
	ROM_REGION( 0x80000, "maincpu", 0 ) /* 68000 code */
	ROM_LOAD16_BYTE( "v1.2_hi.pro", 0x20000, 0x20000, CRC(2210dd79) SHA1(007e9930965d6281889fca487f00a1edaac54d85) )
	ROM_CONTINUE(                   0x00000, 0x20000)
	ROM_LOAD16_BYTE( "v1.2_lo.pro", 0x20001, 0x20000, CRC(adb6060f) SHA1(1aff8be7830f61f97720e773eab7985956c7569d) )
	ROM_CONTINUE(                   0x00001, 0x20000)

	ROM_REGION( 0x40000, "gfx1", 0 )
	ROM_LOAD16_BYTE( "v1.2_hi.gfx", 0x00000, 0x10000, CRC(0b62d1a8) SHA1(4156379cc000cbea997b1c21cebea9021fa697b2) )
	ROM_LOAD16_BYTE( "v1.2_lo.gfx", 0x00001, 0x10000, CRC(70e8e9d5) SHA1(c026493b4bd302d389219ba564aafa42fca86491) )
ROM_END


/*************************
*      Game Drivers      *
*************************/

/*    YEAR  NAME      PARENT    MACHINE    INPUT      INIT  ROT    COMPANY                           FULLNAME                          FLAGS */
GAME( 1990, swisspkr, 0,        swisspkr,  goldngam, driver_device,  0,    ROT0, "Golden Games / C+M Technics AG", "Swiss Poker ('50 SG-.10', V2.5)", GAME_NO_SOUND | GAME_NOT_WORKING )
GAME( 1998, moviecrd, 0,        moviecrd,  goldngam, driver_device,  0,    ROT0, "Golden Games / C+M Technics AG", "Movie Card",                      GAME_NO_SOUND | GAME_NOT_WORKING )
}; READ32_MEMBER( next_state::scsictrl_r ) { uint32_t res = (scsictrl << 24) | (scsistat << 16); logerror("scsictrl_read %08x @ %08x (%08x)\n", res, mem_mask, maincpu->pc()); return res; } WRITE32_MEMBER( next_state::scsictrl_w ) { if(ACCESSING_BITS_24_31) { scsictrl = data >> 24; if(scsictrl & 0x02) scsi->reset(); device_t::static_set_clock(*scsi, scsi_clocks[scsictrl >> 6]); logerror("SCSIctrl %dMHz int=%s dma=%s dmadir=%s%s%s dest=%s (%08x)\n", scsi_clocks[scsictrl >> 6]/1000000, scsictrl & 0x20 ? "on" : "off", scsictrl & 0x10 ? "on" : "off", scsictrl & 0x08 ? "read" : "write", scsictrl & 0x04 ? " flush" : "", scsictrl & 0x02 ? " reset" : "", scsictrl & 0x01 ? "wd3392" : "ncr5390", maincpu->pc()); } if(ACCESSING_BITS_16_23) { scsistat = data >> 16; logerror("SCSIstat %02x (%08x)\n", data, maincpu->pc()); } } READ32_MEMBER( next_state::event_counter_r) { // Event counters, around that time, are usually fixed-frequency counters. // This one being 1MHz seems to make sense // The v74 rom seems pretty convinced that it's 20 bits only. if(ACCESSING_BITS_24_31) eventc_latch = machine().time().as_ticks(1000000) & 0xfffff; return eventc_latch; } READ32_MEMBER( next_state::dsp_r) { return 0x7fffffff; } WRITE32_MEMBER( next_state::fdc_control_w ) { logerror("FDC write %02x (%08x)\n", data >> 24, maincpu->pc()); } READ32_MEMBER( next_state::fdc_control_r ) { // Type of floppy present // 0 = no floppy in drive // 1 = ed // 2 = hd // 3 = dd // The rom strangely can't boot on anything else than ED, it has // code for the other densities but forces ED for some mysterious // reason. The kernel otoh behaves as expected. if(fdc) { floppy_image_device *fdev = machine().device<floppy_connector>(":fdc:0")->get_device(); if(fdev->exists()) { uint32_t variant = fdev->get_variant(); switch(variant) { case floppy_image::SSSD: case floppy_image::SSDD: case floppy_image::DSDD: return 3 << 24; case floppy_image::DSHD: return 2 << 24; case floppy_image::DSED: return 1 << 24; } } } return 0 << 24; } READ32_MEMBER( next_state::phy_r ) { logerror("phy_r %d %08x (%08x)\n", offset, phy[offset], maincpu->pc()); return phy[offset] | (0 << 24); } WRITE32_MEMBER( next_state::phy_w ) { COMBINE_DATA(phy+offset); logerror("phy_w %d %08x (%08x)\n", offset, phy[offset], maincpu->pc()); } void next_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { irq_set(29, true); timer_data = timer_next_data; if(timer_ctrl & 0x40000000) timer_start(); else timer_ctrl &= 0x7fffffff; } READ32_MEMBER( next_state::timer_data_r ) { if(timer_ctrl & 0x80000000) timer_update(); return timer_data; } WRITE32_MEMBER( next_state::timer_data_w ) { if(timer_ctrl & 0x80000000) { COMBINE_DATA(&timer_next_data); timer_next_data &= 0xffff0000; } else { COMBINE_DATA(&timer_data); timer_data &= 0xffff0000; } } READ32_MEMBER( next_state::timer_ctrl_r ) { irq_set(29, false); return timer_ctrl; } WRITE32_MEMBER( next_state::timer_ctrl_w ) { bool oldact = timer_ctrl & 0x80000000; COMBINE_DATA(&timer_ctrl); bool newact = timer_ctrl & 0x80000000; if(oldact != newact) { if(oldact) { timer_update(); irq_set(29, false); } else { timer_next_data = timer_data; timer_start(); } } } void next_state::timer_update() { int delta = timer_vbase - (machine().time() - timer_tbase).as_ticks(1000000); if(delta < 0) delta = 0; timer_data = delta << 16; } void next_state::timer_start() { timer_tbase = machine().time(); timer_vbase = timer_data >> 16; timer_tm->adjust(attotime::from_usec(timer_vbase)); } WRITE_LINE_MEMBER(next_state::scc_irq) { irq_set(17, state); } WRITE_LINE_MEMBER(next_state::keyboard_irq) { irq_set(3, state); } WRITE_LINE_MEMBER(next_state::power_irq) { irq_set(2, state); } WRITE_LINE_MEMBER(next_state::nmi_irq) { irq_set(31, state); } WRITE_LINE_MEMBER(next_state::fdc_irq) { irq_set(7, state); } WRITE_LINE_MEMBER(next_state::fdc_drq) { dma_drq_w(1, state); } WRITE_LINE_MEMBER(next_state::net_tx_irq) { irq_set(10, state); } WRITE_LINE_MEMBER(next_state::net_rx_irq) { irq_set(9, state); } WRITE_LINE_MEMBER(next_state::net_tx_drq) { dma_drq_w(17, state); } WRITE_LINE_MEMBER(next_state::net_rx_drq) { dma_drq_w(21, state); } WRITE_LINE_MEMBER(next_state::mo_irq) { irq_set(13, state); } WRITE_LINE_MEMBER(next_state::mo_drq) { dma_drq_w(5, state); } WRITE_LINE_MEMBER(next_state::scsi_irq) { irq_set(12, state); } WRITE_LINE_MEMBER(next_state::scsi_drq) { dma_drq_w(1, state); } WRITE8_MEMBER(next_state::ramdac_w) { switch(offset) { case 0: switch(data) { case 0x05: if(screen_color) irq_set(13, false); else irq_set(5, false); vbl_enabled = false; break; case 0x06: vbl_enabled = true; break; default: fprintf(stderr, "ramdac_w %d, %02x\n", offset, data); break; } break; default: fprintf(stderr, "ramdac_w %d, %02x\n", offset, data); break; } } void next_state::setup(uint32_t _scr1, int size_x, int size_y, int skip, bool color) { scr1 = _scr1; screen_sx = size_x; screen_sy = size_y; screen_skip = skip; screen_color = color; } void next_state::machine_start() { save_item(NAME(scr2)); save_item(NAME(irq_status)); save_item(NAME(irq_mask)); save_item(NAME(irq_level)); save_item(NAME(phy)); save_item(NAME(scsictrl)); save_item(NAME(scsistat)); save_item(NAME(timer_tbase)); save_item(NAME(timer_vbase)); save_item(NAME(timer_data)); save_item(NAME(timer_next_data)); save_item(NAME(timer_ctrl)); save_item(NAME(eventc_latch)); save_item(NAME(esp)); for(int i=0; i<0x20; i++) { save_item(NAME(dma_slots[i].start), i); save_item(NAME(dma_slots[i].limit), i); save_item(NAME(dma_slots[i].chain_start), i); save_item(NAME(dma_slots[i].chain_limit), i); save_item(NAME(dma_slots[i].current), i); save_item(NAME(dma_slots[i].state), i); save_item(NAME(dma_slots[i].supdate), i); save_item(NAME(dma_slots[i].restart), i); save_item(NAME(dma_slots[i].drq), i); } timer_tm = timer_alloc(0); } void next_state::machine_reset() { scr2 = 0; irq_status = 0; irq_mask = 0; irq_level = 0; esp = 0; scsictrl = 0; scsistat = 0; phy[0] = phy[1] = 0; eventc_latch = 0; timer_vbase = 0; timer_data = 0; timer_next_data = 0; timer_ctrl = 0; vbl_enabled = true; dma_drq_w(4, true); // soundout } WRITE_LINE_MEMBER(next_state::vblank_w) { if(vbl_enabled) { if(screen_color) irq_set(13, state); else irq_set(5, state); } } static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("user1", 0) AM_RANGE(0x01000000, 0x0101ffff) AM_ROM AM_REGION("user1", 0) AM_RANGE(0x02000000, 0x020001ff) AM_MIRROR(0x300200) AM_READWRITE(dma_ctrl_r, dma_ctrl_w) AM_RANGE(0x02004000, 0x020041ff) AM_MIRROR(0x300200) AM_READWRITE(dma_regs_r, dma_regs_w) AM_RANGE(0x02006000, 0x0200600f) AM_MIRROR(0x300000) AM_DEVICE8("net", mb8795_device, map, 0xffffffff) // AM_RANGE(0x02006010, 0x02006013) AM_MIRROR(0x300000) memory timing AM_RANGE(0x02007000, 0x02007003) AM_MIRROR(0x300000) AM_READ(irq_status_r) AM_RANGE(0x02007800, 0x02007803) AM_MIRROR(0x300000) AM_READWRITE(irq_mask_r,irq_mask_w) AM_RANGE(0x02008000, 0x02008003) AM_MIRROR(0x300000) AM_READ(dsp_r) AM_RANGE(0x0200c000, 0x0200c003) AM_MIRROR(0x300000) AM_READ(scr1_r) AM_RANGE(0x0200c800, 0x0200c803) AM_MIRROR(0x300000) AM_READ(rom_map_r) AM_RANGE(0x0200d000, 0x0200d003) AM_MIRROR(0x300000) AM_READWRITE(scr2_r,scr2_w) // AM_RANGE(0x0200d800, 0x0200d803) AM_MIRROR(0x300000) RMTINT AM_RANGE(0x0200e000, 0x0200e00b) AM_MIRROR(0x300000) AM_DEVICE("keyboard", nextkbd_device, amap) // AM_RANGE(0x0200f000, 0x0200f003) AM_MIRROR(0x300000) printer // AM_RANGE(0x02010000, 0x02010003) AM_MIRROR(0x300000) brightness AM_RANGE(0x02012000, 0x0201201f) AM_MIRROR(0x300000) AM_DEVICE8("mo", nextmo_device, map, 0xffffffff) AM_RANGE(0x02014000, 0x0201400f) AM_MIRROR(0x300000) AM_DEVICE8("scsibus:7:ncr5390", ncr5390_device, map, 0xffffffff) AM_RANGE(0x02014020, 0x02014023) AM_MIRROR(0x300000) AM_READWRITE(scsictrl_r, scsictrl_w) AM_RANGE(0x02016000, 0x02016003) AM_MIRROR(0x300000) AM_READWRITE(timer_data_r, timer_data_w) AM_RANGE(0x02016004, 0x02016007) AM_MIRROR(0x300000) AM_READWRITE(timer_ctrl_r, timer_ctrl_w) AM_RANGE(0x02018000, 0x02018003) AM_MIRROR(0x300000) AM_DEVREADWRITE8("scc", scc8530_t, reg_r, reg_w, 0xffffffff) // AM_RANGE(0x02018004, 0x02018007) AM_MIRROR(0x300000) SCC CLK // AM_RANGE(0x02018190, 0x02018197) AM_MIRROR(0x300000) warp 9c DRAM timing // AM_RANGE(0x02018198, 0x0201819f) AM_MIRROR(0x300000) warp 9c VRAM timing AM_RANGE(0x0201a000, 0x0201a003) AM_MIRROR(0x300000) AM_READ(event_counter_r) // EVENTC // AM_RANGE(0x020c0000, 0x020c0004) AM_MIRROR(0x300000) BMAP AM_RANGE(0x020c0030, 0x020c0037) AM_MIRROR(0x300000) AM_READWRITE(phy_r, phy_w) AM_RANGE(0x04000000, 0x07ffffff) AM_RAM //work ram // AM_RANGE(0x0c000000, 0x0c03ffff) video RAM w A+B-AB function // AM_RANGE(0x0d000000, 0x0d03ffff) video RAM w (1-A)B function // AM_RANGE(0x0e000000, 0x0e03ffff) video RAM w ceil(A+B) function // AM_RANGE(0x0f000000, 0x0f03ffff) video RAM w AB function // AM_RANGE(0x10000000, 0x1003ffff) main RAM w A+B-AB function // AM_RANGE(0x14000000, 0x1403ffff) main RAM w (1-A)B function // AM_RANGE(0x18000000, 0x1803ffff) main RAM w ceil(A+B) function // AM_RANGE(0x1c000000, 0x1c03ffff) main RAM w AB function ADDRESS_MAP_END static ADDRESS_MAP_START( next_0b_m_nofdc_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_mem) AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram") ADDRESS_MAP_END static ADDRESS_MAP_START( next_fdc_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_mem) AM_RANGE(0x02014100, 0x02014107) AM_MIRROR(0x300000) AM_DEVICE8("fdc", n82077aa_device, map, 0xffffffff) AM_RANGE(0x02014108, 0x0201410b) AM_MIRROR(0x300000) AM_READWRITE(fdc_control_r, fdc_control_w) ADDRESS_MAP_END static ADDRESS_MAP_START( next_0b_m_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_fdc_mem) AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram") ADDRESS_MAP_END static ADDRESS_MAP_START( next_0c_m_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_fdc_mem) AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_SHARE("vram") ADDRESS_MAP_END static ADDRESS_MAP_START( next_0c_c_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_fdc_mem) AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_SHARE("vram") AM_RANGE(0x02018180, 0x02018183) AM_MIRROR(0x300000) AM_WRITE8(ramdac_w, 0xffffffff) ADDRESS_MAP_END static ADDRESS_MAP_START( next_2c_c_mem, AS_PROGRAM, 32, next_state ) AM_IMPORT_FROM(next_fdc_mem) AM_RANGE(0x2c000000, 0x2c1fffff) AM_RAM AM_SHARE("vram") AM_RANGE(0x02018180, 0x02018183) AM_MIRROR(0x300000) AM_WRITE8(ramdac_w, 0xffffffff) ADDRESS_MAP_END /* Input ports */ static INPUT_PORTS_START( next ) INPUT_PORTS_END FLOPPY_FORMATS_MEMBER( next_state::floppy_formats ) FLOPPY_PC_FORMAT FLOPPY_FORMATS_END static SLOT_INTERFACE_START( next_floppies ) SLOT_INTERFACE( "35ed", FLOPPY_35_ED ) SLOT_INTERFACE_END static SLOT_INTERFACE_START( next_scsi_devices ) SLOT_INTERFACE("cdrom", NSCSI_CDROM) SLOT_INTERFACE("harddisk", NSCSI_HARDDISK) SLOT_INTERFACE_INTERNAL("ncr5390", NCR5390) SLOT_INTERFACE_END void next_state::ncr5390(device_t *device) { devcb_base *devcb; (void)devcb; MCFG_DEVICE_CLOCK(10000000) MCFG_NCR5390_IRQ_HANDLER(DEVWRITELINE(":", next_state, scsi_irq)) MCFG_NCR5390_DRQ_HANDLER(DEVWRITELINE(":", next_state, scsi_drq)) } MACHINE_CONFIG_START(next_state::next_base) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_REFRESH_RATE(60) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */ MCFG_SCREEN_UPDATE_DRIVER(next_state, screen_update) MCFG_SCREEN_SIZE(1120, 900) MCFG_SCREEN_VISIBLE_AREA(0, 1120-1, 0, 832-1) MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(next_state, vblank_w)) // devices MCFG_NSCSI_BUS_ADD("scsibus") MCFG_DEVICE_ADD("rtc", MCCS1850, XTAL(32'768)) MCFG_DEVICE_ADD("scc", SCC8530, XTAL(25'000'000)) MCFG_Z8530_INTRQ_CALLBACK(WRITELINE(next_state, scc_irq)) MCFG_DEVICE_ADD("keyboard", NEXTKBD, 0) MCFG_NEXTKBD_INT_CHANGE_CALLBACK(WRITELINE(next_state, keyboard_irq)) MCFG_NEXTKBD_INT_POWER_CALLBACK(WRITELINE(next_state, power_irq)) MCFG_NEXTKBD_INT_NMI_CALLBACK(WRITELINE(next_state, nmi_irq)) MCFG_NSCSI_ADD("scsibus:0", next_scsi_devices, "harddisk", false) MCFG_NSCSI_ADD("scsibus:1", next_scsi_devices, "cdrom", false) MCFG_NSCSI_ADD("scsibus:2", next_scsi_devices, nullptr, false) MCFG_NSCSI_ADD("scsibus:3", next_scsi_devices, nullptr, false) MCFG_NSCSI_ADD("scsibus:4", next_scsi_devices, nullptr, false) MCFG_NSCSI_ADD("scsibus:5", next_scsi_devices, nullptr, false) MCFG_NSCSI_ADD("scsibus:6", next_scsi_devices, nullptr, false) MCFG_NSCSI_ADD("scsibus:7", next_scsi_devices, "ncr5390", true) MCFG_DEVICE_CARD_MACHINE_CONFIG("ncr5390", ncr5390) MCFG_DEVICE_ADD("net", MB8795, 0) MCFG_MB8795_TX_IRQ_CALLBACK(WRITELINE(next_state, net_tx_irq)) MCFG_MB8795_RX_IRQ_CALLBACK(WRITELINE(next_state, net_rx_irq)) MCFG_MB8795_TX_DRQ_CALLBACK(WRITELINE(next_state, net_tx_drq)) MCFG_MB8795_RX_DRQ_CALLBACK(WRITELINE(next_state, net_rx_drq)) MCFG_DEVICE_ADD("mo", NEXTMO, 0) MCFG_NEXTMO_IRQ_CALLBACK(WRITELINE(next_state, mo_irq)) MCFG_NEXTMO_DRQ_CALLBACK(WRITELINE(next_state, mo_drq)) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::next, next_base) MCFG_CPU_ADD("maincpu", M68030, XTAL(25'000'000)) MCFG_CPU_PROGRAM_MAP(next_0b_m_nofdc_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::next_fdc_base, next_base) MCFG_N82077AA_ADD("fdc", n82077aa_device::MODE_PS2) MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(next_state, fdc_irq)) MCFG_UPD765_DRQ_CALLBACK(WRITELINE(next_state, fdc_drq)) MCFG_FLOPPY_DRIVE_ADD("fdc:0", next_floppies, "35ed", next_state::floppy_formats) // software list MCFG_SOFTWARE_LIST_ADD("flop_list", "next") MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nexts, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(25'000'000)) MCFG_CPU_PROGRAM_MAP(next_0b_m_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nexts2, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(25'000'000)) MCFG_CPU_PROGRAM_MAP(next_0b_m_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nextsc, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(25'000'000)) MCFG_CPU_PROGRAM_MAP(next_2c_c_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nextst, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(33'000'000)) MCFG_CPU_PROGRAM_MAP(next_0b_m_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nextstc, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(33'000'000)) MCFG_CPU_PROGRAM_MAP(next_0c_c_mem) MCFG_SCREEN_MODIFY("screen") MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nextct, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(33'000'000)) MCFG_CPU_PROGRAM_MAP(next_0c_m_mem) MACHINE_CONFIG_END MACHINE_CONFIG_DERIVED(next_state::nextctc, next_fdc_base) MCFG_CPU_ADD("maincpu", M68040, XTAL(33'000'000)) MCFG_CPU_PROGRAM_MAP(next_0c_c_mem) MCFG_SCREEN_MODIFY("screen") MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1) MACHINE_CONFIG_END /* ROM definition */ #define ROM_NEXT_V1 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v12", "v1.2" ) /* MAC address/serial number word at 0xC: 005AD0 */ \ ROMX_LOAD( "rev_1.2.bin", 0x0000, 0x10000, CRC(7070bd78) SHA1(e34418423da61545157e36b084e2068ad41c9e24), ROM_BIOS(1)) /* Label: "(C) 1990 NeXT, Inc. // All Rights Reserved. // Release 1.2 // 1142.02", underlabel exists but unknown */ \ ROM_SYSTEM_BIOS( 1, "v10", "v1.0 v41" ) /* MAC address/serial number word at 0xC: 003090 */ \ ROMX_LOAD( "rev_1.0_v41.bin", 0x0000, 0x10000, CRC(54df32b9) SHA1(06e3ecf09ab67a571186efd870e6b44028612371), ROM_BIOS(2)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", underlabel: "MYF // 1.0.41 // 0D5C" */ \ ROM_SYSTEM_BIOS( 2, "v10p", "v1.0 v41 alternate" ) /* MAC address/serial number word at 0xC: 0023D9 */ \ ROMX_LOAD( "rev_1.0_proto.bin", 0x0000, 0x10000, CRC(f44974f9) SHA1(09eaf9f5d47e379cfa0e4dc377758a97d2869ddc), ROM_BIOS(3)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", no underlabel */ #define ROM_NEXT_V2 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v25", "v2.5 v66" ) /* MAC address/serial number word at 0xC: 00F302 */ \ ROMX_LOAD( "rev_2.5_v66.bin", 0x0000, 0x20000, CRC(f47e0bfe) SHA1(b3534796abae238a0111299fc406a9349f7fee24), ROM_BIOS(1)) \ ROM_SYSTEM_BIOS( 1, "v24", "v2.4 v65" ) /* MAC address/serial number word at 0xC: 00A634 */ \ ROMX_LOAD( "rev_2.4_v65.bin", 0x0000, 0x20000, CRC(74e9e541) SHA1(67d195351288e90818336c3a84d55e6a070960d2), ROM_BIOS(2)) \ ROM_SYSTEM_BIOS( 2, "v22", "v2.2 v63" ) /* MAC address/serial number word at 0xC: 00894C */ \ ROMX_LOAD( "rev_2.2_v63.bin", 0x0000, 0x20000, CRC(739d7c07) SHA1(48ffe54cf2038782a92a0850337c5c6213c98571), ROM_BIOS(3)) /* Label: "(C) 1990 NeXT Computer, Inc. // All Rights Reserved. // Release 2.1 // 2918.AB" */ \ ROM_SYSTEM_BIOS( 3, "v21", "v2.1 v59" ) /* MAC address/serial number word at 0xC: 0072FE */ \ ROMX_LOAD( "rev_2.1_v59.bin", 0x0000, 0x20000, CRC(f20ef956) SHA1(09586c6de1ca73995f8c9b99870ee3cc9990933a), ROM_BIOS(4)) \ ROM_SYSTEM_BIOS( 4, "v12", "v1.2 v58" ) /* MAC address/serial number word at 0xC: 006372 */ \ ROMX_LOAD( "rev_1.2_v58.bin", 0x0000, 0x20000, CRC(b815b6a4) SHA1(97d8b09d03616e1487e69d26609487486db28090), ROM_BIOS(5)) /* Label: "V58 // (C) 1990 NeXT, Inc. // All Rights Reserved // Release 1.2 // 1142.02" */ #define ROM_NEXT_V3 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v33", "v3.3 v74" ) /* MAC address/serial number word at 0xC: 123456 */ \ ROMX_LOAD( "rev_3.3_v74.bin", 0x0000, 0x20000, CRC(fbc3a2cd) SHA1(a9bef655f26f97562de366e4a33bb462e764c929), ROM_BIOS(1)) \ ROM_SYSTEM_BIOS( 1, "v32", "v3.2 v72" ) /* MAC address/serial number word at 0xC: 012f31 */ \ ROMX_LOAD( "rev_3.2_v72.bin", 0x0000, 0x20000, CRC(e750184f) SHA1(ccebf03ed090a79c36f761265ead6cd66fb04329), ROM_BIOS(2)) \ ROM_SYSTEM_BIOS( 2, "v30", "v3.0 v70" ) /* MAC address/serial number word at 0xC: 0106e8 */ \ ROMX_LOAD( "rev_3.0_v70.bin", 0x0000, 0x20000, CRC(37250453) SHA1(a7e42bd6a25c61903c8ca113d0b9a624325ee6cf), ROM_BIOS(3)) ROM_START(next) ROM_NEXT_V1 ROM_END ROM_START(nexts) ROM_NEXT_V2 ROM_END ROM_START(nexts2) ROM_NEXT_V2 ROM_END ROM_START(nextsc) ROM_NEXT_V2 ROM_END ROM_START(nextst) ROM_NEXT_V3 ROM_END ROM_START(nextstc) ROM_NEXT_V3 ROM_END ROM_START(nextct) ROM_NEXT_V3 ROM_END ROM_START(nextctc) ROM_NEXT_V3 ROM_END DRIVER_INIT_MEMBER(next_state,next) { setup(0x00010002, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nexts) { setup(0x00011002, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nexts2) { setup(0x00012102, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nextsc) { setup(0x00013102, 1120, 832, 16, true); } DRIVER_INIT_MEMBER(next_state,nextst) { setup(0x00014103, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nextstc) { setup(0x00015103, 832, 624, 0, true); } DRIVER_INIT_MEMBER(next_state,nextct) { setup(0x00018103, 1120, 832, 0, false); } DRIVER_INIT_MEMBER(next_state,nextctc) { setup(0x00019103, 832, 624, 0, true); } /* Driver */ // YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS COMP( 1987, next, 0, 0, next, next, next_state, next, "Next Software Inc", "NeXT Cube", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( 1990, nexts, 0, 0, nexts, next, next_state, nexts, "Next Software Inc", "NeXTstation", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( 1990, nexts2, nexts, 0, nexts2, next, next_state, nexts2, "Next Software Inc", "NeXTstation (X15 variant)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( 1990, nextsc, nexts, 0, nextsc, next, next_state, nextsc, "Next Software Inc", "NeXTstation color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( 1990, nextst, 0, 0, nextst, next, next_state, nextst, "Next Software Inc", "NeXTstation turbo", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( 1990, nextstc, nextst, 0, nextstc, next, next_state, nextstc, "Next Software Inc", "NeXTstation turbo color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( ????, nextct, nextst, 0, nextct, next, next_state, nextct, "Next Software Inc", "NeXT Cube turbo", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) COMP( ????, nextctc, nextst, 0, nextctc, next, next_state, nextctc, "Next Software Inc", "NeXT Cube turbo color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )