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* plib: don't assume constructors will only throw things derived from ↵ Vas Crabb2019-04-241-1/+1
| | | | | | | | std::exception (nw) funworld.cpp cleanup: (nw) * remove revision history - we use version control for a reason * don't #define things before inluding the PCH, and don't #define generic names before #including anything
* netlist: fix exception handling and uninitialized var. (nw) couriersud2019-04-221-1/+1
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* netlist/plib: Fix memory leak when exception is thrown in constructor. couriersud2019-04-221-0/+17
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* (nw) Clean up the mess on master Vas Crabb2019-03-261-129/+384
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-384/+129
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* netlist: add MOSFET model. [Couriersud] couriersud2019-03-251-1/+1
| | | | | | | | | | | | | | | | | | | - added MOSFET model. Currently capacitances are not modelled. This is a 3-pin model (Bulk connected to Source) with provisions to extend it to 4-pin at a later stage. - Add a capacitor generic model which is charge conserving. Switch netlist to use this model instead of constant capacity model. - Start putting constants into a central place. Please expect minor timing differences due to a different numerical path. The cmos inverter example illustrates the analog implementation of a cmos inverter gate. These were used a lot back in the 70s/80s to generate sinus waves. The model should also be able to better emulate 4066 analog switches. The addition of a relatively simple capacitor model is planned at a later stage. Expect everything from the MOSFET model at the current stage. Wrong results as well as convergence issues and crashes.
* srcclean (nw) Vas Crabb2019-03-241-1/+1
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* netlist: Added B-E and B-C capacitance to EB model. [Couriersud] couriersud2019-03-171-0/+6
| | | | | Despite the overhead - two devices more per transistor - this addition significantly reduces computing time on switching conditions by reducing the needed Newton-Raphson loops dramatically.
* netlist: remove printf. (nw) couriersud2019-03-021-1/+1
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* netlist: memory code refactoring. (nw) couriersud2019-03-011-167/+211
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* netlist: fix bugs in the alignment code. (nw) couriersud2019-02-251-31/+21
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* netlist: tidy changes and better constexpr support for ptime class. (nw) couriersud2019-02-241-32/+32
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* netlist: more alignment related refactoring. (nw) couriersud2019-02-241-40/+84
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* srcclean (nw) Vas Crabb2019-02-241-51/+51
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* netlist: fix visibility issues and more issues reported by tidy. (nw) couriersud2019-02-221-4/+21
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* netlist: memory management. [Couriersud] couriersud2019-02-221-10/+183
| | | | | | | | | | | | | | Memory management in plib is now alignment-aware. All allocations respect c++11 alignas. Selected classes like parray and aligned_vector also provide hints (__builtin_assume_aligned) to g++ and clang. The alignment optimizations have little impact on the current use cases. They only become effective on bigger data processing. What has a measurable impact is memory pooling. This speeds up netlist games like breakout and pong by about 5%. Tested with linux, macosx and windows cross builds. All features are disabled since I can not rule out they may temporarily break more exotic builds.
* netlist: tick off some issues clang-tidy highlights. (nw) couriersud2019-02-181-2/+1
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* netlist: memory pool now supports aligned storage. (nw) couriersud2019-02-161-39/+44
| | | | | | Set USE_MEMPOOL to 1 to try this (max 5% performance increase). For mingw, there is no alignment support. This triggers -Wattribute errors which due to -Werror crash the build.
* netlist: indent. (nw) couriersud2019-02-131-114/+114
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* netlist: memory allocation clean-up. (nw) couriersud2019-02-131-38/+0
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* netlist: More cpp core guidelines alignment. (nw) couriersud2019-02-111-0/+13
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* netlist: Refactoring after adding clang-tidy support to netlist makefile couriersud2019-02-071-2/+2
| | | | | | | - convert macros to c++ code. - order of device creation should not depend on std lib. - some state saving cleanup. - added support for clang-tidy to makefile. - modifications triggered by clang-tidy-9.
* Fix clang-8 warnings. (nw) couriersud2019-01-111-1/+1
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* C++ and minor performance optimizations. (nw) couriersud2019-01-091-4/+4
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* add C++ standard library headers for things that are used (nw) Vas Crabb2019-01-071-1/+3
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* Reorder include order to comply with best practices. (nw) couriersud2017-02-101-1/+2
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* Make sure netlist includes are not found directly on include path. couriersud2017-02-101-4/+11
| | | | Instead, they have to be prefixed by "netlist/". Removed unneeded link librariers for nltool and nlwav along the way. (nw)
* Netlist: It is now possible to have multiple handlers per device ... couriersud2017-02-051-4/+6
| | | | | | | | | | | | | ... for updates. This will make device implementation more flexible and faster. A nice side-effect is that there was some minor (<5%) performance increase already. Each input is now assigned a notification handler. Currently this is update, but going forward this may be a custom handler. In addition - fixed MEMPOOL on OSX - removed dead code - avoid bit-rot - added delegate support for emscripten and arm processors - added delegate support for VS 2015 x64 [Couriersud]
* Solver stuff: couriersud2017-01-291-1/+1
| | | | | | Rewrote mat_cr_t to include data as well. Fixed some bitrot in other parts. Simplified solver creation. (nw)
* Cleanup of includes. (nw) couriersud2017-01-271-3/+0
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* Core refactoring couriersud2017-01-141-0/+1
| | | | | - connect_late ==> connect - register nets where they are created
* Added SIGFPE enabling code to plib/pexception.*. Moved plib exceptions couriersud2017-01-041-54/+0
| | | | | into these files as well. The code uses <cfenv> which is part of c++11 standard. Non-standard glib extensions are currently only used on linux and (i386 or x86_64). (nw)
* Use noexcept in netlist code where appropriate. couriersud2016-08-071-3/+3
| | | | | Use macro NL_NOEXCEPT if debug builds would throw an exception (e.g. by using nl_assert). This is not entirely safe. Going forward, nl_assert should call log first and than throw. (nw)
* Various netlist fixes: couriersud2016-08-061-14/+10
| | | | | - minor include cleanup - fix a memory hole (caused by assign operators) - more C++.
* Netlist updates: couriersud2016-07-211-5/+4
| | | | | | | | | | | | | | | - Removed trampolines (OUTLOGIC, INPLOGIC and friends). - Started using doxygen comment and documentation style. Added doxygen files to documentation folder. - Refactored code triggered by doxygen output. - Moved internal and support classes into namespace detail. - Use an anordered map in parser. - -Wconversion fixes - All done now. - Fixed -Wold-style-cast warnings in netlist code. - Added iterators to pstring. - Moved two macros, added more RAII and improved exceptions. Fixed some bugs in parser code. - Fixed a number of bugs in parser code and exception handling. [Couriersud]
* Moved two macros, added more RAII and improved exceptions. Fixed some couriersud2016-07-091-1/+38
| | | | bugs in parser code. (nw)
* Netlist improvements: couriersud2016-07-011-2/+4
| | | | | | | | | | | | | | | | | | | - nltool now accepts -Ddefine=value to pass on to netlists - improved option handling and added "dummy" options to add grouping and examples in help output. - improved --cmd=listdevices output - Fix dynamic timestepping. This will work with breakout using real capacitor modelling instead of delay devices. Really slow, but very useful to calibrate timings. - Fix an awful bug in timing for delay devices. - Switched to clang 3.8 and made code compile with -Weverything -Werror -Wno-old-style-cast -Wno-padded -Wno-weak-vtables -Wno-missing-variable-declarations -Wno-conversion -Wno-c++98-compat -Wno-float-equal -Wno-cast-align -Wno-global-constructors -Wno-c++98-compat-pedantic -Wno-exit-time-destructors -Wno-format-nonliteral -Wno-weak-template-vtables This was a helpful exercise since it brought forward some serious issues with implicit constructors. [Couriersud]
* Srcclean on netlist files. Avoid the merge massacre. (nw) couriersud2016-06-251-3/+2
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* Remove shared_ptr usage and replace with plib:owned_ptr. Clean up nltool couriersud2016-06-241-10/+19
| | | a bit. (nw)
* Merge netlist_dev branch, all code_refactoring: (nw) couriersud2016-06-161-22/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Object model optimisation. Merge remote-tracking branch 'origin/master' into netlist_dev Fix a merge issue. #if ==> #elif. Ouch. Default PHAS_PMF_INTERNAL=0 for 32bit windows mingw. Change UINT8 to uint_[fast|least|8_t. Move state_var so it can be used by base devices as well. Remove last traces of ATTR_ALIGN. Refactored netlist_time into a template. Removed implicit double assignment to netlist. Doomed to produce bugs. Instead, use netlist_time::from_double. Switch to using proper (i.e. bool type) param_logic_t. Formally differentiate between logic inputs (e.g. switches) and int inputs (e.g. resistor ladders or selection switches). Added parameter USE_DEACTIVATE to truthtable devices. Added more constexpr to netlist_time. Fixed some ifdef code paths. - More c++. - Simplify main processing loop. As a nice side-effect that squeezed out some cycles. - More cycle squeezing. - Removed pvector_t. - Use std::sort. - Refactored netlist state manager. - Introduction of state_var object template to be used on device state members. - Changed remaining save occurrences to state_var. - Rewrote nltool's listdevices command. This allowed removal of one member from devices which served solely for listdevices. - Remove hashmap_t. Fix kidniki regression.
* - More code cleanup. couriersud2016-06-071-2/+2
| | | | | | | | | | | | | | - Dead code removal and minor refactoring. - Simplify. Align naming with stl. Fix somed pedantic warnings. - More STL compatability. - Remove ATTR_HOT and ATTR_COLD. Refactored netlist_time. - Fix long standing workaround which would ignore policy of change-only" propagation. - Rewrote for loops to use auto : semantics. - Truthtable cleanup. (nw) - Get rid of nl_math. Remove nl_util.h and moved contents to plib/putil.h. - Fix standalone build. Refactor ptypes.h. [Couriersud]
* - Minor cosmetic refactoring. Added a "uninitialised array" template to balr0g2016-06-071-19/+19
| | | | | | | | | | | allow in-place creation (for increased locality) of netlist classes. Main use is in truthtable class. - Remove PLIB_NAMESPACE macros. - Remove namespace macros. Use explicit namespace declarations. - Moved device definitions into cpp files. - Moved more device definitions into cpp files. - New prefix "nlid" for include files flags purely internal include files not to be leaked into userland. - Fix factory code.
* Moved more code into plib namespace. (nw) couriersud2016-05-271-26/+108
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* Remove dependency on osd_ticks. Converted palloc and friends into couriersud2016-05-271-60/+16
| | | templates. First effort on a separate plib namespace. (nw)
* Make netlist compile with c++11, use own implementation of make_unique couriersud2016-05-251-0/+7
| | | to avoid c++14. (nw)
* Moved all parameter definitions in constructors. (nw) couriersud2016-05-251-1/+4
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* All netlist devices now follow new syntax. Removed dead code. All sub couriersud2016-05-211-0/+35
| | | | devices are now forced to be initialized in the constructor. Device setup now completely in constructor. Removed start call. [Couriersud]
* Moved netlist from emu to lib (nw) Miodrag Milanovic2015-09-121-0/+120