| Commit message (Collapse) | Author | Age | Files | Lines |
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* fixed DIVS/DIVU opcode so they properly compute SZ flags when requested;
fixes camera wackiness in nbapbp
PPC DRC:
* added support for 4xx protection registers via the MMU
* added TLBH, TLBU, and DEC to the list of registers in the debugger
* turned off "end of transfer" DMA signals in favor of "transfer count 0"
signals; fixes memory-to-memory DMA in fiveside
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In particular, we always clobbered the flags for the subfze instruction, which
broke the nbapbp camera and some other things.
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* Converted sysreg_r/w to 8-bit handlers
* Added hack to make network IRQs work; brings some games back to life
UML:
* Fixed STORE opcode description to allow immediate source operands
x86/x64 back-ends:
* Added flag support to SEXT, ROLAND, ROLINS, LZCNT opcodes
PPC DRC:
* Rewrote lswi/stswi as subroutines
* Made accesses to tempdata explicitly dword or qword
* Fixed SRR0 when generating a syscall
* Removed no longer necessary TESTs on extsb/w, rlwinm, rlwnm, rlwimi, cntlzw
* Fixed bug where the SO flag was not being computed for compares
* Fixed flag computations for mulhw/mulhwu/mullw
* Fixed subtlety of shifts between 32 and 63 in srw/sraw
* Fixed mffs/mtfsf to use FP registers
* Fixed mtfsfi to use the immediate value properly
* Now marking terminal count bit in DMA status register
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* Added simple symbol table to the UML for improved disassembly
* Changed optional disassembler cache parameter to a drcuml object
PPC DRC:
* Added symbols for most common variables
* Fixed bug in handling XER carry flag for subo. forms
* Simplified flag insertion logic for opcodeo. forms
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* Improved disassembly output
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* Added logic to simplify opcodes as much as possible at the UML layer.
* Removed similar logic in the x86 and x64 back-ends.
* Added stricter parameter validation for registers and mapvars
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* Added NOP opcode
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interrupt in the Nintendo Minx cpu core.
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* Removed explicit flag requests from the shorthand opcodes
* Added optimization function to drcuml which is called at block end
* Added logic to compute the necessary flags based on upcoming opcodes
and only select those flags which are required
* Updated the PPC and MIPS3 DRCs to no longer explicitly specify flags
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* Wrote new disassembler based on enhanced opcode info structure.
* Moved disassembler into drcuml.c and removed old code.
* Extended disassembler buffer sizes to at least 256 bytes.
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* Fixed bug where a branch and link to the link register would
overwrite the link register before fetching the target address
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* Added more extensive per-opcode information in preparation for UML
optimization step.
* Made validation more thorough using the extended information.
* Disabled back-end validation for now until it can be revisited
using the new tables.
* Changed GETFLGS encoding so that the mask is in parameter 2 instead
of the flags field.
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The CPU context is not active in a timer callback. You have to set it
yourself.
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- rewrote PowerPC implementation as a dynamic recompiler on top
of the universal recompiler engine
- wrote a front-end to analyze PowerPC code paths and register usage
- wrote a common shared module with C implementations of tricky
CPU behaviors
- added separate CPU types for the variants supported, instead of
relying on a hidden model enum
- rewrote the serial port emulation for the 4xx series to be more
accurate and not rely on separate DMA handlers
- rewrote the MMU handling to implement a software TLB that faults
in pages and handles changed bits appropriately
- implemented emulation of the PowerPC 603's software TLB, which
allows the model 3 games to run without a hack to disable the MMU
Updated the PowerPC disassembler to share constants with the rest of
the core, and to more aggressively use simplified mnemonics, especially
for branches. [Aaron Giles]
Universal recompiler:
- fixed frontend to handle opcode widths different from bus width
- added several new opcodes:
* (D)GETFLGS - copies the UML flags to a destination operand
* FDRNDS - rounds a double precision value to single precision
- renamed several opcodes:
* SETC -> CARRY
* XTRACT -> ROLAND
* INSERT -> ROLINS
- consolidated the following opcodes:
* LOAD?U -> LOAD
* LOAD?S -> LOADS
* STORE? -> STORE
* READ?U -> READ
* READ?M -> READM
* WRITE? -> WRITE
* WRITM? -> WRITEM
* SEXT? -> SEXT
* FTOI?? -> FTOINT
* FFRI? -> FFRINT
* FFRF? -> FFRFLT
- removed some opcodes:
* FLAGS - can be done with GETFLGS/LOAD4/ROLINS
* ZEXT - can be achieved with AND
* READ?S - can be achieved with READ/SEXT
- updated C, x86, and x64 back-ends to support these opcode changes
- updated disassembler to support these opcode changes
MIPS3 dynamic recompiler:
- updated to use new/changed opcode forms
- changed context switch so that it only swaps a single pointer
Konami Hornet changes: [Aaron Giles]
- updated to new PowerPC configurations
- updated some memory handlers to be native 8-bit handlers
- cleaned up JVS implementation to work with new serial code
- added fast RAM for the work RAM to give a small speed boost
Konami GTI Club changes: [Aaron Giles]
- updated to new PowerPC configurations
- updated some memory handlers to be native 8-bit handlers
Konami Viper/ZR107 changes: [Aaron Giles]
- updated to new PowerPC configurations
Sega Model 3 changes: [Aaron Giles]
- updated to new PowerPC configurations
- reimplemented/centralized interrupt handling
- these games are broken for the moment
Fixed crasher due to some Konami games using 8 layers in
the K056832 implementation, even though it was only written
for 4. [Aaron Giles]
Added fisttp opcode to i386 disassembler. [Aaron Giles]
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Nintendo Minx cpu core.
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- Added Microbus support, clock divisor selection, and CKO mode selection to the COP420
- Changed Thayer's Quest keyboard interface to at least slightly resemble the schematics
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Nintendo Minx cpu core.
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- Styling changes
- Added instruction cycle counts.
- Added interrupt support.
- Added HALT support.
- Fixed INT instruction.
- Added incomplete support for DIV and MUL instructions.
- Fixed MOV [#nnnn],BA and MOV [#nnnn],HL instructions.
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mtetrisc and starsldr that they both throw and handle these
exceptions.
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MIPS3 state.
Removed large context in favor of a pointer to the large context to help
improve context switch times.
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1. In the MIPS core:
- renamed struct mips3_config -> mips3_config
- updated all drivers to the new names
- removed MIPS3DRC_STRICT_COP0 flag, which is no longer used
- a few minor cleanups
2. In the CPU interface:
- added new 'intention' parameter to the translate callback to
indicate read/write/fetch access, user/supervisor mode, and
a flag for debugging
- updated all call sites to pass an appropriate value
- updated all CPU cores to the new prototype
3. In the UML:
- added new opcode SETC to set the carry flag from a source bit
- added new opcode BSWAP to swap bytes within a value
- updated C, x86, x64 back-ends to support the new opcodes
- updated disassembler to support the new opcodes
4. In the DRC frontend:
- fixed bug in handling edge case with the PC near the 0 or ~0
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Minor tweaks/cleanups to the MIPS3 drc.
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Changed CPUINFO_INT_MAX_INSTRUCTION_BYTES to prevent crashes during disassembly.
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opcodes. Added CKO general purpose input.
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Subject: [patch] More Machine->machine changes, add machine to irq
callbacks
Hi mamedev,
Here are two more patches to eliminate Machine globals. The first
patch was autogenerated by the attached fixup script. That script has
been updated to catch additional cases which it previously missed
(when Machine is the last parameter to a function or Machine is used
in an assignment). This makes ~50 more files deprecat.h free.
A sizable chunk (~20%) of the remaining uses of the Machine global in
the drivers are due to irq callbacks for sound and machine updates.
Typically such callbacks need to call cpunum_set_input_line, which
requires a machine parameter, so if the callbacks don't pass the
machine parameter, these routines have no choice but to reference the
global variable.
The second patch attempts to address most cases of this by adding the
machine parameter to the callback interfaces. This allows us to
remove #include "deprecat.h" from ~150 files, at the cost of having to
fix up hundreds of callbacks.
In total, these patches reduced the number of files with deprecat.h
from 783 to 575.
~aa
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Subject: saturn CPU patch
Dear MAMEDev,
The attached patch corrects several bugs in the emulation of the saturn
CPU. These corrections are needed to make new HP48 drivers (to be
submitted to MESS imminently) work.
AFAIK, MESS is the only place where this CPU is used, so, the patch
should
not cause any regression in MAME.
The patch is against 0125u1.
Best regards,
-
Antoine Mine
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* Added new opcode LZCNT which returns the number of leading zeros in
a parameter.
* Added new opcode XTRACT which is a combined rotate/mask (basically
rlwinm from PowerPC)
* Added new opcode INSERT which is a combined rotate/mask/blend
(basically rlwimi from PowerPC). Best. Opcode. Ever.
* Updated all back-ends to support these new opcodes.
* Fixed several bugs relating to shifts/rotates and optimizing out
cases incorrectly.
MIPS3 DRC changes:
* Updated to use INSERT and XTRACT where appropriate
* Cleaned up register usage to enable an additional direct mapping;
this means Linux gets 1 now and Windows gets 3
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machine registers if the machine supports it. Currently only x64 on
Windows has enough free registers to do so, though PowerPC will almost
certainly be able to take advantage of this. Gives a minor speedup.
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runtime-only.
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* Fixed front-end so that virtual no-op instructions are still targeted
as branch targets.
* Fixed front-end to mark the beginning of each sequence as needing TLB
validation, since any sequence can be jumped to from anywhere.
* Redid the MIPS3 TLB implementation. Fixed the exception vector and
type handling. Changed the bitfields to directly map from the MIPS TLB
format. Added distinction between TLB fill and TLB valid/modified
exceptions.
* Added separate modes for user, supervisor, and kernel modes. Each mode
does proper verification of addresses now and generates address errors
for invalid accesses.
* Fixed several bugs in the TLB implementation; not everything works
yet but it's a lot closer.
* Made COP0 access checking mandatory in non-kernel modes.
* Fixed several crashes when recompiling virtual no-ops.
* Fixed TLB bug where entries for virtual address 0 were present by
default.
* Fixed bug in the map variable implementation that would sometimes
result in incorrectly recovered values.
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This will be expanded in the future.
Added two new opcodes: SAVE and RESTORE to save and restore the entire
virtual machine state for examination/setup.
Added new back-end function get_info() which returns information from
the back-end about how many actual registers will be mapped.
Fixed a bug that mapped the high a low parts of registers to the same
address. This should help the C back-end run better on big-endian
architectures.
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