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* x86/x64 back-ends: Aaron Giles2008-06-096-25/+101
| | | | | | | | | | | * fixed DIVS/DIVU opcode so they properly compute SZ flags when requested; fixes camera wackiness in nbapbp PPC DRC: * added support for 4xx protection registers via the MMU * added TLBH, TLBU, and DEC to the list of registers in the debugger * turned off "end of transfer" DMA signals in favor of "transfer count 0" signals; fixes memory-to-memory DMA in fiveside
* Fixed bug in x86 and x64 backends where sometimes the flags would be corrupted. Aaron Giles2008-06-082-78/+128
| | | | | In particular, we always clobbered the flags for the subfze instruction, which broke the nbapbp camera and some other things.
* 64-bit GCC compile fixes. R. Belmont2008-06-082-2/+3
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* gticlub: Aaron Giles2008-06-075-184/+251
| | | | | | | | | | | | | | | | | | | | | | | * Converted sysreg_r/w to 8-bit handlers * Added hack to make network IRQs work; brings some games back to life UML: * Fixed STORE opcode description to allow immediate source operands x86/x64 back-ends: * Added flag support to SEXT, ROLAND, ROLINS, LZCNT opcodes PPC DRC: * Rewrote lswi/stswi as subroutines * Made accesses to tempdata explicitly dword or qword * Fixed SRR0 when generating a syscall * Removed no longer necessary TESTs on extsb/w, rlwinm, rlwnm, rlwimi, cntlzw * Fixed bug where the SO flag was not being computed for compares * Fixed flag computations for mulhw/mulhwu/mullw * Fixed subtlety of shifts between 32 and 63 in srw/sraw * Fixed mffs/mtfsf to use FP registers * Fixed mtfsfi to use the immediate value properly * Now marking terminal count bit in DMA status register
* UML: Aaron Giles2008-06-065-22/+139
| | | | | | | | | | * Added simple symbol table to the UML for improved disassembly * Changed optional disassembler cache parameter to a drcuml object PPC DRC: * Added symbols for most common variables * Fixed bug in handling XER carry flag for subo. forms * Simplified flag insertion logic for opcodeo. forms
* UML: Aaron Giles2008-06-064-21/+112
| | | | * Improved disassembly output
* UML: Aaron Giles2008-06-063-590/+540
| | | | | | * Added logic to simplify opcodes as much as possible at the UML layer. * Removed similar logic in the x86 and x64 back-ends. * Added stricter parameter validation for registers and mapvars
* UML: Aaron Giles2008-06-066-2/+32
| | | | * Added NOP opcode
* Fixed handling of the U register in the RET instructions and when taking an ↵ Wilbert Pol2008-06-062-5/+5
| | | | interrupt in the Nintendo Minx cpu core.
* UML: Aaron Giles2008-06-065-355/+273
| | | | | | | | * Removed explicit flag requests from the shorthand opcodes * Added optimization function to drcuml which is called at block end * Added logic to compute the necessary flags based on upcoming opcodes and only select those flags which are required * Updated the PPC and MIPS3 DRCs to no longer explicitly specify flags
* UML: Aaron Giles2008-06-068-591/+235
| | | | | | * Wrote new disassembler based on enhanced opcode info structure. * Moved disassembler into drcuml.c and removed old code. * Extended disassembler buffer sizes to at least 256 bytes.
* PPC DRC: Aaron Giles2008-06-061-6/+10
| | | | | * Fixed bug where a branch and link to the link register would overwrite the link register before fetching the target address
* UML changes: Aaron Giles2008-06-066-225/+311
| | | | | | | | | | * Added more extensive per-opcode information in preparation for UML optimization step. * Made validation more thorough using the extended information. * Disabled back-end validation for now until it can be revisited using the new tables. * Changed GETFLGS encoding so that the mask is in parameter 2 instead of the flags field.
* Fixed compilation error when neither HAS_PPC403GA nor HAS_PPC403GCX are defined Nathan Woods2008-06-061-3/+0
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* Separated condflags into two individual fields. Aaron Giles2008-06-057-778/+950
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* Cleanups/version bump.mame0125u4 Aaron Giles2008-06-0516-377/+377
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* 01859: looping, loopinga, skybump: Fatal Error crash Aaron Giles2008-06-051-2/+10
| | | | | The CPU context is not active in a timer callback. You have to set it yourself.
* PowerPC dynamic recompiler: [Aaron Giles] Aaron Giles2008-06-0526-9107/+10132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - rewrote PowerPC implementation as a dynamic recompiler on top of the universal recompiler engine - wrote a front-end to analyze PowerPC code paths and register usage - wrote a common shared module with C implementations of tricky CPU behaviors - added separate CPU types for the variants supported, instead of relying on a hidden model enum - rewrote the serial port emulation for the 4xx series to be more accurate and not rely on separate DMA handlers - rewrote the MMU handling to implement a software TLB that faults in pages and handles changed bits appropriately - implemented emulation of the PowerPC 603's software TLB, which allows the model 3 games to run without a hack to disable the MMU Updated the PowerPC disassembler to share constants with the rest of the core, and to more aggressively use simplified mnemonics, especially for branches. [Aaron Giles] Universal recompiler: - fixed frontend to handle opcode widths different from bus width - added several new opcodes: * (D)GETFLGS - copies the UML flags to a destination operand * FDRNDS - rounds a double precision value to single precision - renamed several opcodes: * SETC -> CARRY * XTRACT -> ROLAND * INSERT -> ROLINS - consolidated the following opcodes: * LOAD?U -> LOAD * LOAD?S -> LOADS * STORE? -> STORE * READ?U -> READ * READ?M -> READM * WRITE? -> WRITE * WRITM? -> WRITEM * SEXT? -> SEXT * FTOI?? -> FTOINT * FFRI? -> FFRINT * FFRF? -> FFRFLT - removed some opcodes: * FLAGS - can be done with GETFLGS/LOAD4/ROLINS * ZEXT - can be achieved with AND * READ?S - can be achieved with READ/SEXT - updated C, x86, and x64 back-ends to support these opcode changes - updated disassembler to support these opcode changes MIPS3 dynamic recompiler: - updated to use new/changed opcode forms - changed context switch so that it only swaps a single pointer Konami Hornet changes: [Aaron Giles] - updated to new PowerPC configurations - updated some memory handlers to be native 8-bit handlers - cleaned up JVS implementation to work with new serial code - added fast RAM for the work RAM to give a small speed boost Konami GTI Club changes: [Aaron Giles] - updated to new PowerPC configurations - updated some memory handlers to be native 8-bit handlers Konami Viper/ZR107 changes: [Aaron Giles] - updated to new PowerPC configurations Sega Model 3 changes: [Aaron Giles] - updated to new PowerPC configurations - reimplemented/centralized interrupt handling - these games are broken for the moment Fixed crasher due to some Konami games using 8 layers in the K056832 implementation, even though it was only written for 4. [Aaron Giles] Added fisttp opcode to i386 disassembler. [Aaron Giles]
* Fixed flag results for INC, DEC, AND, OR, and XOR instructions in the ↵ Wilbert Pol2008-06-041-4/+36
| | | | Nintendo Minx cpu core.
* Used cpunum_ instead of active_cpu_. Curt Coder2008-06-042-2/+2
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* - Added HALT opcode and halt mode to the COP410 Curt Coder2008-06-045-31/+319
| | | | - Added Microbus support, clock divisor selection, and CKO mode selection to the COP420 - Changed Thayer's Quest keyboard interface to at least slightly resemble the schematics
* Fixed opcodes 45, 4D, 55, 5D, B5, B6, B7, FC, FD, and CF 70-7F in the ↵ Wilbert Pol2008-06-042-17/+17
| | | | Nintendo Minx cpu core.
* Fixed taking of interrupts in the Nintendo Minx cpu core. Wilbert Pol2008-06-021-2/+2
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* Some Nintendo Minx cpu core updates: Wilbert Pol2008-06-015-492/+634
| | | | | | | | | | | - Styling changes - Added instruction cycle counts. - Added interrupt support. - Added HALT support. - Fixed INT instruction. - Added incomplete support for DIV and MUL instructions. - Fixed MOV [#nnnn],BA and MOV [#nnnn],HL instructions.
* Fixed Cause register for bad COP instructions. Verified with Aaron Giles2008-05-301-2/+9
| | | | | mtetrisc and starsldr that they both throw and handle these exceptions.
* 64-bit compile fix (d'oh!) Aaron Giles2008-05-291-4/+4
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* Cleanups for 0.125u3. Aaron Giles2008-05-299-56/+56
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* Removed obsolete comment. Aaron Giles2008-05-291-2/+0
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* Moved implementation-specific state into a pointer hanging off of the core Aaron Giles2008-05-292-341/+366
| | | | | | | MIPS3 state. Removed large context in favor of a pointer to the large context to help improve context switch times.
* Several miscellaneous changes: Aaron Giles2008-05-2919-102/+399
| | | | | | | | | | | | | | | | | | | | | | | | 1. In the MIPS core: - renamed struct mips3_config -> mips3_config - updated all drivers to the new names - removed MIPS3DRC_STRICT_COP0 flag, which is no longer used - a few minor cleanups 2. In the CPU interface: - added new 'intention' parameter to the translate callback to indicate read/write/fetch access, user/supervisor mode, and a flag for debugging - updated all call sites to pass an appropriate value - updated all CPU cores to the new prototype 3. In the UML: - added new opcode SETC to set the carry flag from a source bit - added new opcode BSWAP to swap bytes within a value - updated C, x86, x64 back-ends to support the new opcodes - updated disassembler to support the new opcodes 4. In the DRC frontend: - fixed bug in handling edge case with the PC near the 0 or ~0
* Fixed a benign bug in the x86 DRC backend Nathan Woods2008-05-281-1/+1
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* Added new front-end flag to tag privileged instructions. Aaron Giles2008-05-255-82/+23
| | | | Minor tweaks/cleanups to the MIPS3 drc.
* Fixed memory access in the 80286 cpu core which made i286.h obsolete. ↵ Wilbert Pol2008-05-242-38/+4
| | | | Changed CPUINFO_INT_MAX_INSTRUCTION_BYTES to prevent crashes during disassembly.
* Fixed COP420 instructions XAS and INIL. Fixed cycle count for extended ↵ Curt Coder2008-05-235-56/+86
| | | | opcodes. Added CKO general purpose input.
* Fixed COP420 instructions JSRP, LBI, LQID, and SKT. Draco now has sound. Curt Coder2008-05-223-26/+26
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* Cleanups and version bump. Aaron Giles2008-05-2211-110/+110
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* From: Atari Ace [mailto:atari_ace@verizon.net] Aaron Giles2008-05-223-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subject: [patch] More Machine->machine changes, add machine to irq callbacks Hi mamedev, Here are two more patches to eliminate Machine globals. The first patch was autogenerated by the attached fixup script. That script has been updated to catch additional cases which it previously missed (when Machine is the last parameter to a function or Machine is used in an assignment). This makes ~50 more files deprecat.h free. A sizable chunk (~20%) of the remaining uses of the Machine global in the drivers are due to irq callbacks for sound and machine updates. Typically such callbacks need to call cpunum_set_input_line, which requires a machine parameter, so if the callbacks don't pass the machine parameter, these routines have no choice but to reference the global variable. The second patch attempts to address most cases of this by adding the machine parameter to the callback interfaces. This allows us to remove #include "deprecat.h" from ~150 files, at the cost of having to fix up hundreds of callbacks. In total, these patches reduced the number of files with deprecat.h from 783 to 575. ~aa
* From: Antoine Mine [mailto:Antoine.Mine@ens.fr] Aaron Giles2008-05-227-892/+968
| | | | | | | | | | | | | | | | | | | Subject: saturn CPU patch Dear MAMEDev, The attached patch corrects several bugs in the emulation of the saturn CPU. These corrections are needed to make new HP48 drivers (to be submitted to MESS imminently) work. AFAIK, MESS is the only place where this CPU is used, so, the patch should not cause any regression in MAME. The patch is against 0125u1. Best regards, - Antoine Mine
* Moving old DRC out of the way. Aaron Giles2008-05-222-2/+2
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* UML changes: Aaron Giles2008-05-228-179/+627
| | | | | | | | | | | | | | | | | | * Added new opcode LZCNT which returns the number of leading zeros in a parameter. * Added new opcode XTRACT which is a combined rotate/mask (basically rlwinm from PowerPC) * Added new opcode INSERT which is a combined rotate/mask/blend (basically rlwimi from PowerPC). Best. Opcode. Ever. * Updated all back-ends to support these new opcodes. * Fixed several bugs relating to shifts/rotates and optimizing out cases incorrectly. MIPS3 DRC changes: * Updated to use INSERT and XTRACT where appropriate * Cleaned up register usage to enable an additional direct mapping; this means Linux gets 1 now and Windows gets 3
* Added support in the MIPS recompiler to map a few common registers to Aaron Giles2008-05-212-71/+132
| | | | | | machine registers if the machine supports it. Currently only x64 on Windows has enough free registers to do so, though PowerPC will almost certainly be able to take advantage of this. Gives a minor speedup.
* Minor cleanup. Aaron Giles2008-05-212-14/+0
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* Fix crasher in drcfe.c. Aaron Giles2008-05-201-3/+4
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* Implemented IDT instructions. All invalid instruction asserts are now ↵ Aaron Giles2008-05-201-37/+19
| | | | runtime-only.
* Fixed 80286 databus widths. Wilbert Pol2008-05-191-2/+2
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* 64-bit GCC compile fix. R. Belmont2008-05-191-1/+1
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* Numerous MIPS3 DRC updates: Aaron Giles2008-05-196-221/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fixed front-end so that virtual no-op instructions are still targeted as branch targets. * Fixed front-end to mark the beginning of each sequence as needing TLB validation, since any sequence can be jumped to from anywhere. * Redid the MIPS3 TLB implementation. Fixed the exception vector and type handling. Changed the bitfields to directly map from the MIPS TLB format. Added distinction between TLB fill and TLB valid/modified exceptions. * Added separate modes for user, supervisor, and kernel modes. Each mode does proper verification of addresses now and generates address errors for invalid accesses. * Fixed several bugs in the TLB implementation; not everything works yet but it's a lot closer. * Made COP0 access checking mandatory in non-kernel modes. * Fixed several crashes when recompiling virtual no-ops. * Fixed TLB bug where entries for virtual address 0 were present by default. * Fixed bug in the map variable implementation that would sometimes result in incorrectly recovered values.
* Fixed compiler warning for Apple GCC. R. Belmont2008-05-191-1/+1
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* Added back-end validation mechanism, and a handful of tests as examples. Aaron Giles2008-05-199-195/+1108
| | | | | | | | | | | | | | This will be expanded in the future. Added two new opcodes: SAVE and RESTORE to save and restore the entire virtual machine state for examination/setup. Added new back-end function get_info() which returns information from the back-end about how many actual registers will be mapped. Fixed a bug that mapped the high a low parts of registers to the same address. This should help the C back-end run better on big-endian architectures.
* Fixed a couple of obvious errors in the TLB implementation. Aaron Giles2008-05-171-3/+3
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