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* konami cpu: set EXG/TFR reg A high byte to 0x10 hap2025-04-032-12/+4
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* -cpu/e132xs: Got rid of "Mission Craft flags" compile time option. Vas Crabb2025-04-046-729/+681
| | | | | | | | | | | | | | | | | | | | | | | * Assume ROL sets the V and C flags the same way as SHL and MOVI clears the V flag. -cpu/drcbex64.cpp: Optimise SUB x,0,y to a NEG instruction (gets down to one instruction from two or three a lot of the time). This had been a TODO comment for ages. -cpu/drcbex86.cpp: Got rid of unnecessary std::function use. This substantially reduces the code size and reduces allocations during code generation. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of the intermediate tables in favour of bit switch statements. This improves startup time, reduces code size, and gives the compiler more optimisation opportunities. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of asmjit namespace qualifiers left over from when the class declarations were in headers and hence outside the scope of the using namespace statements.
* cpu/drcbearm64.cpp: orr immediate needs a mask immediate. Vas Crabb2025-04-031-1/+1
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* konami cpu: corrections to EXG/TFR opcode [hap, Jim Westfall] hap2025-04-023-46/+58
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* cpu/drcbearm64.cpp: Fixed build after previous commit. Vas Crabb2025-04-031-1/+1
| | | | Sorry, I'm too tired and didn't git add this. My bad.
* -cpu/e132xs: Miscellaneous fixes/optimisation: Vas Crabb2025-04-036-295/+411
| | | | | | | | | | | | | | | | | | | | | * Fixed behaviour of delayed branches, trace exceptions, and saved PC calculation for error exceptions in delay slots for the interpreter. All instructions in delay slots, branching instructions that can raise exceptions and tracing shoud now (mis)behave properly for the interpreter, including things the manual says you shouldn't do. * Fixed and optimised flag updates for left shifts for the recompiler. * Optimised ROL instruction for the recompiler and made flag calculation equivalent to the interpreter both with and without the "Missioncraft flags" compile-time option. * Only block interrupts for one instruction following a delayed branch. * Optimised the SOFTWARE instruction a little for the recompiler. * Added more SDRAM configuration logging and cleaned up code a bit. -cpu/drcbearm64.cpp: Apply the change from 7efe37938f9dd6a366e to OR and XOR instructions as well, and fix some cases where a 32-bit logical operation would fail to clear the upper bits of a register. -cpu/drcbex64.cpp: Avoid more conditional branches on conditional MOV.
* Add a skeleton for an Oldsmobile Driver Information System (#13525) Devin Acker2025-04-023-1/+27
| | | | | | * New NOT_WORKING machine ---------- Oldsmobile Driver Information System (version 2.2 CH) [Devin Acker]
* mb86233: add /3 clock divider hap2025-04-013-6/+7
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* -cpu/e132xs: Log bus control and memory control setup. Vas Crabb2025-04-016-52/+158
| | | | -cpu/drcbearm64.cpp: Simplified logic for choosing optimal AND strategy.
* -cpu/e132xs.cpp: Improved exception emulation: Vas Crabb2025-04-015-308/+297
| | | | | | | | | | * Fixed behaviour of exceptions in delay slots, and fixed recompiler not updating ILC and P for some exceptions. * Implemented privilege error exception on setting L in user mode for interpreter. -emu/debug, osd/modules/debugger: Added an option to show exceptionpoints in breakpoints windows.
* cpu/m68000: For 68010 only, do not throw away buserr on prefetch (#13405) Adam Billyard2025-03-313-2/+11
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* v60: fix issue with CVTSW overflow flag after rounding hap2025-03-301-6/+9
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* cpu/e132xs: Emulate more exceptions, more recompiler optimisation. Vas Crabb2025-03-316-154/+340
| | | | | | | | | | Emulate pointer error exception on load/store and range error exception on store signed byte/half-word. Further optimised code generation for MOV and MOVI. These are very hot, so this alone gains a further 2% performance or so in the dgPIX games. Also some other miscellaneous cleanup.
* minx: don't crash mame on divide by 0 hap2025-03-302-2/+2
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* -cpu/e132xs: Implemented pointer error exceptions for recompiler. Vas Crabb2025-03-305-462/+428
| | | | | | | | | | * Implemented pointer error exceptions on attempting to use a zero address register (other than SR) in the recompiler. * Also optimised load/store instructions a bit and reduced copy/paste. * Fixed a couple of disassembler issues. -misc/dgpix.cpp: Demoted The X-Files to not working with unemulated protection.
* m6502: like z80, around 10% performance gain by checking unset devcb on ↵ hap2025-03-291-3/+6
| | | | every opcode
* z80: around 10% performance gain by checking if devcb is unset that is ↵ hap2025-03-291-2/+4
| | | | called on every opcode
* -cpu/e132xs: General cleanup and usability improvements: Vas Crabb2025-03-299-1331/+460
| | | | | | | | | | | | | | | | | | | | | | | * Aligned the operand field in disassembly. * Calculate results of immediate values against the PC to make position-independent code easier to read without constantly using a calculator (e.g. this shows destinations for call Rd, PC, imm). * Added more symbols to the UML helper to make logged generated code more readable. * Made single-instruction-per-sequence mode configurable rather than a compile-time option. * Got rid of a criminal amount of copy/paste in the disassembler, and got rid of all the deprecated strcpy calls. * Got rid of some duplicated constants, changed some constants from macros to enumerated values or constexpr globals. * Reduced the amound of stuff in headers that doesn't need to be there. -cpu/drcbex64.cpp: Don't construct std::function objects during code generation - they require allocation. -eolith/eolith.cpp: Turned single-instruction-per-sequence mode on for now until someone works out why turning it off causes Raccoon World to generate so much code it's unplayably slow.
* cpu/e132xs: More recompiler optimisation: Vas Crabb2025-03-284-1123/+1248
| | | | | | | | | | | | | | * Optimised double word shifts. * Optimised the most common PC-relative operations to treat PC as constant when possible, including: - addi PC,imm (long relative branch) - add PC,Rs (computed goto) - sum Rd,PC,imm (calculate PC-relative address) - add Rd,PC (calculate PC-relative address) - ldw.d PC,Rs,imm (PC-relative load) - stw.d PC,Rs,imm (PC-relative store) * Changed template parameters to LlamaCase to make them more visible different to constants/macros.
* cpu/e132xs: More recompiler optimisation: Vas Crabb2025-03-274-299/+137
| | | | | | | | | | * Disabled single-instruction-per-block mode. * Don't bother with delay slot checks where it's unnecessary. * Try to generate a speicalised copy of the delay slot instruction followed by a direct branch of possible. * Use the pre-decoded instruction length for updating the PC. * Specialised versions of the CHK instruction that always or never raise exceptions.
* cpu/e132xs: More fixes and optimisation: Vas Crabb2025-03-276-340/+230
| | | | | | | | | | | | | | | | * Fixed failing to call the debugger instruction hook for the first instruction following an interrupt, exception or trap. * Use UML branches to emulate non-delayed intra-block branches, avoiding the expensive "hash jump". * Re-worked the instruction description code: - Calculate static branch targets for more instructions. - Flag instructions that may cause mode changes. - Don't be so eager to end an instruction sequence. - Removed the local register input/output flags - FP may no be the same when executing the code as when describing instructions. * Fixed interpreter incorrectly setting ILC when an interrupt immediately follows a RET instruction. * Fixed recompiler flag calculation regressions, and optimised a little.
* cpu/e132xs: Fixed some recompiler cycle counts: Vas Crabb2025-03-262-22/+16
| | | | | * Fixed double-counting bug in exception dispatch. * Fixed unsigned comparison of signed values in MUL cycles calculation.
* cpu/e132xs: Made debugging Hyperstone E1 software less painful. Vas Crabb2025-03-264-144/+72
| | | | | * Fixed local register display in debugger (this never worked). * Made disassembler show local register indices.
* cpu/e132xs: Call debugger exception hook for TRAP instructions. Vas Crabb2025-03-264-53/+36
| | | | | Also made cycle counts a bit more consistent between interpreter and recompiler for exceptions and traps.
* i960: Further disassembly fixes AJR2025-03-251-3/+3
| | | | | - Enable decoding of a few more reg-type instructions - Add 0x prefix to unary branch destinations
* cpu/e132xs: Moved interrupt check to the beginning of instruction execution. Vas Crabb2025-03-265-328/+271
| | | | | | | * Fixes interrupts not being serviced while tracing. * Further improves recompiler performance. * Fixes recompiler interrupt check function calling itself recursively. * Also added debugger exception hook calls to interpreter and recompiler.
* -cpu/e132xs: Fixes and optimisations: Vas Crabb2025-03-266-670/+380
| | | | | | | | | | | | | | | | | | | * Fixed XM (index move) instructions failing to update the destination register on range error for interpreter and recompiler. * Fixed double-word stores when the source indicates SR (both stored words are zero) for interpreter and recompiler. * Fixed recompiler failing to set ILC and P on range error and frame error exceptions. * Optimised recompiled code for word size shifts. * Pushed more recompiler logic from run-time to code generation time and simplified delay slot PC check and trace check logic. * Use MOV rather than LOAD where possible in recompiler to improve code generation performance and symbolic memory locatin names in disassembled UML. * Updated TODO list in header comment, reduced copy/paste some more. -cpu/drcbex64.cpp: Avoid some more unnecessary register copies for ROLAND.
* cpu/e132xs: Optimised recompiled FRAME instruction. Vas Crabb2025-03-254-197/+181
| | | | Also added some more constants so there are a few less magic literals.
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
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* cpu/e132xs: Removed leftover block end from a function that no longer ↵ Vas Crabb2025-03-251-2/+0
| | | | generates a standalone block.
* cpu/e132xs, cpu/drcbex64.cpp: More fixes and optimisation: Vas Crabb2025-03-257-406/+397
| | | | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs: Implemented supervisor and trace modes as recompiler modes. This eliminates or simplifies a lot of run-time checks. In particular, the trace checks on every instruction are not generated when not tracing, and simplified to just checking the P bit when tracing. cpu/e132xs: Optimised code generation for RET, avoid a redundant load when checking for an overflow trap, use the exception parameter for exception codes rather than generating one function for each possible code. Also simplified interpreter code for RET. cpu/e132xs: Implemented SUMS for the recompiler. cpu/e132xs: Implemented privilege check for setting L (interrupt lockout) for recompiler. Not implemented for interpreter. cpu/e132xs: Partially fixed tracing. P flag should be set by all instructions except RET. Trace exceptions are not triggered for branches when using the recompiler. cpu/e132xs: Fixed ILC being set incorrectly for RET. cpu/drcbex64.cpp: Avoid unnecessary expensive operations when a shift operation request the zero and/or sign flags but not the carry flag.
* cpu/e132xs: Don't generate code to handle a delayed branch inline. Vas Crabb2025-03-243-85/+49
| | | | | | | * Also avoid an redundant load when checking if trace is active. * Reduces generated native instruction count by about 24% on x86-64 and gives an overall performance improvement of about 3.5% in -bench scores.
* mn10300: Fix disassembly of ADD Dm, Dn AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of even more move instruction modes AJR2025-03-221-1/+1
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* mn10300: Re-add missing LSR and ASR modes AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of yet another move instruction mode AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of another move instruction mode AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of some move instruction modes AJR2025-03-221-5/+5
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* unidasm: Add Panasonic MN10300 disassembler AJR2025-03-222-0/+971
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* srcclean the tree. Vas Crabb2025-03-231-1/+1
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* cpu/e132xs: Fixed IO2 interrupt check in recompiler. Vas Crabb2025-03-231-33/+33
| | | | | Also further reduced conditional branches and logic operations in interrupt check.
* cpu/e132xs: More recompiler optimisation: Vas Crabb2025-03-233-198/+126
| | | | | | | | * Made interrupt check function generate far more compact code (about 85% reduction in number of native instructions on x86-64). * Optimised out-of-cycles check. * Applied prior optimisation for trap/interrupt checks to static exception checks as well (code is still copy/pasted).
* Revert "i960: don't preserve sign bit when shifting integer left (#13507)" AJR2025-03-211-1/+1
| | | | | | This reverts commit 5954767b0b4da0c43f7194c7def4c162fbc8ef78. This was merged way too hastily based on incomplete information.
* i960: don't preserve sign bit when shifting integer left (#13507) Matthew Daniels2025-03-211-1/+1
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* cpu/e132xs: More recompiler fixes: Vas Crabb2025-03-224-177/+169
| | | | | | | | | * Cleaned up and commented code for generating an exception, reducing about nine memory accesses to update SR to two. * Implemented NEGS, and fixed ADDS and SUBS not setting excption handler address. * Optimised code to update Z flag on logic operations to avoid branches. * Reduced copy/paste a bit more.
* v60: implement correct rounding mode when converting float to integer (#13506) Matthew Daniels2025-03-211-1/+7
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* z80/z80dasm.cpp: Switched *R (LDIR, OTIR, etc) debugger flag to STEP_OVER ↵ holub2025-03-211-3/+3
| | | | (#13451)
* cpu/e132xs, cpu/drcbex64.cpp: Recompiler fixes and optimisations: Vas Crabb2025-03-214-1500/+753
| | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs.cpp: Refactored code generation to improve performance and fixed some issues: * Moved a considerable amound of logic from execution time to code generation time. * Fixed some cases where add/subtract carry was being interpreted incorrectly. * Fixed a case where a load double intruction was incorrectly writing the same register twice. * Use UML flags to generate condition codes for addition/subtraction. * Use UML carry flag for carry-/borrow-in. * Reduced UML register pressure (improves performance for hosts with fewer callee-saved CPU registers). * Moved more logic to helper functions to simplify maintenance. cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when used as address offset for LOAD/STORE. cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift operations if only carry flag will be used. cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
* Write the results of an ALU operation before writing to register/memory (#13486) Matthew Daniels2025-03-202-19/+19
| | | | | Sega Rally has an instruction that calculates d += p and loads a value into d at the same time; it is the loaded value that should be used, not the result of the ALU operation Also only test the d register when performing an ALU operation
* fixing cpu for missing opcode (#13502) ffxx682025-03-203-11/+18
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