| Commit message (Collapse) | Author | Age | Files | Lines |
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* Assume ROL sets the V and C flags the same way as SHL and MOVI clears
the V flag.
-cpu/drcbex64.cpp: Optimise SUB x,0,y to a NEG instruction (gets down to
one instruction from two or three a lot of the time). This had been a
TODO comment for ages.
-cpu/drcbex86.cpp: Got rid of unnecessary std::function use. This
substantially reduces the code size and reduces allocations during code
generation.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of the
intermediate tables in favour of bit switch statements. This improves
startup time, reduces code size, and gives the compiler more
optimisation opportunities.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of
asmjit namespace qualifiers left over from when the class declarations
were in headers and hence outside the scope of the using namespace
statements.
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Sorry, I'm too tired and didn't git add this. My bad.
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* Fixed behaviour of delayed branches, trace exceptions, and saved PC
calculation for error exceptions in delay slots for the interpreter.
All instructions in delay slots, branching instructions that can raise
exceptions and tracing shoud now (mis)behave properly for the
interpreter, including things the manual says you shouldn't do.
* Fixed and optimised flag updates for left shifts for the recompiler.
* Optimised ROL instruction for the recompiler and made flag calculation
equivalent to the interpreter both with and without the "Missioncraft
flags" compile-time option.
* Only block interrupts for one instruction following a delayed branch.
* Optimised the SOFTWARE instruction a little for the recompiler.
* Added more SDRAM configuration logging and cleaned up code a bit.
-cpu/drcbearm64.cpp: Apply the change from 7efe37938f9dd6a366e to OR and
XOR instructions as well, and fix some cases where a 32-bit logical
operation would fail to clear the upper bits of a register.
-cpu/drcbex64.cpp: Avoid more conditional branches on conditional MOV.
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* New NOT_WORKING machine
----------
Oldsmobile Driver Information System (version 2.2 CH) [Devin Acker]
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-cpu/drcbearm64.cpp: Simplified logic for choosing optimal AND strategy.
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* Fixed behaviour of exceptions in delay slots, and fixed recompiler not
updating ILC and P for some exceptions.
* Implemented privilege error exception on setting L in user mode for
interpreter.
-emu/debug, osd/modules/debugger: Added an option to show
exceptionpoints in breakpoints windows.
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Emulate pointer error exception on load/store and range error exception
on store signed byte/half-word.
Further optimised code generation for MOV and MOVI. These are very hot,
so this alone gains a further 2% performance or so in the dgPIX games.
Also some other miscellaneous cleanup.
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* Implemented pointer error exceptions on attempting to use a zero
address register (other than SR) in the recompiler.
* Also optimised load/store instructions a bit and reduced copy/paste.
* Fixed a couple of disassembler issues.
-misc/dgpix.cpp: Demoted The X-Files to not working with unemulated
protection.
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every opcode
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called on every opcode
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* Aligned the operand field in disassembly.
* Calculate results of immediate values against the PC to make
position-independent code easier to read without constantly using a
calculator (e.g. this shows destinations for call Rd, PC, imm).
* Added more symbols to the UML helper to make logged generated code
more readable.
* Made single-instruction-per-sequence mode configurable rather than a
compile-time option.
* Got rid of a criminal amount of copy/paste in the disassembler, and
got rid of all the deprecated strcpy calls.
* Got rid of some duplicated constants, changed some constants from
macros to enumerated values or constexpr globals.
* Reduced the amound of stuff in headers that doesn't need to be there.
-cpu/drcbex64.cpp: Don't construct std::function objects during code
generation - they require allocation.
-eolith/eolith.cpp: Turned single-instruction-per-sequence mode on for
now until someone works out why turning it off causes Raccoon World to
generate so much code it's unplayably slow.
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* Optimised double word shifts.
* Optimised the most common PC-relative operations to treat PC as
constant when possible, including:
- addi PC,imm (long relative branch)
- add PC,Rs (computed goto)
- sum Rd,PC,imm (calculate PC-relative address)
- add Rd,PC (calculate PC-relative address)
- ldw.d PC,Rs,imm (PC-relative load)
- stw.d PC,Rs,imm (PC-relative store)
* Changed template parameters to LlamaCase to make them more visible
different to constants/macros.
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* Disabled single-instruction-per-block mode.
* Don't bother with delay slot checks where it's unnecessary.
* Try to generate a speicalised copy of the delay slot instruction
followed by a direct branch of possible.
* Use the pre-decoded instruction length for updating the PC.
* Specialised versions of the CHK instruction that always or never
raise exceptions.
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* Fixed failing to call the debugger instruction hook for the first
instruction following an interrupt, exception or trap.
* Use UML branches to emulate non-delayed intra-block branches, avoiding
the expensive "hash jump".
* Re-worked the instruction description code:
- Calculate static branch targets for more instructions.
- Flag instructions that may cause mode changes.
- Don't be so eager to end an instruction sequence.
- Removed the local register input/output flags - FP may no be the
same when executing the code as when describing instructions.
* Fixed interpreter incorrectly setting ILC when an interrupt
immediately follows a RET instruction.
* Fixed recompiler flag calculation regressions, and optimised a little.
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* Fixed double-counting bug in exception dispatch.
* Fixed unsigned comparison of signed values in MUL cycles calculation.
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* Fixed local register display in debugger (this never worked).
* Made disassembler show local register indices.
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Also made cycle counts a bit more consistent between interpreter and
recompiler for exceptions and traps.
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- Enable decoding of a few more reg-type instructions
- Add 0x prefix to unary branch destinations
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* Fixes interrupts not being serviced while tracing.
* Further improves recompiler performance.
* Fixes recompiler interrupt check function calling itself recursively.
* Also added debugger exception hook calls to interpreter and recompiler.
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* Fixed XM (index move) instructions failing to update the destination
register on range error for interpreter and recompiler.
* Fixed double-word stores when the source indicates SR (both stored
words are zero) for interpreter and recompiler.
* Fixed recompiler failing to set ILC and P on range error and frame
error exceptions.
* Optimised recompiled code for word size shifts.
* Pushed more recompiler logic from run-time to code generation time and
simplified delay slot PC check and trace check logic.
* Use MOV rather than LOAD where possible in recompiler to improve code
generation performance and symbolic memory locatin names in
disassembled UML.
* Updated TODO list in header comment, reduced copy/paste some more.
-cpu/drcbex64.cpp: Avoid some more unnecessary register copies for
ROLAND.
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Also added some more constants so there are a few less magic literals.
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generates a standalone block.
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cpu/e132xs: Implemented supervisor and trace modes as recompiler modes.
This eliminates or simplifies a lot of run-time checks. In particular,
the trace checks on every instruction are not generated when not
tracing, and simplified to just checking the P bit when tracing.
cpu/e132xs: Optimised code generation for RET, avoid a redundant load
when checking for an overflow trap, use the exception parameter for
exception codes rather than generating one function for each possible
code. Also simplified interpreter code for RET.
cpu/e132xs: Implemented SUMS for the recompiler.
cpu/e132xs: Implemented privilege check for setting L (interrupt
lockout) for recompiler. Not implemented for interpreter.
cpu/e132xs: Partially fixed tracing. P flag should be set by all
instructions except RET. Trace exceptions are not triggered for
branches when using the recompiler.
cpu/e132xs: Fixed ILC being set incorrectly for RET.
cpu/drcbex64.cpp: Avoid unnecessary expensive operations when a shift
operation request the zero and/or sign flags but not the carry flag.
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* Also avoid an redundant load when checking if trace is active.
* Reduces generated native instruction count by about 24% on x86-64 and
gives an overall performance improvement of about 3.5% in -bench
scores.
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Also further reduced conditional branches and logic operations in
interrupt check.
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* Made interrupt check function generate far more compact code (about
85% reduction in number of native instructions on x86-64).
* Optimised out-of-cycles check.
* Applied prior optimisation for trap/interrupt checks to static
exception checks as well (code is still copy/pasted).
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This reverts commit 5954767b0b4da0c43f7194c7def4c162fbc8ef78.
This was merged way too hastily based on incomplete information.
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* Cleaned up and commented code for generating an exception, reducing
about nine memory accesses to update SR to two.
* Implemented NEGS, and fixed ADDS and SUBS not setting excption handler
address.
* Optimised code to update Z flag on logic operations to avoid branches.
* Reduced copy/paste a bit more.
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(#13451)
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cpu/e132xs.cpp: Refactored code generation to improve performance and
fixed some issues:
* Moved a considerable amound of logic from execution time to code
generation time.
* Fixed some cases where add/subtract carry was being interpreted
incorrectly.
* Fixed a case where a load double intruction was incorrectly writing
the same register twice.
* Use UML flags to generate condition codes for addition/subtraction.
* Use UML carry flag for carry-/borrow-in.
* Reduced UML register pressure (improves performance for hosts with
fewer callee-saved CPU registers).
* Moved more logic to helper functions to simplify maintenance.
cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when
used as address offset for LOAD/STORE.
cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift
operations if only carry flag will be used.
cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
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Sega Rally has an instruction that calculates d += p and loads a value into d at the same time; it is the loaded value that should be used, not the result of the ALU operation
Also only test the d register when performing an ALU operation
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