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* cpu/z180/z180.cpp: Fix filename in comment (#13555) cam9002025-04-031-1/+1
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* diexec: Add callback to allow debugger to break into the middle of wait-type ↵ AJR2024-11-171-7/+13
| | | | | | | | | | instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one). Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs. * cpu/hd61700, cpu/tms32031: Add standard IRQ callback * cpu/m68000gen.py: Change name of invoked executable to bin/python3 * cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
* z180asci: Fix calculation of framing and parity errors AJR2024-10-211-6/+6
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* Added ATTR_COLD to common lifecycle methods for many files in src/devices. ↵ holub2024-09-274-16/+16
| | | | (#12822)
* tlcs90: small spacing cleanup, remove execute_burn altogether (renamed but ↵ hap2024-09-205-8/+6
| | | | | | keeping it in z180 after seeing TODO note), kl1839vm1: execute_input_lines getter was removed from mame
* diexec: Remove vestigial execute_burn override AJR2024-09-181-1/+1
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* diexec: remove vestigal execute_input_lines() hap2024-09-181-1/+0
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* Removed some extraneous semicolons. (#12029) amameuser2024-02-131-1/+1
| | | | * cpu/z180/z180op.hxx: Remove extraneous semicolon. * machine/ldv1000hle.cpp: Remove extraneous semicolon
* emu/devcb.h: Eliminated the need to call resolve() on callbacks. (#11333) Vas Crabb2023-06-177-41/+14
| | | | | | | | | | | | Read callbacks now need a default return value supplied at construction. Replaced isnull() with isunset() which tells you if the callback wasn't configured rather than whether it isn't safe to call. Enabled validation of device callbacks (it seems it was disabled at some point, probably accidentally). Device callbacks and object finders now implement the same interface for resolution.
* emu/devfind.h: Added a lookup() member function to device finders. Vas Crabb2023-06-121-7/+7
| | | | | | | | | | | | | This simplifies looking up the target device during configuration. It is useful when configuring child devices in things like CPUs with integrated peripherals. emu/device.h: Allow templated subdevice() and siblingdevice() to work with classes that don't derive from device_t (e.g. classes that derive from device_interface). util/delegate.h: Added more noexcept. Won't make much difference as most of the affected member functions are inline anyway.
* emu/device.h: Removed device (READ|WRITE)_LINE_MEMBER in favor of explicit ↵ MooglyGuy2023-06-015-20/+20
| | | | function signatures. (#11283) [Ryan Holtz]
* z180: Fix cycle timings for branches not taken (one operand byte is always read) AJR2023-05-201-4/+7
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* cpu/nec: Fixed build; also, srcclean Vas Crabb2023-03-261-1/+1
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* dimemory: Add the target address space to translate, wrap the constants Olivier Galibert2023-03-182-2/+3
| | | | divtlb: Wrap the constants
* amstrad/pda600.cpp: Added simulation of coprocessor, input and storage. (#10862) Sandro Ronco2023-03-151-1/+9
| | | | | | | | | | | | * Added HLE character recognition. * Added pen display input. * Added PCMCIA memory card support and initial software list. * Added internal layout. * cpu/z180: Fixed SLP instruction. New working software list items ------------------------------- pda600: Games (Crazy Money, Mosaic and Pagged) pda600: Games Demo (Game 44, Squares and FliView)
* Interrupt callback rationalization AJR2023-03-111-1/+1
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* cpu/z180: Added CSIO emulation. [Vas Crabb, Sandro Ronco] Vas Crabb2023-03-115-49/+400
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* hd647180x: fix typo on port E read hap2022-12-071-3/+3
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* z180asci: fix logic errors (nw) Peter Ferrie2022-08-031-4/+4
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* Z180 ASCI (#9762) Miodrag Milanović2022-06-064-220/+965
| | | | | | | | | | | New working machines ----------------------------------- Micromint SB180 [Miodrag Milanovic] -z180: implemented ASCI serial communication [Miodrag Milanovic] -tim011: hookup serial keyboard [Miodrag Milanovic] -20pacgal: Add support for terminal
* -tim011.cpp: Hooked up floppy drives properly. (#9649) Miodrag Milanović2022-05-022-0/+21
| | | | | | | | * Hooked up floppy drives and controller properly, and implemented video display. * formats/tim011_dsk.cpp: Added TIM 011 floppy image format. -machine/upd765.cpp: If waiting for additional command bytes, treat a data register read as an open bus write (tested on real hardware) and always trigger the DRQ line even if in nodma mode. [Carl -cpu/z180: Added callbacks for tend; decrement bcr1 when DMA channel 1 is active. [Carl]
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* Debugger feature improvements AJR2022-03-271-3/+11
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* Debugger-related feature removals and cleanup AJR2021-08-151-1/+0
| | | | | | | | - Remove the hotspot read tracker. This was never robustly implemented, but changes to the memory system made it much less useful, and the "speedup opportunities" which it aimed to determine are not very important from a current emulation standpoint. - Remove the CURSP/GENSP state symbol and the generic sp() getter. Stacking semantics vary too much between CPU architectures for this to be of much use. (A "SP" symbol has been added to a few CPU cores whose stack pointers were otherwise not being registered.) - Remove the cached pointer to device_state_interface and the state() fast accessor from device_t. Most users of device_state_interface either already had a pointer to the specific CPU device type or needed to check first for the presence of the interface. - Change the PC memory write tracker to use pcbase(), which works even when the instruction callback is masked out, instead of peeking at the PC history index. - Remove some obsolete watchpoint-related definitions from machine.h.
* hd647180x: Eliminate data space and instead map internal RAM into program ↵ AJR2021-03-174-58/+16
| | | | space using memory view
* -Switch to building MAME as C++17. Vas Crabb2020-11-151-0/+1
| | | | | | | * Updated sol2 to 3.2.2 * Updated pugixml to 1.10 * Increased minimum clang version to 6 * Cleaned up some stuff that can use new features
* z180: Updates AJR2020-08-125-58/+51
| | | | | | - Correct FRC counting rate and direction - Run programmable reload timer off FRC - Emulate a subtle difference from Z80 behavior in fetching opcode after DD CB or FD CB
* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-255-25/+22
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* z8s180: Fix segmentation fault due to oversight in last commit (nw) AJR2020-03-221-0/+2
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* z8s180: Internalize certain registers; make clock divider software-selectable AJR2020-03-222-170/+177
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* that should be the rest of the devcb arrays switched to new syntax (nw) Vas Crabb2020-02-082-8/+8
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* Make many device_execute_interface functions noexcept, including the ↵ AJR2019-11-091-7/+7
| | | | | | | | "information" overrides. This also covers several time-related functions in attotime, running_machine and emu_timer. (nw) m6805: Calculate min_cycles and max_cycles once at device_start time (Nw) attotime: Add as_khz and as_mhz (nw)
* z180: Reduce logical address width to 16 bits AJR2019-10-021-2/+2
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* z180: Minor technical correction to note (nw) AJR2019-10-021-1/+1
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* Add internal clock divider for Z180 family and adjust CPU clocks in many ↵ AJR2019-10-022-6/+12
| | | | drivers to compensate
* hd64180rp: Fix major address space configuration error (nw) AJR2019-09-302-5/+5
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* Split generic Z180 device into several subtypes. HD647180X now has specific ↵ AJR2019-09-306-51/+551
| | | | device emulation for the internal PROM, RAM and parallel ports.
* z180: Fixed verbose logging (nw) Nigel Barnes2019-08-221-6/+6
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* z180: Fix copy-and-paste error (nw) AJR2019-06-171-1/+1
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* z180: Separate out internal registers by function; get rid of a lot of ↵ AJR2019-06-174-1110/+735
| | | | not-so-useful macros (nw)
* "hardware" typo corrections (nw) Scott Stone2019-03-301-1/+1
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* srcclean and manual fixup (nw) Vas Crabb2018-08-261-4/+4
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* Z180: CSIO Flags & FRC implementation (#3882) grullosgo2018-08-231-3/+4
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* diexec: Interrupt API changes (nw) AJR2018-05-181-1/+2
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* proposal: move z80daisy* to devices/machine (#3572) Patrick Mackinlay2018-05-151-1/+1
| | | | | | | | | | * proposal: move z80daisy* to devices/machine Seems to me this is a machine, not a CPU? Main reason was to stop the Z80 CPU from being dragged into systems that don't have one just because they use a Z80 family peripheral. * missed this one (nw) * missed a spot (nw)
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-115-9/+9
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* Reshuffle some stuff: Vas Crabb2018-03-281-4/+4
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-1/+1
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* emumem: API change [O. Galibert] Olivier Galibert2017-11-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.