| Commit message (Collapse) | Author | Age | Files | Lines |
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instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one).
Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs.
* cpu/hd61700, cpu/tms32031: Add standard IRQ callback
* cpu/m68000gen.py: Change name of invoked executable to bin/python3
* cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
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(#12822)
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Read callbacks now need a default return value supplied at construction.
Replaced isnull() with isunset() which tells you if the callback wasn't
configured rather than whether it isn't safe to call.
Enabled validation of device callbacks (it seems it was disabled at some
point, probably accidentally).
Device callbacks and object finders now implement the same interface for
resolution.
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---------------------------------------
FLIT - Flexowriter Interrogation Tape [Bitsavers]
FLIT II [Bitsavers]
FLITloader Punch [Bitsavers, AJR]
* tx0: Minor adjustments to OPR disassembly
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shifted LOG_xxx constant macros
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- Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected.
- Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions.
- Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse.
- Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx)
- Don't pass over delay slots for debugging in ASAP core
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* Reduce repeated directory walking in cleansrc target (substantially
improves speed of building the target on Windows).
* Disable a validity check using an MSVC language extension when using
clang in MSVC ABI mode.
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--------------------------------
TX-0 upgraded system (8 kWords of RAM, old order code)
* tx0_64kw: Swap LR and MBR when MLR and LMB are specified together
* tx0_8kw: Recognize a few more composite OPRs in disassembly
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- Load typewriter input into correct bit positions of LR
- Invert MSB of display coordinates (fixes tic-tac-toe grid)
- tx0_8kw: Resolve confusion between SHR and CYR semantics (these were incorrectly swapped)
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- Complete rewrite of disassemblers, using standard names for OPRs
- Clear MBR in cycle 1 when AMB is not specified
- Perform AMB before COM (tx0_64kw)
- Fix characters printed on Flexowriter (bit order was incorrectly reversed)
- Modernize logging in CPU device
- Only call the debugger hook once per instruction cycle
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- Make IOS actually wait for I/O when used more than once
- Remove break statement that disabled half the OPRs
- Don't normalize minus zero sums (also applies to tx0_8kw)
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