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* (nw) Clean up the mess on master Vas Crabb2019-03-261-0/+3
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-3/+0
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* srcclean and cleanup (nw) Vas Crabb2019-01-271-1/+1
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* MIPS3: Add minimal support for revealing the Secondary Cache Line size in ↵ tyfighter2019-01-141-0/+2
| | | | the Status Register
* mips3: Fixed fastram accesses and COP0 exception handling. [Ryan Holtz] MooglyGuy2019-01-111-0/+1
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* -mips, rsp: Removed MCFG, nw mooglyguy2018-12-091-10/+0
| | | | -aleck64, hng64, kinst, namcops2, namcos23, ps2sony, pyson, vp101: Removed MACHINE_CONFIG_*, nw
* mips3.cpp: Started laying the groundwork for cache support, nw mooglyguy2018-11-191-7/+21
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* -o2.cpp: Added CRIME and MACE skeleton devices. [Ryan Holtz] mooglyguy2018-11-181-24/+30
| | | | | | | | | | | -mips3.cpp: Various changes: [Ryan Holtz] * Added an #ifdef to display DPRINTF calls from the SGI O2 PROM. * Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus. * Fixed a bug that caused a crash with 64-bit data bus and the DRC. -indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz] -hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
* mips3: add r4000 and r4400 variants (nw) Patrick Mackinlay2018-09-191-0/+42
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* Revert "MIPS3: Fixup LL/SC opcode operation. (nw)" Ted Green2018-09-011-1/+2
| | | | This reverts commit 326b1f7465540684ffe539099b20b2384f16feb7.
* MIPS3: Fixup LL/SC opcode operation. (nw) Ted Green2018-09-011-2/+1
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* (nw) srcclean and some cleanup: Vas Crabb2018-07-221-686/+686
| | | | | | * Make more #include guards follow standard format - using MAME_ as the prefix makes it easy to see which ones come from our code in a preprocessor dump, and having both src/devices/machine/foo.h and src/mame/machine/foo.h causes issues anyway * Get #include "emu.h" out of headers - it should only be the first thing in a complilation unit or we get differences in behaviour with PCH on/off * Add out-of-line destructors to some devices - it forces the compiler to instantiate the vtable in a certain location and avoids some non-deterministic compiler behaviours
* You can't require a forward declared class (nw) smf-2018-07-211-2/+0
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* (nw) fixed the build. Robbbert2018-07-211-0/+1
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* ps2sony: Some basic VU1 support, major file reshuffling, nw mooglyguy2018-07-211-1/+1
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* ps2sony: Checkpoint, nw mooglyguy2018-07-171-2/+15
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* ps2sony: Checkpoint. Adds a bunch of vector and parallel ops to the EE core, ↵ mooglyguy2018-07-141-1/+7
| | | | and skeleton GIF VIF1, and GS devices.
* -ps2sony: Various DMA and SIF bug fixes, initial OSDSYS ELF transfers to IOP ↵ mooglyguy2018-07-051-0/+4
| | | | now, but EE and IOP hang immediately thereafter. nw
* -ps2sony: Fleshing out the skeleton driver. [Ryan Holtz] mooglyguy2018-06-281-660/+723
| | | | | | | | | | | | | * Added ps2timer device to encapsulate Playstation 2 timers. * Temporarily hacked R5900 core to always have scratchpad RAM mapped at 0x70000000. * Added reference counting to divtlb so that it does not unmap pages that are still shared with other entries. * Added a considerable amount of logging to ps2sony.cpp. -mips3: Added basic Emotion Engine support. [Ryan Holtz] * Added S bit to TLB mapping. * Added support for VSUB, VIADD, VSQI, VISWR, VOR, LQ, SQ, MFSA, MTSA, MFHI1, MFLO1, MULT1, DIV1, DIVU1, PEXTLW, PADDUW, PMFHI, PMFLO, PCPYLD, PCPYUD, SQC2, LQC2 opcodes. [Ryan Holtz]
* srcclean and other cleanup (nw) Vas Crabb2018-06-241-52/+52
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* mips3: Added VU0 macro-instructions to R5900 disassembler, pending split ↵ mooglyguy2018-06-231-1/+3
| | | | into separate device. nw
* mips3: Added disassembler for Emotion Engine core opcodes. VU macro ops are ↵ mooglyguy2018-06-231-68/+96
| | | | still to-do. [Ryan Holtz]
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-1/+2
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-39/+40
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* destaticify initializations (nw) (#3289) wilbertpol2018-03-041-6/+6
| | | | | | * destaticify initializations (nw) * fix this->set_screen (nw)
* emumem: API change [O. Galibert] Olivier Galibert2017-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-10/+1
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* This is too contentious, please put it up for review Vas Crabb2017-08-011-2/+1
| | | | | | Revert "Changes to debugger memory address translation" This reverts commit bb0964f9a284b15851773f5428bd602ca01cc28b.
* Changes to debugger memory address translation AJR2017-08-011-1/+2
| | | | | | - memory_translate now returns an address space number rather a boolean flag, permitting addresses in part of one space to map to an entirely different space. This is primarily intended to help MCUs which have blocks of internal memory that can be dynamically remapped, but may also allow for more accurate emulation of MMUs that drive multiple external address spaces, since the old limit of four address spaces per MAME device has been lifted. - memory_translate has also been made a const method, in spite of a couple of badly behaved CPU cores that can't honestly treat it as one. - The (read|write)_(byte|word|dword|qword|memory|opcode) accessors have been transferred from debugger_cpu to device_memory_interface, with somewhat modified arguments corresponding to the translate function it calls through to if requested.
* make device_memory_interface slightly less of a special case, use a typedef ↵ Vas Crabb2017-07-101-1/+1
| | | | to avoid nested templates everywhere (nw)
* dimemory: Lift the cap on the number of address spaces per device [O. Galibert] Olivier Galibert2017-07-031-2/+2
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* more incorrect names fixed (nw) smf-2017-05-141-4/+4
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* Move static data out of devices into the device types. This is a ↵ Vas Crabb2017-05-141-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | significant change, so please pay attention. The core changes are: * Short name, full name and source file are no longer members of device_t, they are part of the device type * MACHINE_COFIG_START no longer needs a driver class * MACHINE_CONFIG_DERIVED_CLASS is no longer necessary * Specify the state class you want in the GAME/COMP/CONS line * The compiler will work out the base class where the driver init member is declared * There is one static device type object per driver rather than one per machine configuration Use DECLARE_DEVICE_TYPE or DECLARE_DEVICE_TYPE_NS to declare device type. * DECLARE_DEVICE_TYPE forward-declares teh device type and class, and declares extern object finders. * DECLARE_DEVICE_TYPE_NS is for devices classes in namespaces - it doesn't forward-declare the device type. Use DEFINE_DEVICE_TYPE or DEFINE_DEVICE_TYPE_NS to define device types. * These macros declare storage for the static data, and instantiate the device type and device finder templates. The rest of the changes are mostly just moving stuff out of headers that shouldn't be there, renaming stuff for consistency, and scoping stuff down where appropriate. Things I've actually messed with substantially: * More descriptive names for a lot of devices * Untangled the fantasy sound from the driver state, which necessitates breaking up sound/flip writes * Changed DECO BSMT2000 ready callback into a device delegate * Untangled Microprose 3D noise from driver state * Used object finders for CoCo multipak, KC85 D002, and Irem sound subdevices * Started to get TI-99 stuff out of the TI-990 directory and arrange bus devices properly * Started to break out common parts of Samsung ARM SoC devices * Turned some of FM, SID, SCSP DSP, EPIC12 and Voodoo cores into something resmbling C++ * Tried to make Z180 table allocation/setup a bit safer * Converted generic keyboard/terminal to not use WRITE8 - space/offset aren't relevant * Dynamically allocate generic terminal buffer so derived devices (e.g. teleprinter) can specify size * Imporved encapsulation of Z80DART channels * Refactored the SPC7110 bit table generator loop to make it more readable * Added wrappers for SNES PPU operations so members can be made protected * Factored out some boilerplate for YM chips with PSG * toaplan2 gfx * stic/intv resolution * Video System video * Out Run/Y-board sprite alignment * GIC video hookup * Amstrad CPC ROM box members * IQ151 ROM cart region * MSX cart IRQ callback resolution time * SMS passthrough control devices starting subslots I've smoke-tested several drivers, but I've probably missed something. Things I've missed will likely blow up spectacularly with failure to bind errors and the like. Let me know if there's more subtle breakage (could have happened in FM or Voodoo). And can everyone please, please try to keep stuff clean. In particular, please stop polluting the global namespace. Keep things out of headers that don't need to be there, and use things that can be scoped down rather than macros. It feels like an uphill battle trying to get this stuff under control while more of it's added.
* MIPS: initial support for VR5500 and TX4925 CPUs. [R. Belmont] arbee2017-03-251-0/+42
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* mips3: Retry fixing FPU register aliasing Happy2017-02-261-8/+2
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* srcclean (nw) Vas Crabb2016-11-271-1/+1
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* Changing the MIPS DRC to not use static char buffers when disassembling Nathan Woods2016-11-201-1/+0
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* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-201-1/+1
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* Put the declaration of dasmmips3() in a header file Nathan Woods2016-11-161-0/+8
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* converted lot of TRUE/FALSE to real boolean and updated types (nw) Miodrag Milanovic2016-10-221-13/+13
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-152/+152
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* fix disassembly window (nw) smf-2016-10-181-2/+2
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* Port Happy's PPC aliasing fix to the MIPS3 DRC, nw therealmogminer@gmail.com2016-04-151-2/+8
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* Make generic VTLB implementation a modern device interface (nw) AJR2016-02-071-4/+2
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* reverting: Miodrag Milanovic2016-01-201-17/+17
| | | | | | | SHA-1: 1f90ceab075c4869298e963bf0a14a0aac2f1caa * tags are now strings (nw) fix start project for custom builds in Visual Studio (nw)
* Revert "rest of device parameters to std::string (nw)" Miodrag Milanovic2016-01-201-1/+1
| | | | This reverts commit caba131d844ade3f2b30d6be24ea6cf46b2949d7.
* rest of device parameters to std::string (nw) Miodrag Milanovic2016-01-161-1/+1
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* tags are now strings (nw) Miodrag Milanovic2016-01-161-17/+17
| | | | fix start project for custom builds in Visual Studio (nw)
* Revert "remove const (nw)" Miodrag Milanovic2016-01-131-1/+1
| | | | This reverts commit e96fd34dd817f1113daf9e6b099a8f40cfd1ed6d.
* remove const (nw) Miodrag Milanovic2016-01-111-1/+1
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