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* diexec: Add callback to allow debugger to break into the middle of wait-type ↵ AJR2024-11-172-26/+20
| | | | | | | | | | instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one). Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs. * cpu/hd61700, cpu/tms32031: Add standard IRQ callback * cpu/m68000gen.py: Change name of invoked executable to bin/python3 * cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
* Added ATTR_COLD to common lifecycle methods for many files in src/devices. ↵ holub2024-09-271-8/+8
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* diexec: remove vestigal execute_input_lines() hap2024-09-181-1/+0
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* util/ioprocs.cpp: Added wrappers for common patterns. (#11608) Vas Crabb2024-02-251-4/+12
| | | | | emu/diimage.h: Removed fread overloads that allocate memory for output. util/core_file.cpp: Changed output size of load to size_t.
* emu/devcb.h: Eliminated the need to call resolve() on callbacks. (#11333) Vas Crabb2023-06-172-19/+9
| | | | | | | | | | | | Read callbacks now need a default return value supplied at construction. Replaced isnull() with isunset() which tells you if the callback wasn't configured rather than whether it isn't safe to call. Enabled validation of device callbacks (it seems it was disabled at some point, probably accidentally). Device callbacks and object finders now implement the same interface for resolution.
* mc68hc11: Fix STOP recovery again AJR2023-03-201-1/+1
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* mc68hc11: Fix WAI handling for now AJR2023-03-181-2/+2
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* mc68hc11: Use standard interrupt handling for RESET vector; add XIRQ input AJR2023-03-182-10/+18
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* mc68hc11: Clean up interrupt code and generalize handling; enable all timer ↵ AJR2023-03-182-85/+112
| | | | output compare and count overflow interrupts (only TOC1 was fully supported before)
* Interrupt callback rationalization AJR2023-03-111-9/+6
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* dinvram: Separate backup-enable parameter (which prevents both loading and ↵ AJR2022-08-092-7/+1
| | | | saving) from nvram_can_save
* Add M68HC11 internal EEPROM for relevant models AJR2022-06-272-17/+123
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* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* New machines market as NOT_WORKING AJR2022-03-312-0/+63
| | | | | ---------------------------------- Waldorf Electronics MiniWorks 4-Pole [DBWBP]
* Debugger feature improvements AJR2022-03-271-0/+2
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* mc68hc11: Add stubs for TCTL registers; document coding bug in asma2k AJR2021-09-062-0/+52
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* mc68hc11: Fix bug causing DES to decrement IX rather than the stack pointer AJR2021-04-161-1/+1
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* 68hc11: amount of work not worthy of me being copyright holder hap2021-03-274-4/+4
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* mc68hc11: Memory modernization and updates AJR2021-03-262-306/+491
| | | | | | | | - Eliminate data and I/O spaces, using memory views to remap internal RAM and I/O registers within the program space - Add MC68HC811E2 type - Lay some groundwork for future internal EEPROM support - Add RTI and counter overflow flag - Register debugger state for a few more internal registers
* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-252-16/+16
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* sweeten most of the remaining arrays of delegates (nw) Vas Crabb2020-02-072-12/+9
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* mc68hc11: Fix disassembly and execution of BRCLR/BRSET (IND, Y) AJR2019-12-042-5/+5
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* mc68hc11: Emulate FDIV instruction AJR2019-11-153-1/+38
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* mc68hc11: Fix size of fetched operand for ADDD indexed modes AJR2019-11-141-2/+2
| | | | This appears to have accidentally regressed in bcd74f1e42234b8376a3b020684394b8f72111e5.
* mc68hc11: Clock is internally divided by 4 AJR2019-11-131-0/+2
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* Make many device_execute_interface functions noexcept, including the ↵ AJR2019-11-091-3/+3
| | | | | | | | "information" overrides. This also covers several time-related functions in attotime, running_machine and emu_timer. (nw) m6805: Calculate min_cycles and max_cycles once at device_start time (Nw) attotime: Add as_khz and as_mhz (nw)
* New machines marked as NOT_WORKING AJR2019-11-091-0/+2
| | | | | | ---------------------------------- MiniJook [SpinalFeyd] SuperStars (CD jukebox) [SpinalFeyd]
* Fix build (nw) AJR2019-11-011-1/+1
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* mc68hc11: Preliminary MC68HC11F1 type added (nw) AJR2019-11-012-9/+79
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* mc68hc11: Add another register stub; remove vestigial declaration (nw) AJR2019-08-132-3/+21
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* mc68hc11: Add internal latches and direction registers for ports AJR2019-08-132-226/+418
| | | | | | | Related changes (nw): - Split up hc11_regs_r/w into many separate handlers - Give each MC68HC11 model its own specific io_map - Remove now-unnecessary readback handlers from skeetsht.cpp and taitojc.cpp
* mc68hc11: CPU device modernization (nw) AJR2019-08-102-89/+181
| | | | | | - Replace the old-style fake I/O space with callbacks - Add address spaces to handle remappable accesses to internal RAM and registers - Eliminate set_config in favor of separate device types for each model (not differentiated properly yet...)
* mc68hc11 - implement more of the instructions. 68bit2019-07-253-163/+817
| | | | | | | | Limited testing of these additions on 6800 code. The fdiv instruction appears the only one remaining now. Cleaned up some of the existing definitions to make the patterns more consistent, and to make it easier to spot inconsistencies and errors.
* -nanoprocessor, mn10200, ps2vu, m68hc11: Removed MCFG macros. [Ryan Holtz] mooglyguy2018-12-151-8/+7
| | | | -30test, skeetsht, taitojc: Removed MACHINE_CONFIG macros. [Ryan Holtz]
* diexec: Interrupt API changes (nw) AJR2018-05-181-1/+0
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-112-4/+4
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-1/+1
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* destaticify initializations (nw) (#3289) wilbertpol2018-03-041-6/+6
| | | | | | * destaticify initializations (nw) * fix this->set_screen (nw)
* mc68hc11: Fix dissassembly of instructions with 16-bit operands (immediate ↵ AJR2018-01-011-2/+2
| | | | or direct)
* MC68HC11 is big-endian (nw) AJR2018-01-011-2/+2
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-264-90/+108
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* make device_memory_interface slightly less of a special case, use a typedef ↵ Vas Crabb2017-07-102-3/+3
| | | | to avoid nested templates everywhere (nw)
* dimemory: Lift the cap on the number of address spaces per device [O. Galibert] Olivier Galibert2017-07-032-4/+8
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* Move static data out of devices into the device types. This is a ↵ Vas Crabb2017-05-142-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | significant change, so please pay attention. The core changes are: * Short name, full name and source file are no longer members of device_t, they are part of the device type * MACHINE_COFIG_START no longer needs a driver class * MACHINE_CONFIG_DERIVED_CLASS is no longer necessary * Specify the state class you want in the GAME/COMP/CONS line * The compiler will work out the base class where the driver init member is declared * There is one static device type object per driver rather than one per machine configuration Use DECLARE_DEVICE_TYPE or DECLARE_DEVICE_TYPE_NS to declare device type. * DECLARE_DEVICE_TYPE forward-declares teh device type and class, and declares extern object finders. * DECLARE_DEVICE_TYPE_NS is for devices classes in namespaces - it doesn't forward-declare the device type. Use DEFINE_DEVICE_TYPE or DEFINE_DEVICE_TYPE_NS to define device types. * These macros declare storage for the static data, and instantiate the device type and device finder templates. The rest of the changes are mostly just moving stuff out of headers that shouldn't be there, renaming stuff for consistency, and scoping stuff down where appropriate. Things I've actually messed with substantially: * More descriptive names for a lot of devices * Untangled the fantasy sound from the driver state, which necessitates breaking up sound/flip writes * Changed DECO BSMT2000 ready callback into a device delegate * Untangled Microprose 3D noise from driver state * Used object finders for CoCo multipak, KC85 D002, and Irem sound subdevices * Started to get TI-99 stuff out of the TI-990 directory and arrange bus devices properly * Started to break out common parts of Samsung ARM SoC devices * Turned some of FM, SID, SCSP DSP, EPIC12 and Voodoo cores into something resmbling C++ * Tried to make Z180 table allocation/setup a bit safer * Converted generic keyboard/terminal to not use WRITE8 - space/offset aren't relevant * Dynamically allocate generic terminal buffer so derived devices (e.g. teleprinter) can specify size * Imporved encapsulation of Z80DART channels * Refactored the SPC7110 bit table generator loop to make it more readable * Added wrappers for SNES PPU operations so members can be made protected * Factored out some boilerplate for YM chips with PSG * toaplan2 gfx * stic/intv resolution * Video System video * Out Run/Y-board sprite alignment * GIC video hookup * Amstrad CPC ROM box members * IQ151 ROM cart region * MSX cart IRQ callback resolution time * SMS passthrough control devices starting subslots I've smoke-tested several drivers, but I've probably missed something. Things I've missed will likely blow up spectacularly with failure to bind errors and the like. Let me know if there's more subtle breakage (could have happened in FM or Voodoo). And can everyone please, please try to keep stuff clean. In particular, please stop polluting the global namespace. Keep things out of headers that don't need to be there, and use things that can be scoped down rather than macros. It feels like an uphill battle trying to get this stuff under control while more of it's added.
* Self-registering devices prep: Vas Crabb2017-02-271-1/+1
| | | | | | | | | | | | | | * Make device_creator a variable template and get rid of the ampersands * Remove screen.h and speaker.h from emu.h and add where necessary * Centralise instantiations of screen and speaker finder templates * Add/standardise #include guards in many hearers * Remove many redundant #includes * Order #includesr to help catch headers that can't be #included alone (nw) This changes #include order to be prefix, unit header if applicable then other stuff roughly in order from most dependent to least dependent library. This helps catch headers that don't #include things that they use.
* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-203-14/+4
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* Changed the hc11 disassembler to use 'std::ostream &' internally Nathan Woods2016-11-151-31/+30
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