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* m68000: When a SR S-flag update happens in parallel to a bus access, be ↵ Olivier Galibert2023-06-021-1/+1
| | | | careful to delay the update to after the access because it is otherwise seen too early through fc, and acts on mmus&co. Fixes hp_ipc [ajrhacker, O. Galibert]
* m68008: Implement as a 68000 variant Olivier Galibert2023-05-271-21/+4
| | | | m68000mcu: Extract from m68000
* tmp68301: Add timers and fix interrupts (thanks grdians for the test cases) Olivier Galibert2023-04-041-0/+1
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* tmp68301: Reimplement in the new68k framework. The timers are not yet ↵ Olivier Galibert2023-04-041-0/+16
| | | | implemented, couldn't find a driver which cared. Hopefully the regression testing will find some.
* cpu/nec: Fixed build; also, srcclean Vas Crabb2023-03-261-13/+13
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* m68000: Fix the vpa wait state, make using irq 7/NMI a little more transparent Olivier Galibert2023-02-221-0/+2
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* emumem: Fix delegates on delay methods Olivier Galibert2023-02-221-0/+1
| | | | | m68000: Fix the vpa timings mac128: Use vpa for the via
* m68000: Correct over, it was losing the offset Olivier Galibert2023-02-221-2/+3
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* m68000: the ext-derived over alu operation shoudl clear aluo (it's actually ↵ Olivier Galibert2023-02-221-0/+1
| | | | slightly more complicated but clearing is the end result). Fixes some address calculations in div (thanks qkumba again)
* emumem: First try at wait states Olivier Galibert2023-02-221-0/+3
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* m68000: New implementation, generated from the micro/nanocode Olivier Galibert2023-02-221-10/+900
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* 68000: Add a level of transparent indirection, turn the reset output line ↵ Olivier Galibert2022-11-031-2/+2
| | | | into devcb.
* m68000: split the header to make future semi-indenpendant implementations sane Olivier Galibert2022-09-301-709/+2
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* 68k: support for external MMU bus error instruction restart (#9369) J Booth2022-03-201-1/+4
| | | | | * 68010 RTE: don't set SR (which may change SP to USP) until after unwinding 1000 stack exception frame * 68010: create 1000 format stack frame on bus error * 68k: support for external MMU bus error instruction restart, set fault address in 68010 and 68070 stack frames, set fc and rw in 68010 stack frame
* devices/*: Removed extra semicolons after function bodies in headers. (#9275) 0kmg2022-02-061-38/+38
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* m68k: header update. [R. Belmont] arbee2021-05-131-2/+2
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* m68000: Separate FPU code from header AJR2020-10-151-2/+59
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* fix compile? untested (nw) hap2020-06-091-2/+2
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* megadriv.cpp, megaplay.cpp, megatech.cpp: macro removal (nw) Ivan Vangelista2020-05-311-1/+1
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* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-251-0/+7
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* m68000: Don't iterate to save arrays; eliiminate legacy prepost registration ↵ AJR2020-04-221-3/+2
| | | | (nw)
* Make many device_execute_interface functions noexcept, including the ↵ AJR2019-11-091-38/+38
| | | | | | | | "information" overrides. This also covers several time-related functions in attotime, running_machine and emu_timer. (nw) m6805: Calculate min_cycles and max_cycles once at device_start time (Nw) attotime: Add as_khz and as_mhz (nw)
* scc68070: Add more accurate cycle counts, distinguished from MC68000 and MC68010 AJR2019-10-301-1/+1
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* Make devdelegate more like devcb for configuration. This is a Vas Crabb2019-10-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fundamental change to show device delegates are configured. Device delegates are now aware of the current device during configuration and will resolve string tags relative to it. This means that device delegates need a device to be supplied on construction so they can find the machine configuration object. There's a one-dimensional array helper to make it easier to construct arrays of device delegates with the same owner. (I didn't make an n-dimensional one because I didn't hit a use case, but it would be a simple addition.) There's no more bind_relative_to member - just call resolve() like you would for a devcb. There's also no need to cast nullptr when creating a late bind device delegate. The flip side is that for an overloaded or non-capturing lambda you'll need to cast to the desired type. There is one less conditional branch in the hot path for calls for delegates bound to a function pointer of member function pointer. This comes at the cost of one additional unconditional branch in the hot path for calls to delegates bound to functoids (lambdas, functions that don't take an object reference, other callable objects). This applies to all delegates, not just device delegates. Address spaces will now print an error message if a late bind error is encountered while installing a handler. This will give the range and address range, hopefully making it easier to guess which memory map is faulty. For the simple case of allowing a device_delegate member to be configured, use a member like this: template <typename... T> void set_foo(T &&...args) { m_foo_cb.set(std::forward<T>(args)...); } For a case where different delegates need to be used depending on the function signature, see src/emu/screen.h (the screen update function setters). Device delegates now take a target specification and function pointer. The target may be: * Target omitted, implying the current device being configured. This can only be used during configuration. It will work as long as the current device is not removed/replaced. * A tag string relative to the current device being configured. This can only be used during configuration. It will not be callable until .resolve() is called. It will work as long as the current device is not removed/replaced. * A device finder (required_device/optional_device). The delegate will late bind to the current target of the device finder. It will not be callable until .resolve() is called. It will work properly if the target device is replaced, as long as the device finder's base object isn't removed/replaced. * A reference to an object. It will be callable immediately. It will work as long as the target object is not removed/replaced. The target types and restrictions are pretty similar to what you already have on object finders and devcb, so it shouldn't cause any surprises. Note that dereferencing a device finder will changes the effect. To illustrate this: ... required_device<some_device> m_dev; ... m_dev(*this, "dev") ... // will late bind to "dev" relative to *this // will work if "dev" hasn't been created yet or is replaced later // won't work if *this is removed/replaced // won't be callable until resolve() is called cb1.set(m_dev, FUNC(some_device::w)); ... // will bind to current target of m_dev // will not work if m_dev is not resolved // will not work if "dev" is replaced later // will be callable immediately cb2.set(*m_dev, FUNC(some_device::w)); ... The order of the target and name has been reversed for functoids (lambdas and other callable objects). This allows the NAME macro to be used on lambdas and functoids. For example: foo.set_something(NAME([this] (u8 data) { m_something = data; })); I realise the diagnostic messages get ugly if you use NAME on a large lambda. You can still give a literal name, you just have to place it after the lambda rather than before. This is uglier, but it's intentional. I'm trying to drive developers away from a certain style. While it's nice that you can put half the driver code in the memory map, it detracts from readability. It's hard to visualise the memory range mappings if the memory map functions are punctuated by large lambdas. There's also slightly higher overhead for calling a delegate bound to a functoid. If the code is prettier for trivial lambdas but uglier for non-trivial lambdas in address maps, it will hopefully steer people away from putting non-trivial lambdas in memory maps. There were some devices that were converted from using plain delegates without adding bind_relative_to calls. I fixed some of them (e.g. LaserDisc) but I probably missed some. These will likely crash on unresolved delegate calls. There are some devices that reset delegates at configuration complete or start time, preventing them from being set up during configuration (e.g. src/devices/video/ppu2c0x.cpp and src/devices/machine/68307.cpp). This goes against the design principles of how device delegates should be used, but I didn't change them because I don't trust myself to find all the places they're used. I've definitely broken some stuff with this (I know about asterix), so report issues and bear with me until I get it all fixed.
* m680x0: Rely on the opcode tables for cpu filtering, ban "return" from ↵ Olivier Galibert2019-04-291-1/+1
| | | | opcode handlers, restyle [O. Galibert]
* m680x0: Normalize type names to the short versions [O. Galibert] Olivier Galibert2019-04-291-147/+147
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* m680x0: Change method pointers to state ids in the big tables [O. Galibert] Olivier Galibert2019-04-291-7/+8
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* m680x0: Rename remaining_cycles to icount in alignemnt with the rest of mame ↵ Olivier Galibert2019-04-291-1/+1
| | | | [O. Galibert]
* m680x0: Only keep the bodies in the input file [O. Galibert] Olivier Galibert2019-04-291-0/+20
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* scc68070: Merge CPU device with on-chip peripheral emulation AJR2019-04-171-6/+5
| | | | | - Add internal clock divider - Add a few crude hacks to force status bits in unemulated UART and I2C
* m68000: Make the autovector abstraction a bit less leaky (nw) AJR2019-04-141-3/+4
| | | | m68008plcc: Rename device for future use (nw)
* fidel_eag68k: disable_interrupt_mixer for feagv5 (nw) hap2019-04-051-0/+4
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* 68000: Rework interrupt handling [O. Galibert] Olivier Galibert2019-04-051-23/+17
| | | | | | | * Implement the cpu space as an address space * Make all vectored interrupts use the cpu space * Make it possible to direct the cpu space to another space, use it for amiga (which handles it as a normal AS_PROGRAM read) * Make it possible to disable the priority muxer and get 3 lines instead, use it for cps2
* (nw) Clean up the mess on master Vas Crabb2019-03-261-16/+3
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-3/+16
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* apollo: Updates and resurrection [Hans Ostermeyer] arbee2019-03-221-0/+1
| | | | | | | - Fix typo'd constant in m68kmmu that prevented trapping user accesses to kernel space - Remove need for intrusive m68k modifications - Fix crash in 3c505 networking - Fix Domain/OS booting in Normal mode
* m68301: Remove device type (nw) AJR2019-03-221-16/+0
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* m68000: Add overrideable method to signal RESET instruction to internal ↵ AJR2019-02-111-0/+2
| | | | peripherals (nw)
* srcclean and fixup (nw) Vas Crabb2018-11-251-1/+1
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* Hpux final fixes (#4257) dxl2018-11-061-0/+1
| | | | | | | | | | | * m68kmmu: Set B bit in ATC on buserror (nw) * m68kmmu: store last logical address for bus error handler (nw) * hp9k_3xx: update /370 to 48MB configuration (nw) It was the maximum configuration on /370, and allows us to have a pretty usable HP VUE Environment.
* m68000: show PMMU registers for 68020/030/040 in debugger Sven Schnelle2018-11-061-1/+3
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* m68kmmu improvements (#4229) dxl2018-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * m68kmmu: PMMU improvements (nw) - handle RW bit in ATC cache properly - add page table walk that result in BUSERROR to ATC - fix ptest instruction - trap if PLOAD is called with MMU disabled on MC68851 - don't skip descriptor status update for page descriptors - set address in ptest to last descriptor address - add function code page table lookup - fix ptest level report in MMU SR - fix TT register matching (test RW bit, fix masking of bits) - decode fc field for pload instruction - fix decoding of pload instruction * m68kmmu: remove unused variable (nw) * m68kmmu: abort table search when WP is encountered * m68kmmu: various improvements * hp9k_3xx: call MMU buserror handler * m68kmmu: set M bit if root descriptor is of page type It seems like at least the 68030 sets the M bit in the MMU SR if the root descriptor is of PAGE type, so do a logical and between RW and the root type. * m68kmmu: fix comment * m68kmmu: rename descriptor types to more useful names * m68kmmu: set type for 8 byte table descriptors * m68kmmu: use iterative approach for table walking * style (nw) * fix ptest argument (nw) * hp9k_3xx: ignore buserror if it's caused by a page table walk (nw) * m68kmmu: initialize addr_out to 0 (nw) Otherwise we might return an arbitrary value if ptest can't find an entry. Shouldn't matter for the OS, but that change makes at least the compiler happy.
* add Special Status Word (SSW) to exception frames Sven Schnelle2018-10-071-0/+7
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* diexec: Interrupt API changes (nw) AJR2018-05-181-36/+2
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-46/+13
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-19/+19
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* Revert "Revert "Merge branch 'master' of https://github.com/mamedev/mame"" Firehawke2017-12-131-164/+143
| | | | This reverts commit 54155441e9ba9941e85d80c4834a66376a11e791.
* Revert "Merge branch 'master' of https://github.com/mamedev/mame" Firehawke2017-12-131-143/+164
| | | | | This reverts commit f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4, reversing changes made to 0d70d798107d4e4e8fb9f230410aeb1e888d65c5.
* Refactor 680x0 so that member variables aren't public. [smf] smf-2017-12-131-164/+143
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.