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* Added ATTR_COLD to common lifecycle methods for many files in src/devices. ↵ holub2024-09-271-2/+2
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* diexec: remove vestigal execute_input_lines() hap2024-09-181-6/+2
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* emu/devcb.h: Eliminated the need to call resolve() on callbacks. (#11333) Vas Crabb2023-06-171-7/+3
| | | | | | | | | | | | Read callbacks now need a default return value supplied at construction. Replaced isnull() with isunset() which tells you if the callback wasn't configured rather than whether it isn't safe to call. Enabled validation of device callbacks (it seems it was disabled at some point, probably accidentally). Device callbacks and object finders now implement the same interface for resolution.
* Interrupt callback rationalization AJR2023-03-111-1/+1
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* Debugger feature improvements AJR2022-03-271-15/+15
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-252-7/+7
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* capricorn, hphybrid, nanoprocessor: Use devcb_read8 for interrupt vectoring (nw) AJR2020-04-222-2/+9
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* hp86b: new working machine fulivi2020-02-142-14/+51
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* Make many device_execute_interface functions noexcept, including the ↵ AJR2019-11-091-3/+3
| | | | | | | | "information" overrides. This also covers several time-related functions in attotime, running_machine and emu_timer. (nw) m6805: Calculate min_cycles and max_cycles once at device_start time (Nw) attotime: Add as_khz and as_mhz (nw)
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-112-3/+3
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-264-130/+169
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* make device_memory_interface slightly less of a special case, use a typedef ↵ Vas Crabb2017-07-102-3/+3
| | | | to avoid nested templates everywhere (nw)
* fix broken build (all compilers). (nw) smf-2017-07-091-0/+1
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* never hurts to srcclean (nw) Vas Crabb2017-07-092-52/+52
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* Begin of HP80 emulation (#2448) fulivi2017-07-083-0/+1865
What works: * HP85A machine with 16K of RAM * Capricorn CPU works * Keyboard works (with minor issues) * CRT text / graphics modes work (correct speed is not emulated yet so service ROM complaints) * BASIC is usable What is missing (and I'll have hopefully working soon): * HW timers * Beeper * Integral printer * DC100 cassette drive * Extension ROMs * I/O modules (especially the HPIB interface so that we can hook up floppy drives) * Other models in the family (e.g. HP86)