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-rw-r--r--src/devices/bus/isa/isa.cpp2
-rw-r--r--src/devices/bus/isa/isa.h1
-rw-r--r--src/devices/bus/lpci/southbridge.cpp24
-rw-r--r--src/devices/bus/lpci/southbridge.h2
-rw-r--r--src/devices/machine/intelfsh.cpp4
-rw-r--r--src/emu/debug/debugcpu.cpp3
-rw-r--r--src/emu/emumem.cpp14
-rw-r--r--src/emu/emumem.h1
-rw-r--r--src/emu/machine.cpp8
-rw-r--r--src/mame/drivers/crystal.cpp75
-rw-r--r--src/mame/drivers/hh_sm510.cpp34
-rw-r--r--src/mame/drivers/intellec4.cpp2
-rw-r--r--src/mame/drivers/interpro.cpp62
-rw-r--r--src/mame/drivers/megasys1.cpp17
-rw-r--r--src/mame/drivers/shootaway2.cpp7
-rw-r--r--src/mame/drivers/sun1.cpp88
-rw-r--r--src/mame/includes/interpro.h29
-rw-r--r--src/mame/machine/interpro_ioga.cpp310
-rw-r--r--src/mame/machine/interpro_ioga.h104
-rw-r--r--src/mame/machine/interpro_sga.cpp6
20 files changed, 468 insertions, 325 deletions
diff --git a/src/devices/bus/isa/isa.cpp b/src/devices/bus/isa/isa.cpp
index 740df102b8f..88822b1f78e 100644
--- a/src/devices/bus/isa/isa.cpp
+++ b/src/devices/bus/isa/isa.cpp
@@ -485,7 +485,7 @@ void isa16_device::device_start()
void isa16_device::install16_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler)
{
- int buswidth = m_memwidth;
+ int buswidth = m_iowidth;
switch(buswidth)
{
case 16:
diff --git a/src/devices/bus/isa/isa.h b/src/devices/bus/isa/isa.h
index 901a1634509..2675d660b24 100644
--- a/src/devices/bus/isa/isa.h
+++ b/src/devices/bus/isa/isa.h
@@ -226,6 +226,7 @@ public:
void install_rom(device_t *dev, offs_t start, offs_t end, const char *tag, const char *region);
void install_memory(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler);
+ void unmap_device(offs_t start, offs_t end) const { m_iospace->unmap_readwrite(start, end); }
void unmap_bank(offs_t start, offs_t end);
void unmap_rom(offs_t start, offs_t end);
bool is_option_rom_space_available(offs_t start, int size);
diff --git a/src/devices/bus/lpci/southbridge.cpp b/src/devices/bus/lpci/southbridge.cpp
index 70bff510211..3bc4108b28e 100644
--- a/src/devices/bus/lpci/southbridge.cpp
+++ b/src/devices/bus/lpci/southbridge.cpp
@@ -182,7 +182,8 @@ void southbridge_device::device_start()
spaceio.install_readwrite_handler(0x0000, 0x001f, read8_delegate(FUNC(am9517a_device::read),&(*m_dma8237_1)), write8_delegate(FUNC(am9517a_device::write),&(*m_dma8237_1)), 0xffffffff);
spaceio.install_readwrite_handler(0x0020, 0x003f, read8_delegate(FUNC(pic8259_device::read),&(*m_pic8259_master)), write8_delegate(FUNC(pic8259_device::write),&(*m_pic8259_master)), 0xffffffff);
spaceio.install_readwrite_handler(0x0040, 0x005f, read8_delegate(FUNC(pit8254_device::read),&(*m_pit8254)), write8_delegate(FUNC(pit8254_device::write),&(*m_pit8254)), 0xffffffff);
- spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(southbridge_device::at_keybc_r),this), write8_delegate(FUNC(southbridge_device::at_keybc_w),this), 0xffffffff);
+ spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(at_keyboard_controller_device::data_r), &(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::data_w), &(*m_keybc)), 0x000000ff);
+ spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(southbridge_device::at_portb_r), this), write8_delegate(FUNC(southbridge_device::at_portb_w), this), 0x0000ff00);
spaceio.install_readwrite_handler(0x0064, 0x0067, read8_delegate(FUNC(at_keyboard_controller_device::status_r),&(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::command_w),&(*m_keybc)), 0xffffffff);
spaceio.install_readwrite_handler(0x0070, 0x007f, read8_delegate(FUNC(ds12885_device::read),&(*m_ds12885)), write8_delegate(FUNC(ds12885_device::write),&(*m_ds12885)), 0xffffffff);
spaceio.install_readwrite_handler(0x0080, 0x009f, read8_delegate(FUNC(southbridge_device::at_page8_r),this), write8_delegate(FUNC(southbridge_device::at_page8_w),this), 0xffffffff);
@@ -458,27 +459,6 @@ WRITE8_MEMBER( southbridge_device::at_dma8237_2_w )
m_dma8237_2->write( space, offset / 2, data);
}
-READ8_MEMBER( southbridge_device::at_keybc_r )
-{
- switch (offset)
- {
- case 0: return m_keybc->data_r(space, 0);
- case 1: return at_portb_r(space, 0);
- }
-
- return 0xff;
-}
-
-WRITE8_MEMBER( southbridge_device::at_keybc_w )
-{
- switch (offset)
- {
- case 0: m_keybc->data_w(space, 0, data); break;
- case 1: at_portb_w(space, 0, data); break;
- }
-}
-
-
WRITE8_MEMBER( southbridge_device::write_rtc )
{
if (offset==0) {
diff --git a/src/devices/bus/lpci/southbridge.h b/src/devices/bus/lpci/southbridge.h
index 142fcc0f98b..93d116c442b 100644
--- a/src/devices/bus/lpci/southbridge.h
+++ b/src/devices/bus/lpci/southbridge.h
@@ -121,8 +121,6 @@ private:
DECLARE_WRITE8_MEMBER(ide2_write_cs1_w);
DECLARE_READ8_MEMBER(at_dma8237_2_r);
DECLARE_WRITE8_MEMBER(at_dma8237_2_w);
- DECLARE_READ8_MEMBER(at_keybc_r);
- DECLARE_WRITE8_MEMBER(at_keybc_w);
DECLARE_WRITE8_MEMBER(write_rtc);
DECLARE_READ8_MEMBER(pc_dma_read_byte);
DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
diff --git a/src/devices/machine/intelfsh.cpp b/src/devices/machine/intelfsh.cpp
index 83e88b42dd7..ee69f2d2b19 100644
--- a/src/devices/machine/intelfsh.cpp
+++ b/src/devices/machine/intelfsh.cpp
@@ -109,9 +109,9 @@ DEFINE_DEVICE_TYPE(SHARP_UNK128MBIT, sharp_unk128mbit_device, "sharp_u
DEFINE_DEVICE_TYPE(INTEL_28F320J3D, intel_28f320j3d_device, "intel_28f320j3d", "Intel 28F320J3D Flash")
DEFINE_DEVICE_TYPE(INTEL_28F320J5, intel_28f320j5_device, "intel_28f320j5", "Intel 28F320J5 Flash")
-DEFINE_DEVICE_TYPE(SST_39VF400A, sst_39vf400a_device, "atmel_49f4096", "Atmel AT49F4096 Flash")
+DEFINE_DEVICE_TYPE(SST_39VF400A, sst_39vf400a_device, "sst_39vf400a", "SST 39VF400A Flash")
-DEFINE_DEVICE_TYPE(ATMEL_49F4096, atmel_49f4096_device, "sst_39vf400a", "SST 39VF400A Flash")
+DEFINE_DEVICE_TYPE(ATMEL_49F4096, atmel_49f4096_device, "atmel_49f4096", "Atmel AT49F4096 Flash")
//**************************************************************************
diff --git a/src/emu/debug/debugcpu.cpp b/src/emu/debug/debugcpu.cpp
index 5124204a500..dfc581d478b 100644
--- a/src/emu/debug/debugcpu.cpp
+++ b/src/emu/debug/debugcpu.cpp
@@ -767,7 +767,8 @@ u64 debugger_cpu::read_opcode(address_space &space, offs_t address, int size)
void debugger_cpu::on_vblank(screen_device &device, bool vblank_state)
{
/* just set a global flag to be consumed later */
- m_vblank_occurred = true;
+ if (vblank_state)
+ m_vblank_occurred = true;
}
diff --git a/src/emu/emumem.cpp b/src/emu/emumem.cpp
index cdbda64f396..08e0bc3e02a 100644
--- a/src/emu/emumem.cpp
+++ b/src/emu/emumem.cpp
@@ -1559,7 +1559,6 @@ memory_manager::memory_manager(running_machine &machine)
void memory_manager::allocate(device_memory_interface &memory)
{
- memory.load_configs();
for (int spacenum = 0; spacenum < memory.max_space_count(); ++spacenum)
{
// if there is a configuration for this space, we need an address space
@@ -1570,6 +1569,19 @@ void memory_manager::allocate(device_memory_interface &memory)
}
//-------------------------------------------------
+// configure - configure the address spaces
+//-------------------------------------------------
+
+void memory_manager::configure()
+{
+ // loop over devices to configure the address spaces
+ memory_interface_iterator iter(machine().root_device());
+ for (device_memory_interface &memory : iter)
+ memory.load_configs();
+ m_machine.m_dummy_space.load_configs();
+}
+
+//-------------------------------------------------
// initialize - initialize the memory system
//-------------------------------------------------
diff --git a/src/emu/emumem.h b/src/emu/emumem.h
index dd6ff5df38e..8b28aab8cfe 100644
--- a/src/emu/emumem.h
+++ b/src/emu/emumem.h
@@ -643,6 +643,7 @@ class memory_manager
public:
// construction/destruction
memory_manager(running_machine &machine);
+ void configure();
void initialize();
// getters
diff --git a/src/emu/machine.cpp b/src/emu/machine.cpp
index 3906671587c..36e107e838d 100644
--- a/src/emu/machine.cpp
+++ b/src/emu/machine.cpp
@@ -233,8 +233,12 @@ void running_machine::start()
// initialize the streams engine before the sound devices start
m_sound = std::make_unique<sound_manager>(*this);
- // first load ROMs, then populate memory, and finally initialize CPUs
- // these operations must proceed in this order
+ // configure the address spaces, load ROMs (which needs
+ // width/endianess of the spaces), then populate memory (which
+ // needs rom bases), and finally initialize CPUs (which needs
+ // complete address spaces). These operations must proceed in this
+ // order
+ m_memory.configure();
m_rom_load = make_unique_clear<rom_load_manager>(*this);
m_memory.initialize();
diff --git a/src/mame/drivers/crystal.cpp b/src/mame/drivers/crystal.cpp
index 93fe482e5b0..5c14f7b81ea 100644
--- a/src/mame/drivers/crystal.cpp
+++ b/src/mame/drivers/crystal.cpp
@@ -119,18 +119,18 @@ Notes:
P's Attack (c) 2004 Uniana Co., Ltd
-+----------1||||---1|||||--1|||||---------------------------+
++----------54321---654321--654321---------------------------+
|VOL TICKET GUN_1P GUN_2P +---------|
| | |
+-+ | 256MB |
| CC-DAC | Compact |
+-+ EMUL* | Flash |
| | |
-|J +---+ +---------|
-|A | | |
-|M | R | 25.1750MHz +--------------+|
-|M | A | | 42Pin* ||
-|A | M | +--------------+|
+|5 +---+ +---------|
+|6 | | |
+|P | R | 25.1750MHz +--------------+|
+|I | A | | 42Pin* ||
+|N | M | +--------------+|
| | | +--------------+|
|C +---+ +------------+ | SYS ||
|O | | +--------------+|
@@ -161,24 +161,69 @@ EMUL is an unpopulated 8 pin connector
EEPROM is a 93C86 16K 5.0v Serial EEPROM (2048x8-bit or 1024x16-bit)
CC-DAC is a TDA1311A Stereo Continuous Calibration DAC
+
+ P's Attack non JAMMA standard 56pin Edge Connector Pinout:
+
+ 56pin Edge Connector
+ Solder Side | Parts Side
+------------------------------------------------------------------
+ GND | A | 1 | GND
+ GND | B | 2 | GND
+ +5 | C | 3 | +5
+ +5 | D | 4 | +5
+ Player 1 Start Lamp | E | 5 | Coin Lamp
+ +12 | F | 6 | +12
+------------ KEY ------------| G | 7 |------------ KEY -----------
+ Player 1 Start Lamp | H | 8 | Coin Counter
+ L Speaker (-) | J | 9 | L Speaker (+)
+ R Speaker (-) | K | 10| R Speaker (+)
+ Video VSync | L | 11|
+ Video Green | M | 12| Video Red
+ Video Sync | N | 13| Video Blue
+ Service Switch | P | 14| Video GND
+ Video HSync | R | 15| Test Switch
+ | S | 16| Coin Switch
+ Start Player 2 | T | 17| Start Player 1
+ | U | 18|
+ | V | 19|
+ | W | 20|
+ | X | 21|
+ | Y | 22|
+ | a | 23|
+ | b | 24|
+ | d | 25|
+ | e | 26|
+ GND | f | 27| GND
+ GND | g | 28| GND
+
+
TICKET is a 5 pin connector:
- 1| +12v
- 2| IN
+ 1| LED
+ 2| GND
3| OUT
- 4| GND
- 5| LED
+ 4| IN
+ 5| +12v
-GUN_xP are 6 pin gun connectors (pins 1-4 match the UNICO sytle guns):
+GUN_xP are 6 pin gun connectors (pins 3-6 match the UNICO sytle guns):
+
+ GUN-1P: Left (Blue) Gun Connector Pinout
1| GND
- 2| SW
- 3| +5v
- 4| SENS
- 5| SOL
+ 2| Solenoid
+ 3| Sensor
+ 4| +5V
+ 5| Switch (Trigger)
6| GND
+ GUN-2P: Right (Pink) Gun Connector Pinout
+ 1| GND
+ 2| Solenoid
+ 3| Sensor
+ 4| +5V
+ 5| Switch (Trigger)
+ 6| GND
*/
diff --git a/src/mame/drivers/hh_sm510.cpp b/src/mame/drivers/hh_sm510.cpp
index 9fa47bc5674..072703b6ddf 100644
--- a/src/mame/drivers/hh_sm510.cpp
+++ b/src/mame/drivers/hh_sm510.cpp
@@ -6,7 +6,7 @@
Sharp SM5xx family handhelds.
TODO:
- - improve LCD segments in SVGs for: gnw_mc25, gnw_eg26, gnw_jr55, gnw_mw56, exospace
+ - improve LCD segments in SVGs for: gnw_mc25, gnw_eg26, exospace
- SVG background/foreground vector graphics where possible. Doesn't apply to eg. the
Konami games where MAME's SVG renderer needs to add support for embedded images.
- confirm gnw_mc25/gnw_eg26 rom (dumped from Soviet clone, but pretty confident that it's same)
@@ -853,13 +853,13 @@ static MACHINE_CONFIG_START( jr55 )
/* video hardware */
MCFG_SCREEN_SVG_ADD("screen_top", "svg_top")
MCFG_SCREEN_REFRESH_RATE(50)
- MCFG_SCREEN_SIZE(1920/2, 1225/2)
- MCFG_SCREEN_VISIBLE_AREA(0, 1920/2-1, 0, 1225/2-1)
+ MCFG_SCREEN_SIZE(1920/2, 1229/2)
+ MCFG_SCREEN_VISIBLE_AREA(0, 1920/2-1, 0, 1229/2-1)
MCFG_SCREEN_SVG_ADD("screen_bottom", "svg_bottom")
MCFG_SCREEN_REFRESH_RATE(50)
- MCFG_SCREEN_SIZE(1920/2, 1261/2)
- MCFG_SCREEN_VISIBLE_AREA(0, 1920/2-1, 0, 1261/2-1)
+ MCFG_SCREEN_SIZE(1920/2, 1238/2)
+ MCFG_SCREEN_VISIBLE_AREA(0, 1920/2-1, 0, 1238/2-1)
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_sm510_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_gnw_dualv)
@@ -935,13 +935,13 @@ static MACHINE_CONFIG_START( mw56 )
/* video hardware */
MCFG_SCREEN_SVG_ADD("screen_left", "svg_left")
MCFG_SCREEN_REFRESH_RATE(50)
- MCFG_SCREEN_SIZE(2087/2, 1440/2)
- MCFG_SCREEN_VISIBLE_AREA(0, 2087/2-1, 0, 1440/2-1)
+ MCFG_SCREEN_SIZE(2258/2, 1440/2)
+ MCFG_SCREEN_VISIBLE_AREA(0, 2258/2-1, 0, 1440/2-1)
MCFG_SCREEN_SVG_ADD("screen_right", "svg_right")
MCFG_SCREEN_REFRESH_RATE(50)
- MCFG_SCREEN_SIZE(2079/2, 1440/2)
- MCFG_SCREEN_VISIBLE_AREA(0, 2079/2-1, 0, 1440/2-1)
+ MCFG_SCREEN_SIZE(2261/2, 1440/2)
+ MCFG_SCREEN_VISIBLE_AREA(0, 2261/2-1, 0, 1440/2-1)
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_sm510_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_gnw_dualh)
@@ -1329,11 +1329,11 @@ ROM_START( gnw_jr55 )
ROM_REGION( 0x1000, "maincpu", 0 )
ROM_LOAD( "jr-55_cms54c_kms560", 0x0000, 0x1000, CRC(46aed0ae) SHA1(72f75ccbd84aea094148c872fc7cc1683619a18a) )
- ROM_REGION( 207397, "svg_top", 0)
- ROM_LOAD( "gnw_jr55_top.svg", 0, 207397, CRC(715b5bf3) SHA1(2b4ba476ecb2f02835df651a94d6a8b8be74112d) )
+ ROM_REGION( 261499, "svg_top", 0)
+ ROM_LOAD( "gnw_jr55_top.svg", 0, 261499, CRC(3e48708f) SHA1(fc35bd4022327f2061d054c23316d2d6412b25b7) )
- ROM_REGION( 200030, "svg_bottom", 0)
- ROM_LOAD( "gnw_jr55_bottom.svg", 0, 200030, CRC(0cfefd3f) SHA1(516802d53334582e6c25c96d60afed11351bb1ca) )
+ ROM_REGION( 389658, "svg_bottom", 0)
+ ROM_LOAD( "gnw_jr55_bottom.svg", 0, 389658, CRC(0a5eb4b2) SHA1(498aded148401a624a4ed215126e0d0b27d25d44) )
ROM_END
@@ -1341,11 +1341,11 @@ ROM_START( gnw_mw56 )
ROM_REGION( 0x1000, "maincpu", 0 )
ROM_LOAD( "mw-56", 0x0000, 0x1000, CRC(385e59da) SHA1(2f79281bdf2f2afca2fb5bd7b9a3beeffc9c4eb7) )
- ROM_REGION( 100251, "svg_left", 0)
- ROM_LOAD( "gnw_mw56_left.svg", 0, 100251, CRC(bca1048b) SHA1(a9b213cf9243c9e332619afac125f0549cf40757) )
+ ROM_REGION( 165452, "svg_left", 0)
+ ROM_LOAD( "gnw_mw56_left.svg", 0, 165452, CRC(07fda7f3) SHA1(4c884e57963cef4f22263afd7fe3cd72cd1cd756) )
- ROM_REGION( 85767, "svg_right", 0)
- ROM_LOAD( "gnw_mw56_right.svg", 0, 85767, CRC(336a3b59) SHA1(73d9985b199146c48ec854967e075047ae1d22da) )
+ ROM_REGION( 224225, "svg_right", 0)
+ ROM_LOAD( "gnw_mw56_right.svg", 0, 224225, CRC(515e1a7a) SHA1(e63419f6f7784b1a0a75e6e29c806a3abe2d7a42) )
ROM_END
diff --git a/src/mame/drivers/intellec4.cpp b/src/mame/drivers/intellec4.cpp
index c803beeb971..8451e8f270d 100644
--- a/src/mame/drivers/intellec4.cpp
+++ b/src/mame/drivers/intellec4.cpp
@@ -1,4 +1,4 @@
-// license:BSD-3-Clause
+// license:BSD-3-Clause
// copyright-holders:Vas Crabb
/*
Intel INTELLEC® 4/MOD 40
diff --git a/src/mame/drivers/interpro.cpp b/src/mame/drivers/interpro.cpp
index 8747c865ad0..1064cadbaa1 100644
--- a/src/mame/drivers/interpro.cpp
+++ b/src/mame/drivers/interpro.cpp
@@ -3,8 +3,6 @@
#include "emu.h"
-#define NEW_SCSI 1
-
#include "includes/interpro.h"
#include "debugger.h"
@@ -262,7 +260,6 @@ READ8_MEMBER(interpro_state::rtc_r)
READ8_MEMBER(interpro_state::scsi_r)
{
-#if NEW_SCSI
switch (offset >> 6)
{
case 0x0: return m_scsi->tcounter_lo_r(space, 0);
@@ -275,19 +272,14 @@ READ8_MEMBER(interpro_state::scsi_r)
case 0x7: return m_scsi->fifo_flags_r(space, 0);
case 0x8: return m_scsi->conf_r(space, 0);
case 0xb: return m_scsi->conf2_r(space, 0);
- case 0xc: return m_scsi->conf3_r(space, 0);
}
- logerror("read unmapped scsi adapter register 0x%x\n", offset >> 6);
- return 0x00;
-#else
- return m_scsi->read(space, offset >> 6, mem_mask);
-#endif
+ logerror("scsi: read unmapped register 0x%x (%s)\n", offset >> 6, machine().describe_context());
+ return space.unmap();
}
WRITE8_MEMBER(interpro_state::scsi_w)
{
-#if NEW_SCSI
switch (offset >> 6)
{
case 0: m_scsi->tcount_lo_w(space, 0, data); return;
@@ -302,36 +294,9 @@ WRITE8_MEMBER(interpro_state::scsi_w)
case 9: m_scsi->clock_w(space, 0, data); return;
case 0xa: m_scsi->test_w(space, 0, data); return;
case 0xb: m_scsi->conf2_w(space, 0, data); return;
- case 0xc: m_scsi->conf3_w(space, 0, data); return;
- case 0xf: m_scsi->fifo_align_w(space, 0, data); return;
}
- logerror("unmapped scsi register write 0x%02x data 0x%02x\n", offset >> 6, data);
-#else
- m_scsi->write(space, offset >> 6, data, mem_mask);
-#endif
-}
-
-READ8_MEMBER(interpro_state::scsi_dma_r)
-{
-#if NEW_SCSI
- return m_scsi->dma_r();
-#else
- u8 data = 0;
-
- m_scsi->dma_read_data(1, &data);
-
- return data;
-#endif
-}
-
-WRITE8_MEMBER(interpro_state::scsi_dma_w)
-{
-#if NEW_SCSI
- m_scsi->dma_w(data);
-#else
- m_scsi->dma_write_data(1, &data);
-#endif
+ logerror("scsi: unmapped register write 0x%02x data 0x%02x (%s)\n", offset >> 6, data, machine().describe_context());
}
DRIVER_INIT_MEMBER(interpro_state, ip2800)
@@ -351,19 +316,17 @@ DRIVER_INIT_MEMBER(interpro_state, ip2800)
space.install_ram(0, m_ram->mask(), m_ram->pointer());
}
-#if NEW_SCSI
static SLOT_INTERFACE_START(interpro_scsi_devices)
SLOT_INTERFACE("harddisk", NSCSI_HARDDISK)
SLOT_INTERFACE("cdrom", NSCSI_CDROM)
- SLOT_INTERFACE_INTERNAL(INTERPRO_SCSI_ADAPTER_TAG, NCR53C94)
+ SLOT_INTERFACE_INTERNAL(INTERPRO_SCSI_ADAPTER_TAG, NCR53C90A)
SLOT_INTERFACE_END
static MACHINE_CONFIG_START(interpro_scsi_adapter)
- MCFG_DEVICE_CLOCK(XTAL_12_5MHz)
+ MCFG_DEVICE_CLOCK(XTAL_24MHz)
MCFG_NCR5390_IRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, ir0_w))
MCFG_NCR5390_DRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, drq_scsi))
MACHINE_CONFIG_END
-#endif
// these maps point the cpu virtual addresses to the mmu
static ADDRESS_MAP_START(clipper_insn_map, AS_PROGRAM, 32, interpro_state)
@@ -503,7 +466,6 @@ static MACHINE_CONFIG_START(ip2800)
MCFG_FLOPPY_DRIVE_SOUND(false)
// scsi
-#if NEW_SCSI
MCFG_NSCSI_BUS_ADD(INTERPRO_SCSI_TAG)
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":0", interpro_scsi_devices, "harddisk", false)
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":1", interpro_scsi_devices, nullptr, false)
@@ -514,16 +476,6 @@ static MACHINE_CONFIG_START(ip2800)
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":6", interpro_scsi_devices, nullptr, false)
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":7", interpro_scsi_devices, INTERPRO_SCSI_ADAPTER_TAG, true)
MCFG_DEVICE_CARD_MACHINE_CONFIG(INTERPRO_SCSI_ADAPTER_TAG, interpro_scsi_adapter)
-#else
- MCFG_DEVICE_ADD(INTERPRO_SCSI_TAG, SCSI_PORT, 0)
- MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE1, "harddisk", SCSIHD, SCSI_ID_0)
- MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE3, "cdrom", SCSICD, SCSI_ID_3)
-
- MCFG_DEVICE_ADD(INTERPRO_SCSI_ADAPTER_TAG, NCR539X, XTAL_12_5MHz)
- MCFG_LEGACY_SCSI_PORT(INTERPRO_SCSI_TAG)
- MCFG_NCR539X_OUT_IRQ_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, ir0_w))
- MCFG_NCR539X_OUT_DRQ_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, drq_scsi))
-#endif
// i/o gate array
MCFG_INTERPRO_IOGA_ADD(INTERPRO_IOGA_TAG)
@@ -531,9 +483,7 @@ static MACHINE_CONFIG_START(ip2800)
MCFG_INTERPRO_IOGA_IRQ_CB(INPUTLINE(INTERPRO_CPU_TAG, INPUT_LINE_IRQ0))
//MCFG_INTERPRO_IOGA_DMA_CB(IOGA_DMA_CHANNEL_PLOTTER, unknown)
- // use driver helper functions to wrap scsi adapter dma read/write
- MCFG_INTERPRO_IOGA_DMA_CB(IOGA_DMA_SCSI, DEVREAD8("", interpro_state, scsi_dma_r), DEVWRITE8("", interpro_state, scsi_dma_w))
-
+ MCFG_INTERPRO_IOGA_DMA_CB(IOGA_DMA_SCSI, DEVREAD8(INTERPRO_SCSI_DEVICE_TAG, ncr53c90a_device, mdma_r), DEVWRITE8(INTERPRO_SCSI_DEVICE_TAG, ncr53c90a_device, mdma_w))
MCFG_INTERPRO_IOGA_DMA_CB(IOGA_DMA_FLOPPY, DEVREAD8(INTERPRO_FDC_TAG, n82077aa_device, mdma_r), DEVWRITE8(INTERPRO_FDC_TAG, n82077aa_device, mdma_w))
MCFG_INTERPRO_IOGA_DMA_CB(IOGA_DMA_SERIAL, DEVREAD8(INTERPRO_SCC1_TAG, z80scc_device, da_r), DEVWRITE8(INTERPRO_SCC1_TAG, z80scc_device, da_w))
MCFG_INTERPRO_IOGA_FDCTC_CB(DEVWRITELINE(INTERPRO_FDC_TAG, n82077aa_device, tc_line_w))
diff --git a/src/mame/drivers/megasys1.cpp b/src/mame/drivers/megasys1.cpp
index 755edb6e705..3e96df7ad6a 100644
--- a/src/mame/drivers/megasys1.cpp
+++ b/src/mame/drivers/megasys1.cpp
@@ -3645,8 +3645,19 @@ ROM_START( rodlandj )
ROM_LOAD( "PS89013A.M14", 0x0000, 0x0200, CRC(8914e72d) SHA1(80a664471f14c8ed8544a5e226fdca425ab3c657) )
ROM_END
-/* probably a prototype, original JP key and unscrambled ROMs, incorrect
- audio matches PCB */
+/*
+
+Prototype or test location. Original Japanese key and unscrambled ROMs, incorrect audio matches actual PCB.
+
+Title is controlled by the value at 0xF0D7A - 0x00 for Japan region and Rod-Land title / 0x01 for Export and R&T title.
+ These same locations and values work for the Japanese set, but not the Export version. In R&T 0xF0D7A is initialized to 0x01
+
+To access the hidden Location Test Table, during the attaction mode at the title screen with NO Coins / Credits, use Player 1
+ controls to enter:
+
+ D U B1 D D B2 U U B1 B2
+
+ */
ROM_START( rittam )
ROM_REGION( 0x60000, "maincpu", 0 ) /* Main CPU Code */
ROM_LOAD16_BYTE( "2.ROM2", 0x000000, 0x020000, CRC(93085af2) SHA1(e49dc1e62c1cec75f192ac4608f69c4361ad739a) )
@@ -4613,7 +4624,7 @@ GAME( 1989, stdragona,stdragon, system_A, stdragon, megasys1_state, std
GAME( 1989, stdragonb,stdragon, system_A, stdragon, megasys1_state, stdragonb,ROT0, "bootleg","Saint Dragon (bootleg)", MACHINE_SUPPORTS_SAVE )
GAME( 1990, rodland, 0, system_A, rodland, megasys1_state, rodland, ROT0, "Jaleco", "Rod-Land (World)", MACHINE_SUPPORTS_SAVE )
GAME( 1990, rodlandj, rodland, system_A, rodland, megasys1_state, rodlandj, ROT0, "Jaleco", "Rod-Land (Japan)", MACHINE_SUPPORTS_SAVE )
-GAME( 1990, rittam, rodland, system_A, rodland, megasys1_state, rittam, ROT0, "Jaleco", "R&T (Rod-Land prototype?)", MACHINE_SUPPORTS_SAVE )
+GAME( 1990, rittam, rodland, system_A, rodland, megasys1_state, rittam, ROT0, "Jaleco", "R&T (Rod-Land prototype)", MACHINE_SUPPORTS_SAVE )
GAME( 1990, rodlandjb,rodland, system_A, rodland, megasys1_state, rodlandjb,ROT0, "bootleg","Rod-Land (Japan bootleg)", MACHINE_SUPPORTS_SAVE )
GAME( 1990, phantasm, avspirit, system_A, phantasm, megasys1_state, phantasm, ROT0, "Jaleco", "Phantasm (Japan)", MACHINE_SUPPORTS_SAVE )
GAME( 1991, edfp, edf, system_A, edfp, megasys1_state, edfp, ROT0, "Jaleco", "E.D.F. : Earth Defense Force (Japan, prototype)", MACHINE_SUPPORTS_SAVE )
diff --git a/src/mame/drivers/shootaway2.cpp b/src/mame/drivers/shootaway2.cpp
index bf41b769f22..71a31a0ad65 100644
--- a/src/mame/drivers/shootaway2.cpp
+++ b/src/mame/drivers/shootaway2.cpp
@@ -95,11 +95,14 @@ static MACHINE_CONFIG_START( m74 )
MACHINE_CONFIG_END
ROM_START(shootaw2)
+ ROM_REGION(0x20000, "maincpu", 0) /* C68 / M37450 program ROM */
+ ROM_LOAD( "sas1_mpr0c.8l", 0x000000, 0x020000, CRC(21379550) SHA1(2f2b43ca526d1a77c80f81d0e1f22155d90f725d) )
+
ROM_REGION(0x80000, "subcpu", 0) /* Z84C011 program ROM */
ROM_LOAD( "sas1_spr0.7f", 0x000000, 0x080000, CRC(3bc14ba3) SHA1(7a75281621f23107c5c3c1a09831be2f8bb93540) )
- ROM_REGION(0x20000, "maincpu", 0) /* C68 / M37450 program ROM */
- ROM_LOAD( "sas1_mpr0c.8l", 0x000000, 0x020000, CRC(21379550) SHA1(2f2b43ca526d1a77c80f81d0e1f22155d90f725d) )
+ ROM_REGION(0x2000, "at28c64", 0) /* AT28C64 parallel EEPROM (not yet supported by MAME) */
+ ROM_LOAD( "m28c64a.9l", 0x000000, 0x002000, CRC(d65d4176) SHA1(dd9b529a729685f9535ae7f060f67d75d70d9567) )
ROM_REGION(0x40000, "oki", 0)
ROM_LOAD( "unknown_label.5e", 0x000000, 0x040000, CRC(fa75e91e) SHA1(d06ca906135a3f23c1f0dadff75f940ea7ca0e4a) )
diff --git a/src/mame/drivers/sun1.cpp b/src/mame/drivers/sun1.cpp
index 48f89b79425..fed55a057a0 100644
--- a/src/mame/drivers/sun1.cpp
+++ b/src/mame/drivers/sun1.cpp
@@ -50,9 +50,9 @@
****************************************************************************/
#include "emu.h"
+#include "bus/rs232/rs232.h"
#include "cpu/m68000/m68000.h"
-#include "machine/z80dart.h"
-#include "machine/terminal.h"
+#include "machine/z80sio.h"
#define TERMINAL_TAG "terminal"
@@ -60,55 +60,31 @@ class sun1_state : public driver_device
{
public:
sun1_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
- m_maincpu(*this, "maincpu"),
- m_terminal(*this, TERMINAL_TAG),
- m_p_ram(*this, "p_ram")
+ : driver_device(mconfig, type, tag)
+ , m_maincpu(*this, "maincpu")
+ , m_iouart(*this, "iouart")
+ , m_p_ram(*this, "p_ram")
{
}
- DECLARE_READ16_MEMBER(sun1_upd7201_r);
- DECLARE_WRITE16_MEMBER(sun1_upd7201_w);
- void kbd_put(u8 data);
-
protected:
virtual void machine_reset() override;
required_device<cpu_device> m_maincpu;
- required_device<generic_terminal_device> m_terminal;
+ required_device<upd7201_new_device> m_iouart;
required_shared_ptr<uint16_t> m_p_ram;
- uint8_t m_term_data;
};
-
-// Just hack to show output since upd7201 is not implemented yet
-
-READ16_MEMBER( sun1_state::sun1_upd7201_r )
-{
- uint16_t ret;
- if (offset == 0)
- {
- ret = m_term_data << 8;
- m_term_data = 0;
- }
- else
- ret = 0xfeff | (m_term_data ? 0x100 : 0);
-
- return ret;
-}
-
-WRITE16_MEMBER( sun1_state::sun1_upd7201_w )
-{
- if (offset == 0)
- m_terminal->write(space, 0, data >> 8);
-}
-
static ADDRESS_MAP_START(sun1_mem, AS_PROGRAM, 16, sun1_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("p_ram") // 512 KB RAM / ROM at boot
AM_RANGE(0x00200000, 0x00203fff) AM_ROM AM_REGION("user1",0)
- AM_RANGE(0x00600000, 0x00600007) AM_READWRITE( sun1_upd7201_r, sun1_upd7201_w )
+ AM_RANGE(0x00600000, 0x006000ff) AM_DEVREADWRITE8("iouart", upd7201_new_device, ba_cd_r, ba_cd_w, 0xff00)
+ AM_RANGE(0x00800000, 0x008000ff) AM_UNMAP // AM9513 timer at 5MHz
+ AM_RANGE(0x00a00000, 0x00bfffff) AM_UNMAP // page map
+ AM_RANGE(0x00c00000, 0x00dfffff) AM_UNMAP // segment map
+ AM_RANGE(0x00e00000, 0x00ffffff) AM_UNMAP // context register
ADDRESS_MAP_END
/* Input ports */
@@ -123,34 +99,46 @@ void sun1_state::machine_reset()
memcpy((uint8_t*)m_p_ram.target(),user1,0x4000);
m_maincpu->reset();
- m_term_data = 0;
}
-void sun1_state::kbd_put(u8 data)
-{
- m_term_data = data;
-}
-
static MACHINE_CONFIG_START( sun1 )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68000, XTAL_10MHz)
MCFG_CPU_PROGRAM_MAP(sun1_mem)
- /* video hardware */
- MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
- MCFG_GENERIC_TERMINAL_KEYBOARD_CB(PUT(sun1_state, kbd_put))
+ // UART is actually clocked by AM9513 (channel 4 = port A, channel 5 = port B)
+ MCFG_UPD7201_ADD("iouart", 0, 9600*16, 9600*16, 9600*16, 9600*16)
+ MCFG_Z80SIO_OUT_TXDA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_txd))
+ MCFG_Z80SIO_OUT_DTRA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_dtr))
+ MCFG_Z80SIO_OUT_RTSA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_rts))
+ MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd))
+ MCFG_Z80SIO_OUT_DTRB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_dtr))
+ MCFG_Z80SIO_OUT_RTSB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_rts))
+
+ MCFG_RS232_PORT_ADD("rs232a", default_rs232_devices, "terminal")
+ MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, rxa_w))
+ MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, ctsa_w))
+ MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, dcda_w))
+
+ MCFG_RS232_PORT_ADD("rs232b", default_rs232_devices, nullptr)
+ MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, rxb_w))
+ MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, ctsb_w))
+ MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_new_device, dcdb_w))
MACHINE_CONFIG_END
/* ROM definition */
ROM_START( sun1 )
ROM_REGION( 0x4000, "user1", ROMREGION_ERASEFF )
- ROM_LOAD16_BYTE( "v10.8.bin", 0x0001, 0x2000, CRC(3528a0f8) SHA1(be437dd93d1a44eccffa6f5e05935119482beab0))
- ROM_LOAD16_BYTE( "v10.0.bin", 0x0000, 0x2000, CRC(1ad4c52a) SHA1(4bc1a19e8f202378d5d7baa8b95319275c040a6d))
+ ROM_DEFAULT_BIOS("1.0")
+
+ ROM_SYSTEM_BIOS(0, "1.0", "Sun Monitor 1.0")
+ ROMX_LOAD( "v10.8.bin", 0x0001, 0x2000, CRC(3528a0f8) SHA1(be437dd93d1a44eccffa6f5e05935119482beab0), ROM_SKIP(1)|ROM_BIOS(1))
+ ROMX_LOAD( "v10.0.bin", 0x0000, 0x2000, CRC(1ad4c52a) SHA1(4bc1a19e8f202378d5d7baa8b95319275c040a6d), ROM_SKIP(1)|ROM_BIOS(1))
- ROM_REGION( 0x4000, "diag", ROMREGION_ERASEFF )
- ROM_LOAD16_BYTE( "8mhzdiag.8.bin", 0x0001, 0x2000, CRC(808a549e) SHA1(d2aba014a5507c1538f2c1a73e1d2524f28034f4))
- ROM_LOAD16_BYTE( "8mhzdiag.0.bin", 0x0000, 0x2000, CRC(7a92d506) SHA1(5df3800f7083293fc01bb6a7e7538ad425bbebfb))
+ ROM_SYSTEM_BIOS(1, "diag", "Interactive Tests")
+ ROMX_LOAD( "8mhzdiag.8.bin", 0x0001, 0x2000, CRC(808a549e) SHA1(d2aba014a5507c1538f2c1a73e1d2524f28034f4), ROM_SKIP(1)|ROM_BIOS(2))
+ ROMX_LOAD( "8mhzdiag.0.bin", 0x0000, 0x2000, CRC(7a92d506) SHA1(5df3800f7083293fc01bb6a7e7538ad425bbebfb), ROM_SKIP(1)|ROM_BIOS(2))
ROM_REGION( 0x10000, "gfx", ROMREGION_ERASEFF )
ROM_LOAD( "gfxu605.g4.bin", 0x0000, 0x0200, CRC(274b7b3d) SHA1(40d8be2cfcbd03512a05925991bb5030d5d4b5e9))
diff --git a/src/mame/includes/interpro.h b/src/mame/includes/interpro.h
index 021dfc50325..543cb147285 100644
--- a/src/mame/includes/interpro.h
+++ b/src/mame/includes/interpro.h
@@ -19,19 +19,12 @@
#include "machine/z80scc.h"
#include "machine/mc146818.h"
#include "machine/upd765.h"
-#if NEW_SCSI
-#include "machine/ncr5390.h"
+#include "machine/ncr5390.h"
#include "machine/nscsi_bus.h"
#include "machine/nscsi_cd.h"
#include "machine/nscsi_hd.h"
-#else
-#include "machine/ncr539x.h"
-#include "bus/scsi/scsi.h"
-#include "bus/scsi/scsicd.h"
-#include "bus/scsi/scsihd.h"
-#endif
#include "bus/rs232/rs232.h"
#include "formats/pc_dsk.h"
@@ -52,6 +45,7 @@
#define INTERPRO_FDC_TAG "fdc"
#define INTERPRO_SCSI_TAG "scsi"
#define INTERPRO_SCSI_ADAPTER_TAG "adapter"
+#define INTERPRO_SCSI_DEVICE_TAG INTERPRO_SCSI_TAG ":7:" INTERPRO_SCSI_ADAPTER_TAG
#define INTERPRO_IOGA_TAG "ioga"
#define INTERPRO_MCGA_TAG "mcga"
@@ -70,12 +64,8 @@ public:
m_scc2(*this, INTERPRO_SCC2_TAG),
m_rtc(*this, INTERPRO_RTC_TAG),
m_fdc(*this, INTERPRO_FDC_TAG),
-#if NEW_SCSI
m_scsibus(*this, INTERPRO_SCSI_TAG),
- m_scsi(*this, INTERPRO_SCSI_TAG ":7:" INTERPRO_SCSI_ADAPTER_TAG),
-#else
- m_scsi(*this, INTERPRO_SCSI_ADAPTER_TAG),
-#endif
+ m_scsi(*this, INTERPRO_SCSI_DEVICE_TAG),
m_ioga(*this, INTERPRO_IOGA_TAG),
m_mcga(*this, INTERPRO_MCGA_TAG),
m_sga(*this, INTERPRO_SGA_TAG),
@@ -92,13 +82,8 @@ public:
required_device<z80scc_device> m_scc2;
required_device<mc146818_device> m_rtc;
required_device<n82077aa_device> m_fdc;
-#if NEW_SCSI
required_device<nscsi_bus_device> m_scsibus;
- required_device<ncr53c94_device> m_scsi;
-#else
- required_device<ncr539x_device> m_scsi;
-#endif
-
+ required_device<ncr53c90a_device> m_scsi;
required_device<interpro_ioga_device> m_ioga;
required_device<interpro_fmcc_device> m_mcga;
required_device<interpro_sga_device> m_sga;
@@ -137,9 +122,9 @@ public:
CTRL1_FLOPRDY = 0x0002,
CTRL1_LEDENA = 0x0004,
CTRL1_LEDDP = 0x0008,
- CTRL1_ETHLOOP = 0x0010,
+ CTRL1_ETHLOOP = 0x0010, // remote modem loopback
CTRL1_ETHDTR = 0x0020,
- CTRL1_ETHRMOD = 0x0040,
+ CTRL1_ETHRMOD = 0x0040, // remote modem configured active low
CTRL1_CLIPRESET = 0x0040,
CTRL1_FIFOACTIVE = 0x0080
};
@@ -176,8 +161,6 @@ public:
DECLARE_READ8_MEMBER(scsi_r);
DECLARE_WRITE8_MEMBER(scsi_w);
- DECLARE_READ8_MEMBER(scsi_dma_r);
- DECLARE_WRITE8_MEMBER(scsi_dma_w);
DECLARE_FLOPPY_FORMATS(floppy_formats);
diff --git a/src/mame/machine/interpro_ioga.cpp b/src/mame/machine/interpro_ioga.cpp
index 236b64b0d7b..010791f5165 100644
--- a/src/mame/machine/interpro_ioga.cpp
+++ b/src/mame/machine/interpro_ioga.cpp
@@ -18,10 +18,13 @@
#include "emu.h"
#include "interpro_ioga.h"
+// the following enables some hacks which will allow all iogadiag tests to complete successfully, but also breaks scsi dma
+#define IOGA_DMA_DIAG_HACK 0
+
#define LOG_GENERAL (1 << 31)
-#define LOG_HWINT_ENABLE 0 //((1<<3) | LOG_GENERAL)
-#define LOG_DMA_ENABLE ((1<<IOGA_DMA_FLOPPY) | LOG_GENERAL)
-#define LOG_TIMER_ENABLE 0
+#define LOG_HWINT_ENABLE 0
+#define LOG_DMA_ENABLE 0
+#define LOG_TIMER_ENABLE 0
#define VERBOSE 0
@@ -30,14 +33,20 @@
#define LOG_TIMER(timer, ...) if (LOG_TIMER_ENABLE & (1 << timer)) logerror(__VA_ARGS__)
#define LOG_HWINT(interrupt, ...) if (LOG_HWINT_ENABLE & (1 << interrupt)) logerror(__VA_ARGS__)
#define LOG_DMA(channel, ...) if (LOG_DMA_ENABLE & (1 << channel)) logerror(__VA_ARGS__)
+#define LOG_ETH(...) logerror(__VA_ARGS__)
#else
#define LOG_INTERRUPT(...)
#define LOG_TIMER(timer, ...)
#define LOG_HWINT(interrupt, ...)
#define LOG_DMA(channel, ...)
+#define LOG_ETH(...)
#endif
DEVICE_ADDRESS_MAP_START(map, 32, interpro_ioga_device)
+ AM_RANGE(0x00, 0x03) AM_READWRITE(eth_remap_r, eth_remap_w)
+ AM_RANGE(0x04, 0x07) AM_READWRITE(eth_map_page_r, eth_map_page_w)
+ AM_RANGE(0x08, 0x0b) AM_READWRITE(eth_control_r, eth_control_w)
+
AM_RANGE(0x0c, 0x1b) AM_READWRITE(dma_plotter_r, dma_plotter_w)
AM_RANGE(0x1c, 0x1f) AM_READWRITE(dma_plotter_eosl_r, dma_plotter_eosl_w)
AM_RANGE(0x20, 0x2f) AM_READWRITE(dma_scsi_r, dma_scsi_w)
@@ -70,10 +79,10 @@ interpro_ioga_device::interpro_ioga_device(const machine_config &mconfig, const
m_out_irq_func(*this),
m_memory_space(nullptr),
m_dma_channel{
- { 0,0,0,0,false, 0, {*this}, {*this}, ARBCTL_BGR_PLOT },
- { 0,0,0,0,false, 0, {*this}, {*this}, ARBCTL_BGR_SCSI },
- { 0,0,0,0,false, 0, {*this}, {*this}, ARBCTL_BGR_FDC },
- { 0,0,0,0,false, 0, {*this}, {*this}, ARBCTL_BGR_SER0 | ARBCTL_BGR_SER1 | ARBCTL_BGR_SER2 } },
+ { 0,0,0,0,IDLE, {*this}, {*this}, ARBCTL_BGR_PLOT, IOGA_DMA_PLOTTER, "plotter" },
+ { 0,0,0,0,IDLE, {*this}, {*this}, ARBCTL_BGR_SCSI, IOGA_DMA_SCSI, "scsi" },
+ { 0,0,0,0,IDLE, {*this}, {*this}, ARBCTL_BGR_FDC, IOGA_DMA_FLOPPY, "floppy" },
+ { 0,0,0,0,IDLE, {*this}, {*this}, ARBCTL_BGR_SER0 | ARBCTL_BGR_SER1 | ARBCTL_BGR_SER2, IOGA_DMA_SERIAL, "serial" } },
m_fdc_tc_func(*this)
{
}
@@ -135,10 +144,7 @@ void interpro_ioga_device::device_start()
for (auto & timer : m_timer)
timer->enable(false);
- // allocate timer for DMA controller
- m_dma_timer = timer_alloc(IOGA_TIMER_DMA);
- m_dma_timer->adjust(attotime::never);
-
+ // allocate ioga interrupt and dma timer
m_ioga_clock = timer_alloc(IOGA_CLOCK);
m_ioga_clock->adjust(attotime::never);
}
@@ -157,7 +163,7 @@ void interpro_ioga_device::device_reset()
m_timer_reg[0] = 0;
//m_timer[0]->adjust(attotime::zero, IOGA_TIMER_0, attotime::from_hz(60));
- // configure ioga clock timer
+ // configure ioga interrupt and dma timer
m_ioga_clock->adjust(attotime::zero, IOGA_CLOCK, attotime::from_hz(clock()));
}
@@ -282,12 +288,9 @@ void interpro_ioga_device::device_timer(emu_timer &timer, device_timer_id id, in
}
break;
- case IOGA_TIMER_DMA:
- dma_clock(param);
- break;
-
case IOGA_CLOCK:
interrupt_clock();
+ dma_clock();
break;
}
}
@@ -482,7 +485,8 @@ void interpro_ioga_device::interrupt_clock()
if (m_nmi_pending)
{
// check if nmi is enabled
- if ((m_nmictrl & NMI_IE) == NMI_IE)
+ if (((m_nmictrl & NMI_IE) == NMI_IE)
+ || ((m_nmictrl & (NMI_ALL | NMI_ENABLE1)) == (NMI_ALL | NMI_ENABLE1)))
{
LOG_INTERRUPT("nmi: accepting nmi\n");
@@ -607,7 +611,10 @@ WRITE8_MEMBER(interpro_ioga_device::nmictrl_w)
// check for a forced nmi (NMI_NEGPOL written from 1 to 0 with NMI_IE set)
if ((m_nmictrl & NMI_NEGPOL) && (data & (NMI_NEGPOL | NMI_IE)) == NMI_IE)
+ {
+ LOG_INTERRUPT("nmi: forced nmi\n");
m_nmi_pending = true;
+ }
m_nmictrl = data;
}
@@ -628,136 +635,223 @@ WRITE16_MEMBER(interpro_ioga_device::softint_vector_w)
/******************************************************************************
DMA
******************************************************************************/
-void interpro_ioga_device::dma_clock(int channel)
+void interpro_ioga_device::dma_clock()
{
- struct dma &dma_channel = m_dma_channel[channel];
-
- // if bus grant is not enabled, set the busy flag (iogadiag test 7.0265)
- if (!(m_arbctl & dma_channel.arb_mask))
+ for (auto &dma_channel : m_dma_channel)
{
- dma_channel.control |= DMA_CTRL_BUSY;
- m_dma_channel[channel].control |= DMA_CTRL_BUSY;
- m_dma_timer->adjust(attotime::from_hz(clock()), channel);
+ switch (dma_channel.state)
+ {
+ case IDLE:
+ break;
- return;
- }
- else
- dma_channel.control &= ~DMA_CTRL_BUSY;
+ case COMMAND:
+ // start a command
+ // HACK: busy flag indicates bus access required?
+ if (dma_channel.control & DMA_CTRL_BUSY)
+ dma_channel.state = WAIT;
+ else
+ dma_channel.state = COMPLETE;
+ break;
- // if the channel isn't active yet, make it active and log something
- if (!dma_channel.dma_active)
- {
- LOG_DMA(channel, "dma: transfer %s device begun, channel = %d, control 0x%08x, real address 0x%08x, virtual address 0x%08x, count 0x%08x\n",
- (dma_channel.control & DMA_CTRL_WRITE) ? "to" : "from",
- channel, dma_channel.control, dma_channel.real_address, dma_channel.virtual_address, dma_channel.transfer_count);
- dma_channel.dma_active = true;
- }
+ case WAIT:
+ // if bus grant is enabled, clear wait flag and execute transfer
+ if (m_arbctl & dma_channel.arb_mask)
+ {
+ // clear bus wait flag
+ dma_channel.control &= ~DMA_CTRL_WAIT;
- // transfer data while the device is requesting a data transfer and the transfer count is not zero
- while (dma_channel.drq_state && dma_channel.transfer_count)
- {
- // transfer from the memory to device or device to memory
- if (dma_channel.control & DMA_CTRL_WRITE)
- dma_channel.device_w(m_memory_space->read_byte(dma_channel.real_address));
- else
- m_memory_space->write_byte(dma_channel.real_address, dma_channel.device_r());
+ LOG_DMA(dma_channel.channel, "dma: transfer %s device begun, channel = %d, control 0x%08x, real address 0x%08x, virtual address 0x%08x, count 0x%08x\n",
+ (dma_channel.control & DMA_CTRL_WRITE) ? "to" : "from",
+ dma_channel.channel, dma_channel.control, dma_channel.real_address, dma_channel.virtual_address, dma_channel.transfer_count);
- // increment addresses and decrement count
- dma_channel.real_address++;
- dma_channel.virtual_address++;
- dma_channel.transfer_count--;
- }
+ dma_channel.state = TRANSFER;
+ }
+ else
+ // (7.0265) set the bus grant wait flag
+ dma_channel.control |= DMA_CTRL_WAIT;
+ break;
- // if there are no more bytes remaining, terminate the transfer
- if (dma_channel.transfer_count == 0)
- {
- LOG_DMA(channel, "dma: transfer %s device ended, channel = %d, control 0x%08x, real address 0x%08x, virtual address 0x%08x, count 0x%08x\n",
- (dma_channel.control & DMA_CTRL_WRITE) ? "to" : "from",
- channel, dma_channel.control, dma_channel.real_address, dma_channel.virtual_address, dma_channel.transfer_count);
+ case TRANSFER:
+ // if there are no more bytes remaining, terminate the transfer
+ if (dma_channel.transfer_count == 0)
+ {
+ LOG_DMA(dma_channel.channel, "dma: transfer %s device ended, channel = %d, control 0x%08x, real address 0x%08x, virtual address 0x%08x, count 0x%08x\n",
+ (dma_channel.control & DMA_CTRL_WRITE) ? "to" : "from",
+ dma_channel.channel, dma_channel.control, dma_channel.real_address, dma_channel.virtual_address, dma_channel.transfer_count);
- if (channel == IOGA_DMA_FLOPPY)
- {
- LOG_DMA(channel, "dma: asserting fdc terminal count line\n");
+ if (dma_channel.channel == IOGA_DMA_FLOPPY)
+ {
+ LOG_DMA(dma_channel.channel, "dma: asserting fdc terminal count line\n");
- m_fdc_tc_func(ASSERT_LINE);
- m_fdc_tc_func(CLEAR_LINE);
- }
+ m_fdc_tc_func(ASSERT_LINE);
+ m_fdc_tc_func(CLEAR_LINE);
+ }
+
+ // set transfer count zero flag
+ dma_channel.control |= DMA_CTRL_TCZERO;
+ dma_channel.state = COMPLETE;
+ }
+#if IOGA_DMA_DIAG_HACK
+ else
+#define TAG ((dma_channel.control & DMA_CTRL_TAG) >> 3)
+
+ // hacks for forced dma bus error diagnostic tests
+ if ((dma_channel.control & 0xfe000000 && dma_channel.control & 0xe00) || ((dma_channel.control & DMA_CTRL_WMASK) == 0x41000000))
+ if (dma_channel.real_address & 0xff000000 || dma_channel.real_address == 0)
+ {
+ LOG_DMA(dma_channel.channel, "dma: forced bus error hack, control 0x%08x\n", dma_channel.control);
+
+ // (7.0267) trigger an interrupt
+ m_hwicr[dma_channel.channel + 1] |= IOGA_INTERRUPT_PENDING;
+
+ // (7.0268) set bus error bit
+ dma_channel.control |= DMA_CTRL_BERR;
+
+ // 7.0269, 7.0276, 7.0281, 7.0289: set error address from virtual or real dma address
+ // HACK: don't set error address for 7.0276 special case
+ if (!(dma_channel.control == 0x65400600 && dma_channel.real_address != 0))
+ m_error_address = dma_channel.control & DMA_CTRL_VIRTUAL ? dma_channel.virtual_address : dma_channel.real_address;
+
+ // compute bus error cycle type from control register
+ u8 cycle_type = 0x30;
+ switch ((dma_channel.control >> 24) & 0x8c)
+ {
+ case 0x00: cycle_type |= 2; break;
+ case 0x04: cycle_type |= 1; break;
+ case 0x08: cycle_type |= 3; break;
+ case 0x80: cycle_type |= 4; break;
+ case 0x84: cycle_type |= 8; break;
+ }
+
+ switch (dma_channel.control & ~DMA_CTRL_BERR)
+ {
+ case 0x61000800: // VIRTUAL | WRITE | TAG(3)
+ // (7.0266) trigger an nmi
+ m_nmi_pending = true;
+
+ // (7.0270) set error cycle type 0x52f0: SNAPOK | BERR | BG(IOD) | TAG(0c0) | CT(30)
+ m_error_businfo = BINFO_SNAPOK | BINFO_BERR | BINFO_BG_IOD | 0xf0;
+ break;
+
+ case 0x65000600: // VIRTUAL | WRITE | X | TAG(4)
+ if (dma_channel.real_address != 0)
+ {
+ // (7.0275) control register expect 0x64400800
+ dma_channel.control &= ~0x600;
+ dma_channel.control |= 0x800;
+
+ // (7.0277) set error cycle type 0x5331: SNAPOK | BERR | BG(IOD) | TAG(100) | CT(31)
+ m_error_businfo = BINFO_SNAPOK | BINFO_BERR | BINFO_BG_IOD | TAG | cycle_type;
+ }
+ else
+ {
+ // (7.0287) set error cycle type 0x62f0: SNAPOK | MMBE | BG(IOD) | TAG(0c0) | CT(30)
+ m_error_businfo = BINFO_SNAPOK | BINFO_MMBE | BINFO_BG_IOD | TAG | 0x30;
+ }
+ break;
+
+ default:
+ m_error_businfo = BINFO_SNAPOK | BINFO_BERR | BINFO_BG_IOD | TAG | cycle_type;
+ break;
+ }
+
+ dma_channel.state = COMPLETE;
+ }
+#endif
+ break;
- dma_channel.control |= DMA_CTRL_TCZERO;
- dma_channel.dma_active = false;
+ case COMPLETE:
+ // clear busy flag
+ dma_channel.control &= ~DMA_CTRL_BUSY;
+ dma_channel.state = IDLE;
+ break;
+ }
}
}
void interpro_ioga_device::drq(int state, int channel)
{
- // a device is requesting a dma data transfer (read or write)
- m_dma_channel[channel].drq_state = state;
+ // TODO: implement virtual addressing when DMA_CTRL_VIRTUAL is set
+
+ struct dma &dma_channel = m_dma_channel[channel];
if (state)
{
LOG_DMA(channel, "dma: drq for channel %d asserted\n", channel);
- m_dma_timer->adjust(attotime::zero, channel);
+ if (dma_channel.state == TRANSFER && dma_channel.transfer_count)
+ {
+ // transfer from the memory to device or device to memory
+ if (dma_channel.control & DMA_CTRL_WRITE)
+ dma_channel.device_w(m_memory_space->read_byte(dma_channel.real_address));
+ else
+ m_memory_space->write_byte(dma_channel.real_address, dma_channel.device_r());
+
+ // increment addresses and decrement count
+ dma_channel.real_address++;
+ dma_channel.virtual_address++;
+ dma_channel.transfer_count--;
+ }
}
else
LOG_DMA(channel, "dma: drq for channel %d deasserted\n", channel);
}
-/*
-0x94: error address reg: expect 0x7f200000 after bus error (from dma virtual address)
-0x98: error cycle type: expect 0x52f0 (after failed dma?)
- 0x5331 - forced berr with nmi/interrupts disabled?
- 0xc2f0
- 0x62f0
-*/
-// TODO: 7.0266 - forced BERR not working
u32 interpro_ioga_device::dma_r(address_space &space, offs_t offset, u32 mem_mask, int channel)
{
+ struct dma &dma_channel = m_dma_channel[channel];
+
switch (offset)
{
case 0:
- return m_dma_channel[channel].real_address;
+ return dma_channel.real_address;
case 1:
- return m_dma_channel[channel].virtual_address;
+ return dma_channel.virtual_address;
case 2:
- return m_dma_channel[channel].transfer_count;
+ return dma_channel.transfer_count;
case 3:
- return m_dma_channel[channel].control;
- }
+ return dma_channel.control;
- logerror("dma_r: unknown channel %d\n", channel);
- return 0;
+ default:
+ logerror("dma_r: unknown dma register %d\n", offset);
+ return 0;
+ }
}
void interpro_ioga_device::dma_w(address_space &space, offs_t offset, u32 data, u32 mem_mask, int channel)
{
+ struct dma &dma_channel = m_dma_channel[channel];
+
switch (offset)
{
case 0:
LOG_DMA(channel, "dma: channel %d real address = 0x%08x (%s)\n", channel, data, machine().describe_context());
- m_dma_channel[channel].real_address = data;
+ dma_channel.real_address = data;
break;
case 1:
LOG_DMA(channel, "dma: channel %d virtual address = 0x%08x (%s)\n", channel, data, machine().describe_context());
- m_dma_channel[channel].virtual_address = data & ~0x3;
+ dma_channel.virtual_address = data & ~0x3;
break;
case 2:
LOG_DMA(channel, "dma: channel %d transfer count = 0x%08x (%s)\n", channel, data, machine().describe_context());
- m_dma_channel[channel].transfer_count = data;
+ dma_channel.transfer_count = data;
break;
case 3:
LOG_DMA(channel, "dma: channel %d control = 0x%08x (%s)\n", channel, data, machine().describe_context());
- m_dma_channel[channel].control = data & DMA_CTRL_WMASK;
- // start a forced dma transfer if necessary
- if ((data & DMA_CTRL_FORCED) == DMA_CTRL_FORCED)
- m_dma_timer->adjust(attotime::from_hz(clock()), channel);
+ // (7.0272) if bus error flag is set, clear existing bus error (otherwise retain existing state)
+ if (data & DMA_CTRL_BERR)
+ dma_channel.control = data & DMA_CTRL_WMASK;
+ else
+ dma_channel.control = (data & DMA_CTRL_WMASK) | (dma_channel.control & DMA_CTRL_BERR);
+
+ dma_channel.state = COMMAND;
break;
}
}
@@ -806,3 +900,41 @@ WRITE16_MEMBER(interpro_ioga_device::arbctl_w)
m_arbctl = data;
}
+
+WRITE32_MEMBER(interpro_ioga_device::eth_remap_w)
+{
+ LOG_ETH("eth: remap = 0x%08x (%s)\n", data, machine().describe_context());
+
+ m_eth_remap = data & ~0xf;
+}
+
+WRITE32_MEMBER(interpro_ioga_device::eth_map_page_w)
+{
+ LOG_ETH("eth: remap page = 0x%08x (%s)\n", data, machine().describe_context());
+
+ m_eth_map_page = data & ~0xf;
+}
+
+WRITE32_MEMBER(interpro_ioga_device::eth_control_w)
+{
+ LOG_ETH("eth: control = 0x%08x (%s)\n", data, machine().describe_context());
+
+ /* (7.0202) eth ctrl register input test patterns and expected outputs are:
+
+ 7809 -> 4000
+
+ 3809 -> 0800
+ 3409 -> 0400
+ 3209 -> 0200
+ 3109 -> 0100
+
+ 3089 -> 80
+ 3049 -> 40
+ 3019 -> 10
+ 300b -> 02
+ */
+ if (data & ETH_RESET)
+ m_eth_control = ETH_RESET;
+ else
+ m_eth_control = data & 0x0ff2;
+}
diff --git a/src/mame/machine/interpro_ioga.h b/src/mame/machine/interpro_ioga.h
index ee8af40f5a4..f852ed5b985 100644
--- a/src/mame/machine/interpro_ioga.h
+++ b/src/mame/machine/interpro_ioga.h
@@ -60,26 +60,6 @@
#define IOGA_DMA_FLOPPY 2
#define IOGA_DMA_SERIAL 3
-// dma control register
-
-// are these "commands"?
-#define IOGA_DMA_CTRL_RESET_L 0x61000000 // do not clear bus error bit
-#define IOGA_DMA_CTRL_RESET 0x60400000 // clear bus error bit
-
-// uncertain about these
-#define IOGA_DMA_CTRL_START 0x10000000
-#define IOGA_DMA_CTRL_ENABLE 0x20000000
-#define IOGA_DMA_CTRL_X 0x00800000 // another error bit?
-#define IOGA_DMA_CTRL_Y 0x01000000 // turned off if either of two above are found
-
-#define IOGA_DMA_CTRL_UNK1 0x60000000 // don't know yet
-#define IOGA_DMA_CTRL_UNK2 0x67000600 // forced berr with nmi and interrupts disabled
-#define IOGA_DMA_CTRL_UNK3 0xbf000600 // set by scsidiag before executing scsi "transfer information" command
-
-// read values
-// iogadiag expects 0x64400800 after forced berr with nmi/interrupts disabled
-
-
class interpro_ioga_device : public device_t
{
public:
@@ -117,6 +97,45 @@ public:
DECLARE_WRITE_LINE_MEMBER(drq_scsi) { drq(state, IOGA_DMA_SCSI); }
DECLARE_WRITE_LINE_MEMBER(drq_floppy) { drq(state, IOGA_DMA_FLOPPY); }
+ enum eth_remap_mask
+ {
+ ETH_REMAP_CHA_FLUSH = 0x00000008,
+ ETH_REMAP_CHA_BUF = 0x00000010,
+ ETH_REMAP_CHA_QUAD = 0x00000020,
+ ETH_REMAP_CHA_WTAG = 0x000001c0,
+ ETH_REMAP_CHA_RTAG = 0x00000e00,
+ ETH_REMAP_ADDR = 0xfffff000
+ };
+ DECLARE_READ32_MEMBER(eth_remap_r) { return m_eth_remap; }
+ DECLARE_WRITE32_MEMBER(eth_remap_w);
+
+ enum eth_remap_page_mask
+ {
+ ETH_REMAP_CHB_FLUSH = 0x00000008,
+ ETH_REMAP_CHB_BUF = 0x00000010,
+ ETH_REMAP_CHB_QUAD = 0x00000020,
+ ETH_REMAP_CHB_WTAG = 0x000001c0,
+ ETH_REMAP_CHB_RTAG = 0x00000e00,
+ ETH_MAP_PAGE = 0xfffff000
+ };
+ DECLARE_READ32_MEMBER(eth_map_page_r) { return m_eth_map_page; }
+ DECLARE_WRITE32_MEMBER(eth_map_page_w);
+
+ enum eth_control_mask
+ {
+ ETH_CA = 0x00000001,
+ ETH_MAPEN = 0x00000002,
+ ETH_REMAP_CHC_BUF = 0x00000010,
+ ETH_REMAP_CHC_QUAD = 0x00000020,
+ ETH_REMAP_CHC_WTAG = 0x000001c0,
+ ETH_REMAP_CHC_RTAG = 0x00000e00,
+ ETH_BERR = 0x00001000,
+ ETH_MMBE = 0x00002000,
+ ETH_RESET = 0x00004000
+ };
+ DECLARE_READ32_MEMBER(eth_control_r) { return m_eth_control; }
+ DECLARE_WRITE32_MEMBER(eth_control_w);
+
DECLARE_READ32_MEMBER(timer_prescaler_r) { return m_prescaler; }
DECLARE_READ32_MEMBER(timer0_r) { return m_timer_reg[0]; }
DECLARE_READ32_MEMBER(timer1_r);
@@ -126,7 +145,7 @@ public:
ARBCTL_BGR_ETHC = 0x0001,
ARBCTL_BGR_SCSI = 0x0002,
ARBCTL_BGR_PLOT = 0x0004,
- ARBCTL_BGR_FDC = 0x0008,
+ ARBCTL_BGR_FDC = 0x0008,
ARBCTL_BGR_SER0 = 0x0010,
ARBCTL_BGR_SER1 = 0x0020,
ARBCTL_BGR_SER2 = 0x0040,
@@ -186,14 +205,19 @@ public:
enum dma_ctrl_mask
{
- DMA_CTRL_TCZERO = 0x00000001, // transfer count zero
- DMA_CTRL_BERR = 0x00400000, // bus error
- DMA_CTRL_BUSY = 0x02000000, // set until arbiter grants bus access
+ DMA_CTRL_TCZERO = 0x00000001, // transfer count zero
+ DMA_CTRL_TAG = 0x00000e00, // bus tag
+ DMA_CTRL_BERR = 0x00400000, // bus error
+ DMA_CTRL_ERR = 0x00800000, // checked for in scsi isr
+
+ DMA_CTRL_BUSY = 0x01000000, // cleared when command complete (maybe bus grant required?)
+ DMA_CTRL_WAIT = 0x02000000, // waiting for bus grant
+ DMA_CTRL_X = 0x04000000, // set during fdc dma?
- DMA_CTRL_WRITE = 0x40000000, // indicates memory to device transfer
- DMA_CTRL_FORCED = 0x60000000,
+ DMA_CTRL_VIRTUAL = 0x20000000, // use virtual addressing
+ DMA_CTRL_WRITE = 0x40000000, // memory to device transfer
- DMA_CTRL_WMASK = 0xfd000e00 // writable fields
+ DMA_CTRL_WMASK = 0xfd000e00 // writable fields
};
DECLARE_READ32_MEMBER(dma_plotter_r) { return dma_r(space, offset, mem_mask, IOGA_DMA_PLOTTER); }
DECLARE_WRITE32_MEMBER(dma_plotter_w) { dma_w(space, offset, data, mem_mask, IOGA_DMA_PLOTTER); }
@@ -244,8 +268,8 @@ private:
static const device_timer_id IOGA_TIMER_1 = 1;
static const device_timer_id IOGA_TIMER_2 = 2;
static const device_timer_id IOGA_TIMER_3 = 3;
- static const device_timer_id IOGA_TIMER_DMA = 4;
- static const device_timer_id IOGA_CLOCK = 5;
+
+ static const device_timer_id IOGA_CLOCK = 4;
void set_nmi_line(int state);
void set_irq_line(int irq, int state);
@@ -253,13 +277,21 @@ private:
void write_timer(int timer, u32 value, device_timer_id id);
void interrupt_clock();
- void dma_clock(int channel);
+ void dma_clock();
void drq(int state, int channel);
devcb_write_line m_out_nmi_func;
devcb_write_line m_out_irq_func;
address_space *m_memory_space;
+ enum dma_states
+ {
+ IDLE,
+ WAIT,
+ COMMAND,
+ TRANSFER,
+ COMPLETE
+ };
// dma channels
struct dma
{
@@ -268,12 +300,13 @@ private:
u32 transfer_count;
u32 control;
- bool dma_active;
- int drq_state;
+ dma_states state;
devcb_read8 device_r;
devcb_write8 device_w;
const u16 arb_mask;
+ const int channel;
+ const char *name;
} m_dma_channel[IOGA_DMA_CHANNELS];
u32 m_dma_plotter_eosl;
@@ -302,9 +335,6 @@ private:
u32 m_timer3_count;
emu_timer *m_timer[4];
- // dma state
- emu_timer *m_dma_timer;
-
u32 dma_r(address_space &space, offs_t offset, u32 mem_mask, int channel);
void dma_w(address_space &space, offs_t offset, u32 data, u32 mem_mask, int channel);
@@ -322,6 +352,10 @@ private:
bool nmi(int state);
bool irq(int state);
+
+ u32 m_eth_remap;
+ u32 m_eth_map_page;
+ u32 m_eth_control;
};
// device type definition
diff --git a/src/mame/machine/interpro_sga.cpp b/src/mame/machine/interpro_sga.cpp
index b33dfcce297..3d6b0731acc 100644
--- a/src/mame/machine/interpro_sga.cpp
+++ b/src/mame/machine/interpro_sga.cpp
@@ -105,13 +105,13 @@ WRITE32_MEMBER(interpro_sga_device::ddtc1_w)
// error cycle - bit 0x10 indicates source address error (dspad1)
// now expecting 0x5463?
if ((m_dspad1 & 0xfffff000) == 0x40000000)
- out_berr_func(space, 0x5433, m_dspad1);
+ out_berr_func(space, 0x5433, m_dspad1); // BINFO_SNAPOK | BINFO_BERR | BINFO_BG_ICAMMU | 0x30 | CT(3)
else
- out_berr_func(space, 0x5423, m_ddpad1);
+ out_berr_func(space, 0x5423, m_ddpad1); // BINFO_SNAPOK | BINFO_BERR | BINFO_BG_ICAMMU | 0x20 | CT(3)
// 0x5423 = BERR|SNAPOK | BG(ICAMMU)? | CT(23)
// 0x5433 = BERR|SNAPOK | BG(ICAMMU)? | CT(33)
- // 0x5463 = BERR|SNAPOK | BG(ICAMMU)? | TAG(1) | CT(23)
+ // 0x5463 = BERR|SNAPOK | BG(ICAMMU)? | TAG(40=1) | CT(23)
}
#endif
}