diff options
Diffstat (limited to 'src')
34 files changed, 636 insertions, 146 deletions
diff --git a/src/devices/cpu/z180/hd647180x.cpp b/src/devices/cpu/z180/hd647180x.cpp new file mode 100644 index 00000000000..15bf3961d23 --- /dev/null +++ b/src/devices/cpu/z180/hd647180x.cpp @@ -0,0 +1,330 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/********************************************************************** + + Hitachi HD647180X MCU (Micro Controller Unit) + + This expandable 8-bit microcontroller architecturally extends the + on-chip I/O capabilities of the Hitachi HD64180/Zilog Z80180 CPU + with parallel ports and more. It also contains a 16-kilobyte + internal programmable ROM (which can be disabled by strapping) and + 512 bytes of internal RAM, the latter being software-remappable to + the end of any 64K block. The MP pins configure the MCU for either + single-chip mode, one of two expanded modes or PROM writing/ + verification. (Hitachi also had the HD643180X, which uses a 16 KB + mask ROM instead of the PROM, and HD641180X, which offers neither + ROM nor PROM and therefore must be used in ROMless mode.) + + TODO: the current emulation is incomplete, implementing mostly + the internal memory and parallel ports. Timer 2 (which is very + similar to the additional timer of the HD6301) is not emulated at + all. Programs trying to execute from internal RAM will also fail, + though this likely capability is merely theoretical so far. + +**********************************************************************/ + +#include "emu.h" +#include "hd647180x.h" + +#define VERBOSE 0 +#include "logmacro.h" + +// device type definition +DEFINE_DEVICE_TYPE(HD647180X, hd647180x_device, "hd647180x", "Hitachi HD647180X MCU") + +hd647180x_device::hd647180x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z180_device(mconfig, HD647180X, tag, owner, clock, true, address_map_constructor(FUNC(hd647180x_device::prom_map), this)) + , m_port_input_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_port_output_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_data_config("data", ENDIANNESS_LITTLE, 8, 9, 0, address_map_constructor(FUNC(hd647180x_device::ram_map), this)) +{ + // arbitrary initial states + m_ccsr = 0; + std::fill(std::begin(m_odr), std::end(m_odr), 0); +} + +void hd647180x_device::prom_map(address_map &map) +{ + map(0x00000, 0x03fff).rom().region(DEVICE_SELF, 0); // 16 KB internal PROM (not used in mode 1) +} + +void hd647180x_device::ram_map(address_map &map) +{ + map(0x000, 0x1ff).ram(); // 512 bytes remappable internal RAM (available in all modes) +} + +device_memory_interface::space_config_vector hd647180x_device::memory_space_config() const +{ + auto spaces = z180_device::memory_space_config(); + spaces.emplace_back(AS_DATA, &m_data_config); + return spaces; +} + +uint8_t hd647180x_device::z180_read_memory(offs_t addr) +{ + if ((addr & 0xffe00) == (offs_t(m_rmcr) << 12 | 0x0fe00)) + return m_data->read_byte(addr & 0x1ff); + else + return z180_device::z180_read_memory(addr); +} + +void hd647180x_device::z180_write_memory(offs_t addr, uint8_t data) +{ + if ((addr & 0xffe00) == (offs_t(m_rmcr) << 12 | 0x0fe00)) + m_data->write_byte(addr & 0x1ff, data); + else + z180_device::z180_write_memory(addr, data); +} + +uint8_t hd647180x_device::z180_internal_port_read(uint8_t port) +{ + uint8_t data = 0xff; + + switch (port) + { + case 0x40: + data = m_t2frc.b.l; + LOG("HD647180X T2FRCL rd $%02x\n", data); + break; + + case 0x41: + data = m_t2frc.b.h; + LOG("HD647180X T2FRCH rd $%02x\n", data); + break; + + case 0x42: + data = m_t2ocr[0].b.l; + LOG("HD647180X T2OCR1L rd $%02x\n", data); + break; + + case 0x43: + data = m_t2ocr[0].b.h; + LOG("HD647180X T2OCR1H rd $%02x\n", data); + break; + + case 0x44: + data = m_t2ocr[1].b.l; + LOG("HD647180X T2OCR2L rd $%02x\n", data); + break; + + case 0x45: + data = m_t2ocr[1].b.h; + LOG("HD647180X T2OCR2H rd $%02x\n", data); + break; + + case 0x46: + data = m_t2icr.b.l; + LOG("HD647180X T2ICRL rd $%02x\n", data); + break; + + case 0x47: + data = m_t2icr.b.h; + LOG("HD647180X T2ICRH rd $%02x\n", data); + break; + + case 0x48: + data = m_t2csr[0]; + LOG("HD647180X T2CSR1 rd $%02x\n", data); + break; + + case 0x49: + data = m_t2csr[1] | 0x10; + LOG("HD647180X T2CSR2 rd $%02x\n", data); + break; + + case 0x50: + data = m_ccsr | 0x40; + LOG("HD647180X CCSR rd $%02x\n", data); + break; + + case 0x51: + data = m_rmcr | 0x0f; + LOG("HD647180X RMCR rd $%02x\n", data); + break; + + case 0x53: + data = m_dera; + LOG("HD647180X DERA rd $%02x\n", data); + break; + + case 0x60: + case 0x61: + case 0x62: + case 0x65: + data = m_odr[port - 0x60] & m_ddr[port - 0x60]; + if (m_ddr[port - 0x60] != 0xff) + data |= m_port_input_cb[port - 0x60](0, ~m_ddr[port - 0x60]) & ~m_ddr[port - 0x60]; + LOG("HD647180X IDR%c rd $%02x\n", port - 0x60 + 'A', data); + break; + + case 0x63: // ODRD is write-only + data = m_ddr[3]; + if (m_ddr[3] != 0xff) + data |= m_port_input_cb[3](0, ~m_ddr[3]) & ~m_ddr[3]; + LOG("HD647180X IDRD rd $%02x\n", data); + break; + + case 0x64: // lower half of ODRE is write-only + data = (m_odr[port - 0x60] | 0x0f) & m_ddr[3]; + if (m_ddr[3] != 0xff) + data |= m_port_input_cb[3](0, ~m_ddr[3]) & ~m_ddr[3]; + LOG("HD647180X IDRE rd $%02x\n", data); + break; + + case 0x66: // Port G is read-only and only has 6 bits + data = m_port_input_cb[6](0, 0x3f) | 0xc0; + LOG("HD647180X IDRG rd $%02x\n", data); + break; + + default: + data = z180_device::z180_internal_port_read(port); + break; + } + + return data; +} + +void hd647180x_device::z180_internal_port_write(uint8_t port, uint8_t data) +{ + switch (port) + { + case 0x40: + LOG("HD647180X T2FRCL wr $%02x\n", data); + m_t2frc.b.l = data; + break; + + case 0x41: + LOG("HD647180X T2FRCH wr $%02x\n", data); + m_t2frc.b.h = data; + break; + + case 0x42: + LOG("HD647180X T2OCR1L wr $%02x\n", data); + m_t2ocr[0].b.l = data; + break; + + case 0x43: + LOG("HD647180X T2OCR1H wr $%02x\n", data); + m_t2ocr[0].b.h = data; + break; + + case 0x44: + LOG("HD647180X T2OCR2L wr $%02x\n", data); + m_t2ocr[1].b.l = data; + break; + + case 0x45: + LOG("HD647180X T2OCR2H wr $%02x\n", data); + m_t2ocr[1].b.h = data; + break; + + case 0x48: + LOG("HD647180X T2CSR1 wr $%02x\n", data); + m_t2csr[0] = data; + break; + + case 0x49: + LOG("HD647180X T2CSR2 wr $%02x\n", data); + m_t2csr[1] = data & 0xef; + break; + + case 0x50: + LOG("HD647180X CCSR wr $%02x\n", data); + m_ccsr = (m_ccsr & 0x80) | (data & 0x3f); + break; + + case 0x51: + LOG("HD647180X RMCR wr $%02x\n", data); + m_rmcr = data & 0xf0; + break; + + case 0x53: + LOG("HD647180X DERA wr $%02x\n", data); + m_dera = data; + break; + + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + LOG("HD647180X ODR%c wr $%02x\n", port - 0x60 + 'A', data); + if ((data & m_ddr[port - 0x60]) != (m_odr[port - 0x60] & m_ddr[port - 0x60])) + m_port_output_cb[port - 0x60](0, data | ~m_ddr[port - 0x60], m_ddr[port - 0x60]); + m_odr[port - 0x60] = data; + break; + + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + LOG("HD647180X DDR%c wr $%02x\n", port - 0x70 + 'A', data); + if ((data & ~m_ddr[port - 0x70]) != 0) + m_port_output_cb[port - 0x70](0, m_odr[port - 0x70] | ~data, data); + m_ddr[port - 0x70] = data; + break; + + default: + z180_device::z180_internal_port_write(port, data); + break; + } +} + +void hd647180x_device::device_resolve_objects() +{ + for (auto &cb : m_port_input_cb) + cb.resolve_safe(0xff); + for (auto &cb : m_port_output_cb) + cb.resolve_safe(); +} + +void hd647180x_device::device_start() +{ + z180_device::device_start(); + + m_data = &space(AS_DATA); + + state_add(HD647180X_T2FRC, "T2FRC", m_t2frc.w); + state_add(HD647180X_T2OCR1, "T2OCR1", m_t2ocr[0].w); + state_add(HD647180X_T2OCR2, "T2OCR2", m_t2ocr[1].w); + state_add(HD647180X_T2ICR, "T2ICR", m_t2icr.w); + state_add(HD647180X_T2CSR1, "T2CSR1", m_t2csr[0]); + state_add(HD647180X_T2CSR2, "T2CSR2", m_t2csr[1]).mask(0xef); + state_add(HD647180X_CCSR, "CCSR", m_ccsr).mask(0xbf); + state_add(HD647180X_RMCR, "RMCR", m_rmcr).mask(0xf0); + state_add(HD647180X_DERA, "DERA", m_dera); + for (int i = 0; i < 6; i++) + { + state_add(HD647180X_ODRA + i, string_format("ODR%c", i + 'A').c_str(), m_odr[i]); + state_add(HD647180X_DDRA + i, string_format("DDR%c", i + 'A').c_str(), m_ddr[i]); + } + + save_item(NAME(m_t2frc.w)); + save_item(NAME(m_t2ocr[0].w)); + save_item(NAME(m_t2ocr[1].w)); + save_item(NAME(m_t2icr.w)); + save_item(NAME(m_t2csr)); + save_item(NAME(m_ccsr)); + save_item(NAME(m_rmcr)); + save_item(NAME(m_dera)); + save_item(NAME(m_odr)); + save_item(NAME(m_ddr)); +} + +void hd647180x_device::device_reset() +{ + z180_device::device_reset(); + + m_t2frc.w = 0; + m_t2ocr[0].w = m_t2ocr[1].w = 0xffff; + m_t2icr.w = 0; + m_t2csr[0] = 0x00; + m_t2csr[1] = 0x00; + m_ccsr = (m_ccsr & 0x80) | 0x2c; + m_rmcr = 0; + m_dera = 0; + std::fill(std::begin(m_ddr), std::end(m_ddr), 0); +} diff --git a/src/devices/cpu/z180/hd647180x.h b/src/devices/cpu/z180/hd647180x.h new file mode 100644 index 00000000000..0221a614794 --- /dev/null +++ b/src/devices/cpu/z180/hd647180x.h @@ -0,0 +1,87 @@ +// license:BSD-3-Clause +// copyright-holders:AJR + +#ifndef MAME_CPU_Z180_HD647180X_H +#define MAME_CPU_Z180_HD647180X_H + +#pragma once + +#include "z180.h" + +class hd647180x_device : public z180_device +{ +public: + enum + { + HD647180X_T2FRC = Z180_IOLINES + 1, + HD647180X_T2OCR1, HD647180X_T2OCR2, + HD647180X_T2ICR, + HD647180X_T2CSR1, HD647180X_T2CSR2, + HD647180X_CCSR, + HD647180X_RMCR, + HD647180X_DERA, + HD647180X_ODRA, HD647180X_ODRB, HD647180X_ODRC, HD647180X_ODRD, HD647180X_ODRE, HD647180X_ODRF, + HD647180X_DDRA, HD647180X_DDRB, HD647180X_DDRC, HD647180X_DDRD, HD647180X_DDRE, HD647180X_DDRF + }; + + // construction/destruction + hd647180x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + auto in_pa_callback() { return m_port_input_cb[0].bind(); } + auto in_pb_callback() { return m_port_input_cb[1].bind(); } + auto in_pc_callback() { return m_port_input_cb[2].bind(); } + auto in_pd_callback() { return m_port_input_cb[3].bind(); } + auto in_pe_callback() { return m_port_input_cb[4].bind(); } + auto in_pf_callback() { return m_port_input_cb[5].bind(); } + auto in_pg_callback() { return m_port_input_cb[6].bind(); } + auto out_pa_callback() { return m_port_output_cb[0].bind(); } + auto out_pb_callback() { return m_port_output_cb[1].bind(); } + auto out_pc_callback() { return m_port_output_cb[2].bind(); } + auto out_pd_callback() { return m_port_output_cb[3].bind(); } + auto out_pe_callback() { return m_port_output_cb[4].bind(); } + auto out_pf_callback() { return m_port_output_cb[5].bind(); } + +protected: + // device-specific overrides + virtual void device_resolve_objects() override; + virtual void device_start() override; + virtual void device_reset() override; + + // device_memory_interface overrides + virtual space_config_vector memory_space_config() const override; + + // z180_device overrides + virtual uint8_t z180_read_memory(offs_t addr) override; + virtual void z180_write_memory(offs_t addr, uint8_t data) override; + virtual uint8_t z180_internal_port_read(uint8_t port) override; + virtual void z180_internal_port_write(uint8_t port, uint8_t data) override; + +private: + // internal memory maps + void prom_map(address_map &map); + void ram_map(address_map &map); + + // port callbacks + devcb_read8 m_port_input_cb[7]; + devcb_write8 m_port_output_cb[6]; + + // internal RAM space + address_space_config m_data_config; + address_space *m_data; + + // internal registers + PAIR16 m_t2frc; + PAIR16 m_t2ocr[2]; + PAIR16 m_t2icr; + uint8_t m_t2csr[2]; + uint8_t m_ccsr; + uint8_t m_rmcr; + uint8_t m_dera; + uint8_t m_odr[6]; + uint8_t m_ddr[6]; +}; + +// device type declaration +DECLARE_DEVICE_TYPE(HD647180X, hd647180x_device) + +#endif // MAME_CPU_Z180_HD647180X_H diff --git a/src/devices/cpu/z180/z180.cpp b/src/devices/cpu/z180/z180.cpp index aede5f08a28..510075b041d 100644 --- a/src/devices/cpu/z180/z180.cpp +++ b/src/devices/cpu/z180/z180.cpp @@ -78,15 +78,19 @@ Hitachi HD647180 series: /* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */ /****************************************************************************/ -DEFINE_DEVICE_TYPE(Z180, z180_device, "z180", "Zilog Z180") +DEFINE_DEVICE_TYPE(Z80180, z80180_device, "z80180", "Zilog Z80180") // equivalent to Hitachi HD64180 +DEFINE_DEVICE_TYPE(HD64180RP, hd64180rp_device, "hd64180rp", "Hitachi HD64180RP") // DIP version identical to Zilog Z80180xxPSC +DEFINE_DEVICE_TYPE(Z8S180, z8s180_device, "z8s180", "Zilog Z8S180") +DEFINE_DEVICE_TYPE(Z80182, z80182_device, "z80182", "Zilog Z80182") -z180_device::z180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : cpu_device(mconfig, Z180, tag, owner, clock) +z180_device::z180_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool extended_io, address_map_constructor internal_map) + : cpu_device(mconfig, type, tag, owner, clock) , z80_daisy_chain_interface(mconfig, *this) - , m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, internal_map) , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0) - , m_decrypted_opcodes_config("program", ENDIANNESS_LITTLE, 8, 20, 0) + , m_decrypted_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, 20, 0) + , m_extended_io(extended_io) { // some arbitrary initial values m_asci_cntla[0] = m_asci_cntla[1] = 0; @@ -110,6 +114,28 @@ std::unique_ptr<util::disasm_interface> z180_device::create_disassembler() return std::make_unique<z180_disassembler>(); } +z80180_device::z80180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z180_device(mconfig, Z80180, tag, owner, clock, false, address_map_constructor()) +{ +} + +hd64180rp_device::hd64180rp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z180_device(mconfig, HD64180RP, tag, owner, clock, false, address_map_constructor()) +{ + // 64-pin DIP versions omit A19 + set_data_width(19); +} + +z8s180_device::z8s180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z180_device(mconfig, Z8S180, tag, owner, clock, false, address_map_constructor()) +{ +} + +z80182_device::z80182_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z180_device(mconfig, Z80182, tag, owner, clock, false, address_map_constructor()) +{ +} + #define CF 0x01 #define NF 0x02 #define PF 0x04 @@ -388,8 +414,6 @@ bool z180_device::get_tend1() /* 3f I/O control register */ #define Z180_IOCR_IOSTP 0x20 -#define Z180_IOCR_MASK 0xe0 - /*************************************************************************** CPU PREFIXES @@ -427,6 +451,12 @@ static std::unique_ptr<uint8_t[]> SZHVC_sub; #include "z180op.hxx" +void z180_device::set_data_width(int bits) +{ + m_program_config.m_data_width = bits; + m_decrypted_opcodes_config.m_data_width = bits; +} + device_memory_interface::space_config_vector z180_device::memory_space_config() const { if(has_configured_map(AS_OPCODES)) @@ -442,16 +472,29 @@ device_memory_interface::space_config_vector z180_device::memory_space_config() }; } +uint8_t z180_device::z180_read_memory(offs_t addr) +{ + return m_program->read_byte(addr); +} + +void z180_device::z180_write_memory(offs_t addr, uint8_t data) +{ + m_program->write_byte(addr, data); +} + uint8_t z180_device::z180_readcontrol(offs_t port) { - /* normal external readport */ - uint8_t data = m_iospace->read_byte(port); + // normal external readport (ignore the data) + (void)m_iospace->read_byte(port); + + // read the internal register + return z180_internal_port_read(port & (m_extended_io ? 0x7f : 0x3f)); +} - /* remap internal I/O registers */ - if((port & (m_iocr & 0xc0)) == (m_iocr & 0xc0)) - port = port - (m_iocr & 0xc0); +uint8_t z180_device::z180_internal_port_read(uint8_t port) +{ + uint8_t data = 0xff; - /* but ignore the data and read the internal register */ switch (port) { case 0x00: @@ -512,7 +555,7 @@ uint8_t z180_device::z180_readcontrol(offs_t port) case 0x0b: data = m_csio_trdr; - logerror("Z180 TRDR rd $%02x\n", data); + LOG("Z180 TRDR rd $%02x\n", data); break; case 0x0c: @@ -862,7 +905,7 @@ uint8_t z180_device::z180_readcontrol(offs_t port) break; case 0x3f: - data = m_iocr | ~Z180_IOCR_MASK; + data = m_iocr | ~(m_extended_io ? 0xa0 : 0xe0); LOG("Z180 IOCR rd $%02x ($%02x)\n", data, m_iocr); break; } @@ -872,14 +915,15 @@ uint8_t z180_device::z180_readcontrol(offs_t port) void z180_device::z180_writecontrol(offs_t port, uint8_t data) { - /* normal external write port */ + // normal external write port m_iospace->write_byte(port, data); - /* remap internal I/O registers */ - if((port & (m_iocr & 0xc0)) == (m_iocr & 0xc0)) - port = port - (m_iocr & 0xc0); + // store the data in the internal register + z180_internal_port_write(port & (m_extended_io ? 0x7f : 0x3f), data); +} - /* store the data in the internal register */ +void z180_device::z180_internal_port_write(uint8_t port, uint8_t data) +{ switch (port) { case 0x00: @@ -1223,8 +1267,8 @@ void z180_device::z180_writecontrol(offs_t port, uint8_t data) break; case 0x3f: - LOG("Z180 IOCR wr $%02x ($%02x)\n", data, data & Z180_IOCR_MASK); - m_iocr = data & Z180_IOCR_MASK; + LOG("Z180 IOCR wr $%02x ($%02x)\n", data, data & (m_extended_io ? 0xa0 : 0xe0)); + m_iocr = data & (m_extended_io ? 0xa0 : 0xe0); break; } } @@ -1259,24 +1303,24 @@ int z180_device::z180_dma0(int max_cycles) switch( m_dmode & (Z180_DMODE_SM | Z180_DMODE_DM) ) { case 0x00: /* memory SAR0+1 to memory DAR0+1 */ - m_program->write_byte(dar0++, m_program->read_byte(sar0++)); + z180_write_memory(dar0++, z180_read_memory(sar0++)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x04: /* memory SAR0-1 to memory DAR0+1 */ - m_program->write_byte(dar0++, m_program->read_byte(sar0--)); + z180_write_memory(dar0++, z180_read_memory(sar0--)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x08: /* memory SAR0 fixed to memory DAR0+1 */ - m_program->write_byte(dar0++, m_program->read_byte(sar0)); + z180_write_memory(dar0++, z180_read_memory(sar0)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x0c: /* I/O SAR0 fixed to memory DAR0+1 */ if (m_iol & Z180_DREQ0) { - m_program->write_byte(dar0++, IN(sar0)); + z180_write_memory(dar0++, IN(sar0)); cycles += memory_wait_states(); bcr0--; /* edge sensitive DREQ0 ? */ @@ -1288,24 +1332,24 @@ int z180_device::z180_dma0(int max_cycles) } break; case 0x10: /* memory SAR0+1 to memory DAR0-1 */ - m_program->write_byte(dar0--, m_program->read_byte(sar0++)); + z180_write_memory(dar0--, z180_read_memory(sar0++)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x14: /* memory SAR0-1 to memory DAR0-1 */ - m_program->write_byte(dar0--, m_program->read_byte(sar0--)); + z180_write_memory(dar0--, z180_read_memory(sar0--)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x18: /* memory SAR0 fixed to memory DAR0-1 */ - m_program->write_byte(dar0--, m_program->read_byte(sar0)); + z180_write_memory(dar0--, z180_read_memory(sar0)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x1c: /* I/O SAR0 fixed to memory DAR0-1 */ if (m_iol & Z180_DREQ0) { - m_program->write_byte(dar0--, IN(sar0)); + z180_write_memory(dar0--, IN(sar0)); cycles += memory_wait_states(); bcr0--; /* edge sensitive DREQ0 ? */ @@ -1317,12 +1361,12 @@ int z180_device::z180_dma0(int max_cycles) } break; case 0x20: /* memory SAR0+1 to memory DAR0 fixed */ - m_program->write_byte(dar0, m_program->read_byte(sar0++)); + z180_write_memory(dar0, z180_read_memory(sar0++)); cycles += memory_wait_states() * 2; bcr0--; break; case 0x24: /* memory SAR0-1 to memory DAR0 fixed */ - m_program->write_byte(dar0, m_program->read_byte(sar0--)); + z180_write_memory(dar0, z180_read_memory(sar0--)); cycles += memory_wait_states() * 2; bcr0--; break; @@ -1333,7 +1377,7 @@ int z180_device::z180_dma0(int max_cycles) case 0x30: /* memory SAR0+1 to I/O DAR0 fixed */ if (m_iol & Z180_DREQ0) { - OUT(dar0, m_program->read_byte(sar0++)); + OUT(dar0, z180_read_memory(sar0++)); cycles += memory_wait_states(); bcr0--; /* edge sensitive DREQ0 ? */ @@ -1347,7 +1391,7 @@ int z180_device::z180_dma0(int max_cycles) case 0x34: /* memory SAR0-1 to I/O DAR0 fixed */ if (m_iol & Z180_DREQ0) { - OUT(dar0, m_program->read_byte(sar0--)); + OUT(dar0, z180_read_memory(sar0--)); cycles += memory_wait_states(); bcr0--; /* edge sensitive DREQ0 ? */ @@ -1417,16 +1461,16 @@ int z180_device::z180_dma1() switch (m_dcntl & (Z180_DCNTL_DIM1 | Z180_DCNTL_DIM0)) { case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */ - m_iospace->write_byte(iar1, m_program->read_byte(mar1++)); + m_iospace->write_byte(iar1, z180_read_memory(mar1++)); break; case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */ - m_iospace->write_byte(iar1, m_program->read_byte(mar1--)); + m_iospace->write_byte(iar1, z180_read_memory(mar1--)); break; case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */ - m_program->write_byte(mar1++, m_iospace->read_byte(iar1)); + z180_write_memory(mar1++, m_iospace->read_byte(iar1)); break; case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */ - m_program->write_byte(mar1--, m_iospace->read_byte(iar1)); + z180_write_memory(mar1--, m_iospace->read_byte(iar1)); break; } @@ -1742,7 +1786,7 @@ void z180_device::device_start() state_add(Z180_BBR, "BBR", m_mmu_bbr).callimport(); state_add(Z180_CBAR, "CBAR", m_mmu_cbar).callimport(); state_add(Z180_OMCR, "OMCR", m_omcr).mask(Z180_OMCR_MASK); - state_add(Z180_IOCR, "IOCR", m_iocr).mask(Z180_IOCR_MASK); + state_add(Z180_IOCR, "IOCR", m_iocr).mask(m_extended_io ? 0xa0 : 0xe0); } save_item(NAME(m_AF.w.l)); diff --git a/src/devices/cpu/z180/z180.h b/src/devices/cpu/z180/z180.h index d5a1bc6ef94..25b93f8a07e 100644 --- a/src/devices/cpu/z180/z180.h +++ b/src/devices/cpu/z180/z180.h @@ -105,13 +105,13 @@ enum { class z180_device : public cpu_device, public z80_daisy_chain_interface { public: - // construction/destruction - z180_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock); - bool get_tend0(); bool get_tend1(); protected: + // construction/destruction + z180_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool extended_io, address_map_constructor internal_map); + // device-level overrides virtual void device_start() override; virtual void device_reset() override; @@ -138,15 +138,24 @@ protected: // device_disasm_interface overrides virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; -private: - int memory_wait_states() const { return (m_dcntl & 0xc0) >> 6; } - int io_wait_states() const { return (m_dcntl & 0x30) == 0 ? 0 : ((m_dcntl & 0x30) >> 4) + 1; } - bool is_internal_io_address(uint16_t port) const { return ((port ^ m_iocr) & 0xffc0) == 0; } + virtual uint8_t z180_read_memory(offs_t addr); + virtual void z180_write_memory(offs_t addr, uint8_t data); + virtual uint8_t z180_internal_port_read(uint8_t port); + virtual void z180_internal_port_write(uint8_t port, uint8_t data); address_space_config m_program_config; address_space_config m_io_config; address_space_config m_decrypted_opcodes_config; + void set_data_width(int bits); + +private: + int memory_wait_states() const { return (m_dcntl & 0xc0) >> 6; } + int io_wait_states() const { return (m_dcntl & 0x30) == 0 ? 0 : ((m_dcntl & 0x30) >> 4) + 1; } + bool is_internal_io_address(uint16_t port) const { return ((port ^ m_iocr) & (m_extended_io ? 0xff80 : 0xffc0)) == 0; } + + const bool m_extended_io; + PAIR m_PREPC,m_PC,m_SP,m_AF,m_BC,m_DE,m_HL,m_IX,m_IY; PAIR m_AF2,m_BC2,m_DE2,m_HL2; uint8_t m_R,m_R2,m_IFF1,m_IFF2,m_HALT,m_IM,m_I; @@ -1787,7 +1796,37 @@ private: void xycb_ff(); }; +class z80180_device : public z180_device +{ +public: + // construction/destruction + z80180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class hd64180rp_device : public z180_device +{ +public: + // construction/destruction + hd64180rp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class z8s180_device : public z180_device +{ +public: + // construction/destruction + z8s180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class z80182_device : public z180_device +{ +public: + // construction/destruction + z80182_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; -DECLARE_DEVICE_TYPE(Z180, z180_device) +DECLARE_DEVICE_TYPE(Z80180, z80180_device) +DECLARE_DEVICE_TYPE(HD64180RP, hd64180rp_device) +DECLARE_DEVICE_TYPE(Z8S180, z8s180_device) +DECLARE_DEVICE_TYPE(Z80182, z80182_device) #endif // MAME_CPU_Z180_Z180_H diff --git a/src/devices/cpu/z180/z180dasm.cpp b/src/devices/cpu/z180/z180dasm.cpp index 521ec1bfe41..f8d332eca15 100644 --- a/src/devices/cpu/z180/z180dasm.cpp +++ b/src/devices/cpu/z180/z180dasm.cpp @@ -450,7 +450,7 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat break; case 'O': /* Offset relative to PC */ offset = (int8_t) params.r8(pos++); - util::stream_format(stream, "$%05X", pc + offset + 2); + util::stream_format(stream, "$%04X", (pc + offset + 2) & 0xffff); break; case 'P': /* Port number */ ea = params.r8(pos++); @@ -463,7 +463,7 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat case 'W': /* Memory address word */ ea = params.r16(pos); pos += 2; - util::stream_format(stream, "$%05X", ea); + util::stream_format(stream, "$%04X", ea); break; case 'X': offset = (int8_t) params.r8(pos++); diff --git a/src/devices/cpu/z180/z180ops.h b/src/devices/cpu/z180/z180ops.h index 2bc68e3b5e3..7b4d0f159f2 100644 --- a/src/devices/cpu/z180/z180ops.h +++ b/src/devices/cpu/z180/z180ops.h @@ -81,13 +81,13 @@ void z180_device::z180_mmu() inline u8 z180_device::RM(offs_t addr) { m_extra_cycles += memory_wait_states(); - return m_program->read_byte(MMU_REMAP_ADDR(addr)); + return z180_read_memory(MMU_REMAP_ADDR(addr)); } /*************************************************************** * Write a byte to given memory location ***************************************************************/ -#define WM(addr,value) m_extra_cycles += memory_wait_states(); m_program->write_byte(MMU_REMAP_ADDR(addr),value) +#define WM(addr,value) m_extra_cycles += memory_wait_states(); z180_write_memory(MMU_REMAP_ADDR(addr),value) /*************************************************************** * Read a word from given memory location diff --git a/src/mame/drivers/20pacgal.cpp b/src/mame/drivers/20pacgal.cpp index 38883d77efb..ad912569f9e 100644 --- a/src/mame/drivers/20pacgal.cpp +++ b/src/mame/drivers/20pacgal.cpp @@ -400,7 +400,7 @@ WRITE_LINE_MEMBER(_20pacgal_state::vblank_irq) void _20pacgal_state::_20pacgal(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, MAIN_CPU_CLOCK); + Z8S180(config, m_maincpu, MAIN_CPU_CLOCK); m_maincpu->set_addrmap(AS_PROGRAM, &_20pacgal_state::_20pacgal_map); m_maincpu->set_addrmap(AS_IO, &_20pacgal_state::_20pacgal_io_map); diff --git a/src/mame/drivers/asuka.cpp b/src/mame/drivers/asuka.cpp index 1556a996993..25140be246a 100644 --- a/src/mame/drivers/asuka.cpp +++ b/src/mame/drivers/asuka.cpp @@ -933,7 +933,7 @@ void asuka_state::cadash(machine_config &config) Z80(config, m_audiocpu, XTAL(8'000'000)/2); /* verified on pcb */ m_audiocpu->set_addrmap(AS_PROGRAM, &asuka_state::cadash_z80_map); - z180_device &subcpu(Z180(config, "subcpu", XTAL(8'000'000))); /* 8MHz HD64180RP8 Z180 */ + z180_device &subcpu(HD64180RP(config, "subcpu", XTAL(8'000'000))); /* 8MHz HD64180RP8 Z180 */ subcpu.set_addrmap(AS_PROGRAM, &asuka_state::cadash_sub_map); subcpu.set_addrmap(AS_IO, &asuka_state::cadash_sub_io); diff --git a/src/mame/drivers/atronic.cpp b/src/mame/drivers/atronic.cpp index 35ad71cb8cf..3b888be09a5 100644 --- a/src/mame/drivers/atronic.cpp +++ b/src/mame/drivers/atronic.cpp @@ -466,7 +466,7 @@ void atronic_state::ramdac_map(address_map &map) void atronic_state::atronic(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, 6000000); + Z80180(config, m_maincpu, 6000000); m_maincpu->set_addrmap(AS_PROGRAM, &atronic_state::atronic_map); m_maincpu->set_addrmap(AS_IO, &atronic_state::atronic_portmap); m_maincpu->set_vblank_int("screen", FUNC(atronic_state::irq0_line_hold)); diff --git a/src/mame/drivers/cabaret.cpp b/src/mame/drivers/cabaret.cpp index bf7333cf798..d0769e2af22 100644 --- a/src/mame/drivers/cabaret.cpp +++ b/src/mame/drivers/cabaret.cpp @@ -369,7 +369,7 @@ INTERRUPT_GEN_MEMBER(cabaret_state::cabaret_interrupt) void cabaret_state::cabaret(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 2); + Z80180(config, m_maincpu, XTAL(12'000'000) / 2); m_maincpu->set_addrmap(AS_PROGRAM, &cabaret_state::cabaret_map); m_maincpu->set_addrmap(AS_IO, &cabaret_state::cabaret_portmap); m_maincpu->set_vblank_int("screen", FUNC(cabaret_state::cabaret_interrupt)); diff --git a/src/mame/drivers/chsuper.cpp b/src/mame/drivers/chsuper.cpp index e8e4407e7c1..adc63e6589b 100644 --- a/src/mame/drivers/chsuper.cpp +++ b/src/mame/drivers/chsuper.cpp @@ -367,7 +367,7 @@ void chsuper_state::ramdac_map(address_map &map) void chsuper_state::chsuper(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 4); /* HD64180RP8, 8 MHz? */ + HD64180RP(config, m_maincpu, XTAL(12'000'000) / 4); /* HD64180RP8, 8 MHz? */ m_maincpu->set_addrmap(AS_PROGRAM, &chsuper_state::chsuper_prg_map); m_maincpu->set_addrmap(AS_IO, &chsuper_state::chsuper_portmap); m_maincpu->set_vblank_int("screen", FUNC(chsuper_state::irq0_line_hold)); diff --git a/src/mame/drivers/daryde.cpp b/src/mame/drivers/daryde.cpp index 911c518d1c3..977ab59b00a 100644 --- a/src/mame/drivers/daryde.cpp +++ b/src/mame/drivers/daryde.cpp @@ -44,7 +44,7 @@ INPUT_PORTS_END void daryde_state::pandart(machine_config &config) { - cpu_device &maincpu(Z180(config, "maincpu", XTAL(18'432'000))); + cpu_device &maincpu(Z80180(config, "maincpu", XTAL(18'432'000))); maincpu.set_addrmap(AS_PROGRAM, &daryde_state::mem_map); maincpu.set_addrmap(AS_IO, &daryde_state::io_map); diff --git a/src/mame/drivers/ecoinf2.cpp b/src/mame/drivers/ecoinf2.cpp index c1d6844ba91..462c370f26f 100644 --- a/src/mame/drivers/ecoinf2.cpp +++ b/src/mame/drivers/ecoinf2.cpp @@ -500,7 +500,7 @@ INPUT_PORTS_END void ecoinf2_state::ecoinf2_oxo(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, 4000000); // some of these hit invalid opcodes with a plain z80, some don't? + Z80180(config, m_maincpu, 4000000); // some of these hit invalid opcodes with a plain z80, some don't? m_maincpu->set_addrmap(AS_PROGRAM, &ecoinf2_state::oxo_memmap); m_maincpu->set_addrmap(AS_IO, &ecoinf2_state::oxo_portmap); diff --git a/src/mame/drivers/ecoinf3.cpp b/src/mame/drivers/ecoinf3.cpp index 08aa113dd7c..579eb3f96ac 100644 --- a/src/mame/drivers/ecoinf3.cpp +++ b/src/mame/drivers/ecoinf3.cpp @@ -663,7 +663,7 @@ INPUT_PORTS_END void ecoinf3_state::ecoinf3_pyramid(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, 8000000); // certainly not a plain z80 at least, invalid opcodes for that + Z80180(config, m_maincpu, 8000000); // certainly not a plain z80 at least, invalid opcodes for that m_maincpu->set_addrmap(AS_PROGRAM, &ecoinf3_state::pyramid_memmap); m_maincpu->set_addrmap(AS_IO, &ecoinf3_state::pyramid_portmap); diff --git a/src/mame/drivers/hawk.cpp b/src/mame/drivers/hawk.cpp index 444231c6015..b3f3e9a72ee 100644 --- a/src/mame/drivers/hawk.cpp +++ b/src/mame/drivers/hawk.cpp @@ -102,7 +102,7 @@ void hawk_state::hawk_palette(palette_device &palette) const void hawk_state::hawk(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, 12.288_MHz_XTAL / 2); /* HD64B180R0F */ + Z80180(config, m_maincpu, 12.288_MHz_XTAL / 2); /* HD64B180R0F */ m_maincpu->set_addrmap(AS_PROGRAM, &hawk_state::hawk_mem); m_maincpu->set_addrmap(AS_IO, &hawk_state::hawk_io); diff --git a/src/mame/drivers/igs009.cpp b/src/mame/drivers/igs009.cpp index 88a622f316c..f4255f8c685 100644 --- a/src/mame/drivers/igs009.cpp +++ b/src/mame/drivers/igs009.cpp @@ -832,7 +832,7 @@ WRITE_LINE_MEMBER(igs009_state::vblank_irq) void igs009_state::jingbell(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */ + HD64180RP(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */ m_maincpu->set_addrmap(AS_PROGRAM, &igs009_state::jingbell_map); m_maincpu->set_addrmap(AS_IO, &igs009_state::jingbell_portmap); diff --git a/src/mame/drivers/igs017.cpp b/src/mame/drivers/igs017.cpp index 78df9207e81..1621855f4c2 100644 --- a/src/mame/drivers/igs017.cpp +++ b/src/mame/drivers/igs017.cpp @@ -3497,7 +3497,7 @@ MACHINE_RESET_MEMBER(igs017_state,iqblocka) void igs017_state::iqblocka(machine_config &config) { - Z180(config, m_maincpu, XTAL(16'000'000) / 2); + Z80180(config, m_maincpu, XTAL(16'000'000) / 2); m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::iqblocka_map); m_maincpu->set_addrmap(AS_IO, &igs017_state::iqblocka_io); TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1); @@ -3836,7 +3836,7 @@ void igs017_state::mgdha(machine_config &config) void igs017_state::tjsb(machine_config &config) { - Z180(config, m_maincpu, XTAL(16'000'000) / 2); + Z80180(config, m_maincpu, XTAL(16'000'000) / 2); m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::tjsb_map); m_maincpu->set_addrmap(AS_IO, &igs017_state::tjsb_io); TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1); @@ -3874,7 +3874,7 @@ void igs017_state::tjsb(machine_config &config) void igs017_state::spkrform(machine_config &config) { - Z180(config, m_maincpu, XTAL(16'000'000) / 2); + Z80180(config, m_maincpu, XTAL(16'000'000) / 2); m_maincpu->set_addrmap(AS_PROGRAM, &igs017_state::spkrform_map); m_maincpu->set_addrmap(AS_IO, &igs017_state::spkrform_io); TIMER(config, "scantimer").configure_scanline(FUNC(igs017_state::iqblocka_interrupt), "screen", 0, 1); diff --git a/src/mame/drivers/kron.cpp b/src/mame/drivers/kron.cpp index 85de8f4dc61..ba5f4ea4253 100644 --- a/src/mame/drivers/kron.cpp +++ b/src/mame/drivers/kron.cpp @@ -303,7 +303,7 @@ WRITE_LINE_MEMBER(kron180_state::keyb_interrupt) void kron180_state::kron180(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'288'000)); + HD64180RP(config, m_maincpu, XTAL(12'288'000)); m_maincpu->set_addrmap(AS_PROGRAM, &kron180_state::kron180_mem); m_maincpu->set_addrmap(AS_IO, &kron180_state::kron180_iomap); diff --git a/src/mame/drivers/luckgrln.cpp b/src/mame/drivers/luckgrln.cpp index 35f096e6dc3..32e13943bf1 100644 --- a/src/mame/drivers/luckgrln.cpp +++ b/src/mame/drivers/luckgrln.cpp @@ -76,7 +76,7 @@ #include "emu.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "machine/msm6242.h" #include "video/mc6845.h" #include "emupal.h" @@ -116,7 +116,7 @@ private: required_shared_ptr_array<uint8_t, 4> m_reel_scroll; required_shared_ptr_array<uint8_t, 3> m_luck_vram; - required_device<cpu_device> m_maincpu; + required_device<hd647180x_device> m_maincpu; required_device<gfxdecode_device> m_gfxdecode; required_device<palette_device> m_palette; output_finder<12> m_lamps; @@ -299,7 +299,6 @@ uint32_t luckgrln_state::screen_update(screen_device &screen, bitmap_rgb32 &bitm void luckgrln_state::mainmap(address_map &map) { - map(0x00000, 0x03fff).rom(); map(0x10000, 0x1ffff).rom().region("rom_data", 0x10000); map(0x20000, 0x2ffff).rom().region("rom_data", 0x00000); @@ -343,6 +342,8 @@ void luckgrln_state::_7smash_map(address_map &map) WRITE8_MEMBER(luckgrln_state::output_w) { + data &= 0xc7; + /* correct? */ if (data==0x84) m_nmi_enable = 0; @@ -446,8 +447,7 @@ WRITE8_MEMBER(luckgrln_state::counters_w) void luckgrln_state::common_portmap(address_map &map) { map.global_mask(0xff); - map(0x0000, 0x003f).ram(); // Z180 internal regs - map(0x0060, 0x0060).w(FUNC(luckgrln_state::output_w)); + map(0x0000, 0x007f).noprw(); // Z180 internal regs map(0x00a0, 0x00a0).w(FUNC(luckgrln_state::palette_offset_low_w)); map(0x00a1, 0x00a1).w(FUNC(luckgrln_state::palette_offset_high_w)); @@ -511,7 +511,6 @@ READ8_MEMBER(luckgrln_state::test_r) void luckgrln_state::_7smash_io(address_map &map) { common_portmap(map); - map(0x66, 0x66).r(FUNC(luckgrln_state::test_r)); } static INPUT_PORTS_START( luckgrln ) @@ -864,10 +863,11 @@ INTERRUPT_GEN_MEMBER(luckgrln_state::irq) void luckgrln_state::luckgrln(machine_config &config) { - Z180(config, m_maincpu, 8000000); + HD647180X(config, m_maincpu, 8000000); m_maincpu->set_addrmap(AS_PROGRAM, &luckgrln_state::mainmap); m_maincpu->set_addrmap(AS_IO, &luckgrln_state::luckgrln_io); m_maincpu->set_vblank_int("screen", FUNC(luckgrln_state::irq)); + m_maincpu->out_pa_callback().set(FUNC(luckgrln_state::output_w)); hd6845s_device &crtc(HD6845S(config, "crtc", 6000000/4)); /* HD6845SP; unknown clock, hand tuned to get ~60 fps */ crtc.set_screen("screen"); @@ -894,6 +894,7 @@ void luckgrln_state::_7smash(machine_config &config) luckgrln(config); m_maincpu->set_addrmap(AS_PROGRAM, &luckgrln_state::_7smash_map); m_maincpu->set_addrmap(AS_IO, &luckgrln_state::_7smash_io); + m_maincpu->in_pg_callback().set(FUNC(luckgrln_state::test_r)); config.device_remove("rtc"); } diff --git a/src/mame/drivers/luckybal.cpp b/src/mame/drivers/luckybal.cpp index d4a0e10cd1d..b1c7000df50 100644 --- a/src/mame/drivers/luckybal.cpp +++ b/src/mame/drivers/luckybal.cpp @@ -568,7 +568,7 @@ INPUT_PORTS_END void luckybal_state::luckybal(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, CPU_CLOCK / 2); + Z80180(config, m_maincpu, CPU_CLOCK / 2); m_maincpu->set_addrmap(AS_PROGRAM, &luckybal_state::main_map); m_maincpu->set_addrmap(AS_IO, &luckybal_state::main_io); diff --git a/src/mame/drivers/mastboy.cpp b/src/mame/drivers/mastboy.cpp index 70faffe7880..65839271081 100644 --- a/src/mame/drivers/mastboy.cpp +++ b/src/mame/drivers/mastboy.cpp @@ -439,7 +439,7 @@ */ #include "emu.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "sound/saa1099.h" #include "sound/msm5205.h" #include "machine/74259.h" @@ -622,7 +622,6 @@ WRITE_LINE_MEMBER(mastboy_state::vblank_irq) void mastboy_state::mastboy_map(address_map &map) { - map(0x0000, 0x3fff).rom(); // Internal ROM map(0x4000, 0x7fff).rom(); // External ROM map(0x8000, 0x8fff).ram().share("workram");// work ram @@ -642,8 +641,6 @@ void mastboy_state::mastboy_map(address_map &map) map(0xff828, 0xff829).w("saa", FUNC(saa1099_device::write)); map(0xff830, 0xff830).w(FUNC(mastboy_state::msm5205_data_w)); map(0xff838, 0xff83f).w(m_outlatch, FUNC(ls259_device::write_d0)); - - map(0xffc00, 0xfffff).ram(); // Internal RAM } // TODO : banked map is mirrored? @@ -808,7 +805,7 @@ void mastboy_state::machine_reset() void mastboy_state::mastboy(machine_config &config) { - Z180(config, m_maincpu, 12000000/2); /* HD647180X0CP6-1M1R */ + HD647180X(config, m_maincpu, 12000000/2); /* HD647180X0CP6-1M1R */ m_maincpu->set_addrmap(AS_PROGRAM, &mastboy_state::mastboy_map); m_maincpu->set_addrmap(AS_IO, &mastboy_state::mastboy_io_map); diff --git a/src/mame/drivers/mosaic.cpp b/src/mame/drivers/mosaic.cpp index 0ed4b63ed5a..a32d4bf7c5b 100644 --- a/src/mame/drivers/mosaic.cpp +++ b/src/mame/drivers/mosaic.cpp @@ -22,7 +22,7 @@ | YM2203C 9 0 | +--------------------------------------+ - CPU: Z180 (surface scratched) + CPU: Z180 (surface scratched 64-pin DIP) PIC16C5x (surface scratched, exact model unknown) Sound: YM2203C OSC: 14.31818MHz, 12.288MHz @@ -287,7 +287,7 @@ void mosaic_state::machine_reset() void mosaic_state::mosaic(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'288'000)/2); /* 6.144MHz - Verified */ + HD64180RP(config, m_maincpu, XTAL(12'288'000)/2); /* 6.144MHz - Verified */ m_maincpu->set_addrmap(AS_PROGRAM, &mosaic_state::mosaic_map); m_maincpu->set_addrmap(AS_IO, &mosaic_state::mosaic_io_map); m_maincpu->set_vblank_int("screen", FUNC(mosaic_state::irq0_line_hold)); diff --git a/src/mame/drivers/p112.cpp b/src/mame/drivers/p112.cpp index 7b4c6cb4ad3..a36a6c3b9e4 100644 --- a/src/mame/drivers/p112.cpp +++ b/src/mame/drivers/p112.cpp @@ -93,7 +93,7 @@ uint32_t p112_state::screen_update_p112(screen_device &screen, bitmap_ind16 &bit void p112_state::p112(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(16'000'000)); + Z80182(config, m_maincpu, XTAL(16'000'000)); m_maincpu->set_addrmap(AS_PROGRAM, &p112_state::p112_mem); m_maincpu->set_addrmap(AS_IO, &p112_state::p112_io); diff --git a/src/mame/drivers/pda600.cpp b/src/mame/drivers/pda600.cpp index 72e1ae8338e..c6bf7d29a71 100644 --- a/src/mame/drivers/pda600.cpp +++ b/src/mame/drivers/pda600.cpp @@ -207,7 +207,7 @@ GFXDECODE_END void pda600_state::pda600(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(14'318'181)); + Z8S180(config, m_maincpu, XTAL(14'318'181)); m_maincpu->set_addrmap(AS_PROGRAM, &pda600_state::pda600_mem); m_maincpu->set_addrmap(AS_IO, &pda600_state::pda600_io); diff --git a/src/mame/drivers/pinkiri8.cpp b/src/mame/drivers/pinkiri8.cpp index d5ad19d1baa..37d8a429b5b 100644 --- a/src/mame/drivers/pinkiri8.cpp +++ b/src/mame/drivers/pinkiri8.cpp @@ -39,7 +39,7 @@ Dumped by Chackn ***************************************************************************/ #include "emu.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "sound/okim6295.h" #include "emupal.h" #include "screen.h" @@ -83,8 +83,8 @@ public: m_palette(*this, "palette") { } - void init_ronjan(); void pinkiri8(machine_config &config); + void ronjan(machine_config &config); protected: DECLARE_WRITE8_MEMBER(output_regs_w); @@ -104,6 +104,7 @@ protected: void pinkiri8_io(address_map &map); void pinkiri8_map(address_map &map); + void ronjan_io(address_map &map); private: required_shared_ptr<uint8_t> m_janshi_back_vram; @@ -122,7 +123,7 @@ private: uint8_t m_prot_char[5]; uint8_t m_prot_index; - required_device<cpu_device> m_maincpu; + required_device<hd647180x_device> m_maincpu; required_device<janshi_vdp_device> m_vdp; required_device<gfxdecode_device> m_gfxdecode; required_device<palette_device> m_palette; @@ -480,7 +481,7 @@ void pinkiri8_state::pinkiri8_io(address_map &map) { map.global_mask(0xff); map(0x00, 0x3f).ram(); //Z180 internal I/O - map(0x60, 0x60).w(FUNC(pinkiri8_state::output_regs_w)); + map(0x60, 0x60).nopw(); map(0x80, 0x83).w(FUNC(pinkiri8_state::pinkiri8_vram_w)); map(0xa0, 0xa0).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write)); //correct? @@ -511,7 +512,13 @@ void pinkiri8_state::pinkiri8_io(address_map &map) map(0xf3, 0xf3).nopw(); map(0xf7, 0xf7).nopw(); +} +void pinkiri8_state::ronjan_io(address_map &map) +{ + pinkiri8_io(map); + map(0x90, 0x90).rw(FUNC(pinkiri8_state::ronjan_prot_r), FUNC(pinkiri8_state::ronjan_prot_w)); + map(0x9f, 0x9f).r(FUNC(pinkiri8_state::ronjan_patched_prot_r)); } static INPUT_PORTS_START( base_inputs ) @@ -1108,10 +1115,11 @@ GFXDECODE_END void pinkiri8_state::pinkiri8(machine_config &config) { - Z180(config, m_maincpu, XTAL(32'000'000)/2); + HD647180X(config, m_maincpu, XTAL(32'000'000)/2); m_maincpu->set_addrmap(AS_PROGRAM, &pinkiri8_state::pinkiri8_map); m_maincpu->set_addrmap(AS_IO, &pinkiri8_state::pinkiri8_io); m_maincpu->set_vblank_int("screen", FUNC(pinkiri8_state::nmi_line_assert)); + m_maincpu->out_pa_callback().set(FUNC(pinkiri8_state::output_regs_w)); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); screen.set_refresh_hz(60); @@ -1132,6 +1140,14 @@ void pinkiri8_state::pinkiri8(machine_config &config) OKIM6295(config, "oki", 1056000, okim6295_device::PIN7_HIGH).add_route(ALL_OUTPUTS, "mono", 0.5); // clock frequency & pin 7 not verified } +void pinkiri8_state::ronjan(machine_config &config) +{ + pinkiri8(config); + + m_maincpu->set_addrmap(AS_IO, &pinkiri8_state::ronjan_io); + m_maincpu->in_pg_callback().set(FUNC(pinkiri8_state::ronjan_prot_status_r)); +} + /*************************************************************************** Game driver(s) @@ -1242,14 +1258,7 @@ READ8_MEMBER(pinkiri8_state::ronjan_patched_prot_r) return 0; //value is read then discarded } -void pinkiri8_state::init_ronjan() -{ - m_maincpu->space(AS_IO).install_readwrite_handler(0x90, 0x90, read8_delegate(FUNC(pinkiri8_state::ronjan_prot_r), this), write8_delegate(FUNC(pinkiri8_state::ronjan_prot_w), this)); - m_maincpu->space(AS_IO).install_read_handler(0x66, 0x66, read8_delegate(FUNC(pinkiri8_state::ronjan_prot_status_r), this)); - m_maincpu->space(AS_IO).install_read_handler(0x9f, 0x9f, read8_delegate(FUNC(pinkiri8_state::ronjan_patched_prot_r), this)); -} - -GAME( 1992, janshi, 0, pinkiri8, janshi, pinkiri8_state, empty_init, ROT0, "Eagle", "Janshi", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) -GAME( 1991, ronjan, ronjans, pinkiri8, ronjan, pinkiri8_state, init_ronjan, ROT0, "Wing Co., Ltd", "Ron Jan", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) -GAME( 1994, ronjans, 0, pinkiri8, ronjan, pinkiri8_state, init_ronjan, ROT0, "Wing Co., Ltd", "Ron Jan Super", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) // 'SUPER' flashes in the middle of the screen -GAME( 1994, pinkiri8, 0, pinkiri8, pinkiri8, pinkiri8_state, empty_init, ROT0, "Alta", "Pinkiri 8", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) +GAME( 1992, janshi, 0, pinkiri8, janshi, pinkiri8_state, empty_init, ROT0, "Eagle", "Janshi", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) +GAME( 1991, ronjan, ronjans, ronjan, ronjan, pinkiri8_state, empty_init, ROT0, "Wing Co., Ltd", "Ron Jan", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) +GAME( 1994, ronjans, 0, ronjan, ronjan, pinkiri8_state, empty_init, ROT0, "Wing Co., Ltd", "Ron Jan Super", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) // 'SUPER' flashes in the middle of the screen +GAME( 1994, pinkiri8, 0, pinkiri8, pinkiri8, pinkiri8_state, empty_init, ROT0, "Alta", "Pinkiri 8", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING ) diff --git a/src/mame/drivers/sfcbox.cpp b/src/mame/drivers/sfcbox.cpp index a02d68f2e0d..72a9201a838 100644 --- a/src/mame/drivers/sfcbox.cpp +++ b/src/mame/drivers/sfcbox.cpp @@ -469,7 +469,7 @@ void sfcbox_state::sfcbox(machine_config &config) config.m_perfect_cpu_quantum = subtag("maincpu"); /* sfcbox hardware */ - Z180(config, m_bios, XTAL(12'000'000) / 2); /* HD64180RF6X */ + Z80180(config, m_bios, XTAL(12'000'000) / 2); /* HD64180RF6X */ m_bios->set_addrmap(AS_PROGRAM, &sfcbox_state::sfcbox_map); m_bios->set_addrmap(AS_IO, &sfcbox_state::sfcbox_io); diff --git a/src/mame/drivers/spoker.cpp b/src/mame/drivers/spoker.cpp index f36d23a3a62..3c6e0cad3fe 100644 --- a/src/mame/drivers/spoker.cpp +++ b/src/mame/drivers/spoker.cpp @@ -612,7 +612,7 @@ void spoker_state::machine_reset() void spoker_state::spoker(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */ + HD64180RP(config, m_maincpu, XTAL(12'000'000) / 2); /* HD64180RP8, 8 MHz? */ m_maincpu->set_addrmap(AS_PROGRAM, &spoker_state::spoker_map); m_maincpu->set_addrmap(AS_IO, &spoker_state::spoker_portmap); m_maincpu->set_vblank_int("screen", FUNC(spoker_state::nmi_line_assert)); diff --git a/src/mame/drivers/subsino.cpp b/src/mame/drivers/subsino.cpp index 49d526e75bf..747feeeafbf 100644 --- a/src/mame/drivers/subsino.cpp +++ b/src/mame/drivers/subsino.cpp @@ -223,7 +223,7 @@ To Do: ***************************************************************************/ #include "emu.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "machine/i8255.h" #include "machine/nvram.h" #include "machine/subsino.h" @@ -2690,7 +2690,7 @@ GFXDECODE_END void subsino_state::victor21(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ + HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::victor21_map); m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap); @@ -2739,7 +2739,7 @@ void subsino_state::victor5(machine_config &config) void subsino_state::crsbingo(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */ + HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::crsbingo_map); m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap); @@ -2770,7 +2770,7 @@ void subsino_state::crsbingo(machine_config &config) void subsino_state::srider(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ + HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::srider_map); m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap); @@ -2821,7 +2821,7 @@ void subsino_state::sharkpy(machine_config &config) void subsino_state::tisub(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */ + HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown CPU and clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::tisub_map); m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap); @@ -2861,7 +2861,7 @@ void subsino_state::tisub(machine_config &config) void subsino_state::stbsub(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ + HD647180X(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino_state::stbsub_map); m_maincpu->set_addrmap(AS_IO, &subsino_state::subsino_iomap); diff --git a/src/mame/drivers/subsino2.cpp b/src/mame/drivers/subsino2.cpp index c36e97d4276..6ff569c08bf 100644 --- a/src/mame/drivers/subsino2.cpp +++ b/src/mame/drivers/subsino2.cpp @@ -2928,7 +2928,7 @@ void subsino2_state::humlan(machine_config &config) void subsino2_state::mtrain(machine_config &config) { - Z180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ + Z80180(config, m_maincpu, XTAL(12'000'000) / 8); /* Unknown clock */ m_maincpu->set_addrmap(AS_PROGRAM, &subsino2_state::mtrain_map); m_maincpu->set_addrmap(AS_IO, &subsino2_state::mtrain_io); diff --git a/src/mame/drivers/tim011.cpp b/src/mame/drivers/tim011.cpp index ebbaae170b2..026c8595417 100644 --- a/src/mame/drivers/tim011.cpp +++ b/src/mame/drivers/tim011.cpp @@ -135,7 +135,7 @@ static const floppy_format_type tim011_floppy_formats[] = { void tim011_state::tim011(machine_config &config) { /* basic machine hardware */ - Z180(config, m_maincpu, XTAL(12'288'000) / 2); // location U17 HD64180 + HD64180RP(config, m_maincpu, XTAL(12'288'000) / 2); // location U17 HD64180 m_maincpu->set_addrmap(AS_PROGRAM, &tim011_state::tim011_mem); m_maincpu->set_addrmap(AS_IO, &tim011_state::tim011_io); m_maincpu->set_vblank_int("screen", FUNC(tim011_state::irq0_line_hold)); diff --git a/src/mame/drivers/toaplan1.cpp b/src/mame/drivers/toaplan1.cpp index 06dcd3188ad..0db715b533a 100644 --- a/src/mame/drivers/toaplan1.cpp +++ b/src/mame/drivers/toaplan1.cpp @@ -610,7 +610,7 @@ Stephh's and AWJ's notes (based on the games M68000 and Z80 code and some tests) #include "includes/toaplipt.h" #include "cpu/z80/z80.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "machine/74259.h" #include "speaker.h" @@ -945,27 +945,23 @@ void toaplan1_demonwld_state::dsp_io_map(address_map &map) void toaplan1_state::vimana_hd647180_mem_map(address_map &map) { - map(0x00000, 0x03fff).rom(); /* Internal 16k byte ROM */ map(0x08000, 0x087ff).ram().share("sharedram"); /* 2048 bytes of shared ram w/maincpu */ - map(0x0fe00, 0x0ffff).ram(); /* Internal 512 byte RAM */ } void toaplan1_state::vimana_hd647180_io_map(address_map &map) { map.global_mask(0xff); - // lots of low level 647180 peripherals are not emulated yet, ddr regs, timer regs etc, see comments below - // also see http://bitsavers.trailing-edge.com/pdf/hitachi/_dataBooks/U94_HD647180X_8-Bit_Microcontroller_Hardware_Manual_Jan88.pdf particularly page 38 (pdf page 56) map(0x32, 0x32).nopw(); // DMA WAIT/Control register map(0x33, 0x33).nopw(); // IL (int vector low) register map(0x36, 0x36).nopw(); // refresh control register for RFSH pin // 53: disable reg for port A - map(0x60, 0x60).r(FUNC(toaplan1_state::vimana_dswb_invert_r)); // read/write port A; note these inputs seem to be inverted, unlike the DSWA ones. + map(0x60, 0x60).nopr(); // read/write port A // 61: read/write port B // 62: read/write port C // 63: read/write port D // 64: read/write port E // 65: read/write port F - map(0x66, 0x66).r(FUNC(toaplan1_state::vimana_tjump_invert_r)); // read/write port G, bits 7 and 6 ALWAYS read as 1 due to port G being just 6 bits; note these inputs seem to be inverted, unlike the DSWA ones. + map(0x66, 0x66).nopr(); // read port G // 70: ddr for port A map(0x71, 0x71).nopw(); // ddr for port B map(0x72, 0x72).nopw(); // ddr for port C @@ -1014,17 +1010,11 @@ u8 toaplan1_samesame_state::cmdavailable_r() else return 0x00; }; -void toaplan1_samesame_state::hd647180_mem_map(address_map &map) -{ - map(0x00000, 0x03fff).rom(); /* Internal 16k byte ROM */ - map(0x0fe00, 0x0ffff).ram(); /* Internal 512 byte RAM */ -} - void toaplan1_samesame_state::hd647180_io_map(address_map &map) { map.global_mask(0xff); - map(0x63, 0x63).r(FUNC(toaplan1_samesame_state::cmdavailable_r)); + map(0x63, 0x63).nopr(); map(0xa0, 0xa0).r(FUNC(toaplan1_samesame_state::soundlatch_r)); map(0xb0, 0xb0).w(FUNC(toaplan1_samesame_state::sound_done_w)); @@ -2113,9 +2103,10 @@ void toaplan1_samesame_state::samesame(machine_config &config) M68000(config, m_maincpu, XTAL(10'000'000)); m_maincpu->set_addrmap(AS_PROGRAM, &toaplan1_samesame_state::main_map); - Z180(config, m_audiocpu, XTAL(28'000'000) / 8); /* HD647180XOFS6 CPU */ - m_audiocpu->set_addrmap(AS_PROGRAM, &toaplan1_samesame_state::hd647180_mem_map); - m_audiocpu->set_addrmap(AS_IO, &toaplan1_samesame_state::hd647180_io_map); + hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 8)); /* HD647180XOFS6 CPU */ + // 16k byte ROM and 512 byte RAM are internal + audiocpu.set_addrmap(AS_IO, &toaplan1_samesame_state::hd647180_io_map); + audiocpu.in_pd_callback().set(FUNC(toaplan1_samesame_state::cmdavailable_r)); config.m_perfect_cpu_quantum = subtag("maincpu"); @@ -2209,9 +2200,11 @@ void toaplan1_state::vimana(machine_config &config) M68000(config, m_maincpu, XTAL(10'000'000)); /* verified on pcb */ m_maincpu->set_addrmap(AS_PROGRAM, &toaplan1_state::vimana_main_map); - Z180(config, m_audiocpu, XTAL(28'000'000) / 8); /* HD647180XOFS6 CPU */ - m_audiocpu->set_addrmap(AS_PROGRAM, &toaplan1_state::vimana_hd647180_mem_map); - m_audiocpu->set_addrmap(AS_IO, &toaplan1_state::vimana_hd647180_io_map); + hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, XTAL(28'000'000) / 8)); /* HD647180XOFS6 CPU */ + audiocpu.set_addrmap(AS_PROGRAM, &toaplan1_state::vimana_hd647180_mem_map); + audiocpu.set_addrmap(AS_IO, &toaplan1_state::vimana_hd647180_io_map); + audiocpu.in_pa_callback().set(FUNC(toaplan1_state::vimana_dswb_invert_r)); // note these inputs seem to be inverted, unlike the DSWA ones. + audiocpu.in_pg_callback().set(FUNC(toaplan1_state::vimana_tjump_invert_r)); // note these inputs seem to be inverted, unlike the DSWA ones. config.m_minimum_quantum = attotime::from_hz(600); diff --git a/src/mame/drivers/toaplan2.cpp b/src/mame/drivers/toaplan2.cpp index 892adeae76b..64783f2a609 100644 --- a/src/mame/drivers/toaplan2.cpp +++ b/src/mame/drivers/toaplan2.cpp @@ -392,7 +392,7 @@ To reset the NVRAM in Othello Derby, hold P1 Button 1 down while booting. #include "cpu/nec/v25.h" #include "cpu/z80/z80.h" -#include "cpu/z180/z180.h" +#include "cpu/z180/hd647180x.h" #include "machine/nvram.h" #include "sound/3812intf.h" #include "sound/ym2151.h" @@ -1453,17 +1453,12 @@ u8 toaplan2_state::tekipaki_cmdavailable_r() else return 0x00; }; -void toaplan2_state::hd647180_mem_map(address_map &map) -{ - map(0x00000, 0x03fff).rom(); /* Internal 16k byte ROM */ - map(0x0fe00, 0x0ffff).ram(); /* Internal 512 byte RAM */ -} - void toaplan2_state::hd647180_io_map(address_map &map) { map.global_mask(0xff); - map(0x60, 0x60).r(FUNC(toaplan2_state::tekipaki_cmdavailable_r)); + map(0x60, 0x60).nopr(); + map(0x70, 0x75).nopw(); // DDRs are written with the wrong upper addresses! map(0x84, 0x84).r(m_soundlatch, FUNC(generic_latch_8_device::read)); map(0x82, 0x82).rw("ymsnd", FUNC(ym3812_device::status_port_r), FUNC(ym3812_device::control_port_w)); @@ -1473,10 +1468,6 @@ void toaplan2_state::hd647180_io_map(address_map &map) void toaplan2_state::ghox_hd647180_mem_map(address_map &map) { - map(0x00000, 0x03fff).rom(); // Internal 16k byte ROM - map(0x0fe00, 0x0ffff).ram(); // Internal 512 byte RAM - map(0x3fe00, 0x3ffff).ram(); // Relocated internal RAM (RMCR = 30) - map(0x40000, 0x407ff).ram().share("shared_ram"); map(0x80002, 0x80002).portr("DSWA"); @@ -3216,9 +3207,10 @@ void toaplan2_state::tekipaki(machine_config &config) M68000(config, m_maincpu, 10_MHz_XTAL); // 10MHz Oscillator m_maincpu->set_addrmap(AS_PROGRAM, &toaplan2_state::tekipaki_68k_mem); - Z180(config, m_audiocpu, 10_MHz_XTAL); // HD647180 CPU actually - m_audiocpu->set_addrmap(AS_PROGRAM, &toaplan2_state::hd647180_mem_map); - m_audiocpu->set_addrmap(AS_IO, &toaplan2_state::hd647180_io_map); + hd647180x_device &audiocpu(HD647180X(config, m_audiocpu, 10_MHz_XTAL)); + // 16k byte ROM and 512 byte RAM are internal + audiocpu.set_addrmap(AS_IO, &toaplan2_state::hd647180_io_map); + audiocpu.in_pa_callback().set(FUNC(toaplan2_state::tekipaki_cmdavailable_r)); config.m_minimum_quantum = attotime::from_hz(600); @@ -3259,7 +3251,7 @@ void toaplan2_state::ghox(machine_config &config) M68000(config, m_maincpu, 10_MHz_XTAL); /* verified on pcb */ m_maincpu->set_addrmap(AS_PROGRAM, &toaplan2_state::ghox_68k_mem); - Z180(config, m_audiocpu, 10_MHz_XTAL); /* HD647180 CPU actually */ + HD647180X(config, m_audiocpu, 10_MHz_XTAL); m_audiocpu->set_addrmap(AS_PROGRAM, &toaplan2_state::ghox_hd647180_mem_map); config.m_minimum_quantum = attotime::from_hz(600); diff --git a/src/mame/includes/toaplan1.h b/src/mame/includes/toaplan1.h index 497c115e384..b84e1929948 100644 --- a/src/mame/includes/toaplan1.h +++ b/src/mame/includes/toaplan1.h @@ -255,7 +255,6 @@ private: DECLARE_WRITE_LINE_MEMBER(screen_vblank); void hd647180_io_map(address_map &map); - void hd647180_mem_map(address_map &map); void main_map(address_map &map); }; diff --git a/src/mame/includes/toaplan2.h b/src/mame/includes/toaplan2.h index 5144fb0aee9..3deeaebdc0a 100644 --- a/src/mame/includes/toaplan2.h +++ b/src/mame/includes/toaplan2.h @@ -225,7 +225,6 @@ private: void ghox_68k_mem(address_map &map); void ghox_hd647180_mem_map(address_map &map); void hd647180_io_map(address_map &map); - void hd647180_mem_map(address_map &map); void kbash2_68k_mem(address_map &map); void kbash_68k_mem(address_map &map); void kbash_v25_mem(address_map &map); |