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-rw-r--r--src/mess/machine/bbc.c365
1 files changed, 198 insertions, 167 deletions
diff --git a/src/mess/machine/bbc.c b/src/mess/machine/bbc.c
index dcb5f39189f..e5a9c0a254b 100644
--- a/src/mess/machine/bbc.c
+++ b/src/mess/machine/bbc.c
@@ -5,6 +5,8 @@
Gordon Jefferyes
mess_bbc@romvault.com
+ Nigel Barnes
+ ngbarnes@hotmail.com
******************************************************************************/
@@ -51,7 +53,7 @@ Model B memory handling functions
*************************/
/* the model B address all 16 of the ROM sockets */
-/* I have set bank 1 as a special case to load different DFS roms selectable from MESS's DIP settings var:bbc_DFSTypes */
+/* I have set bank 1 as a special case to load different DFS roms selectable from MESS's CONF settings var:bbc_DFSTypes */
WRITE8_MEMBER(bbc_state::bbc_page_selectb_w)
{
m_rombank=data&0x0f;
@@ -68,7 +70,7 @@ WRITE8_MEMBER(bbc_state::bbc_page_selectb_w)
WRITE8_MEMBER(bbc_state::bbc_memoryb3_w)
{
- if (m_RAMSize)
+ if (m_ram->size() == 32*1024)
{
m_region_maincpu->base()[offset + 0x4000] = data;
}
@@ -76,7 +78,6 @@ WRITE8_MEMBER(bbc_state::bbc_memoryb3_w)
{
m_region_maincpu->base()[offset] = data;
}
-
}
/* I have setup 3 types of sideways ram:
@@ -95,7 +96,8 @@ WRITE8_MEMBER(bbc_state::bbc_memoryb4_w)
{
// special DFS case for Acorn DFS E00 Hack that can write to the DFS RAM Bank;
if (m_DFSType == 3) m_region_user2->base()[((m_DFSType) << 14) + offset] = data;
- } else
+ }
+ else
{
switch (m_SWRAMtype)
{
@@ -181,23 +183,23 @@ WRITE8_MEMBER(bbc_state::bbc_memorybp1_w)
DIRECT_UPDATE_MEMBER(bbc_state::bbcbp_direct_handler)
{
- UINT8 *ram = m_region_maincpu->base();
+ UINT8 *RAM = m_region_maincpu->base();
if (m_vdusel == 0)
{
// not in shadow ram mode so just read normal ram
- m_bank2->set_base(ram + 0x3000);
+ m_bank2->set_base(RAM + 0x3000);
}
else
{
if (vdudriverset())
{
// if VDUDriver set then read from shadow ram
- m_bank2->set_base(ram + 0xb000);
+ m_bank2->set_base(RAM + 0xb000);
}
else
{
// else read from normal ram
- m_bank2->set_base(ram + 0x3000);
+ m_bank2->set_base(RAM + 0x3000);
}
}
return address;
@@ -206,23 +208,23 @@ DIRECT_UPDATE_MEMBER(bbc_state::bbcbp_direct_handler)
WRITE8_MEMBER(bbc_state::bbc_memorybp2_w)
{
- UINT8 *ram = m_region_maincpu->base();
+ UINT8 *RAM = m_region_maincpu->base();
if (m_vdusel==0)
{
// not in shadow ram mode so just write to normal ram
- ram[offset + 0x3000] = data;
+ RAM[offset + 0x3000] = data;
}
else
{
if (vdudriverset())
{
// if VDUDriver set then write to shadow ram
- ram[offset + 0xb000] = data;
+ RAM[offset + 0xb000] = data;
}
else
{
// else write to normal ram
- ram[offset + 0x3000] = data;
+ RAM[offset + 0x3000] = data;
}
}
}
@@ -292,7 +294,7 @@ ACCCON
b7 IRR 1=Causes an IRQ to the processor
b6 TST 1=Selects &FC00-&FEFF read from OS-ROM
-b5 IFJ 1=Internal 1 MHz bus
+b5 IFJ 1=Internal 1MHz bus
0=External 1MHz bus
b4 ITU 1=Internal Tube
0=External Tube
@@ -307,7 +309,7 @@ b0 D 1=Display LYNNE as screen
ACCCON is a read/write register
-HAZEL is the 8K of RAM used by the MOS,filling system, and other Roms at &C000-&DFFF
+HAZEL is the 8K of RAM used by the MOS, filing system, and other Roms at &C000-&DFFF
ANDY is the name of the 4K of RAM used by the MOS at &8000-&8FFF
@@ -342,7 +344,6 @@ WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
tempIRR=m_ACCCON_IRR;
-
m_ACCCON_IRR=(data>>7)&1;
m_ACCCON_TST=(data>>6)&1;
m_ACCCON_IFJ=(data>>5)&1;
@@ -390,7 +391,6 @@ WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
{
space.install_read_handler(0xFC00,0xFEFF,read8_delegate(FUNC(bbc_state::bbcm_r),this));
}
-
}
@@ -452,20 +452,20 @@ DIRECT_UPDATE_MEMBER(bbc_state::bbcm_direct_handler)
WRITE8_MEMBER(bbc_state::bbc_memorybm2_w)
{
- UINT8 *ram = m_region_maincpu->base();
+ UINT8 *RAM = m_region_maincpu->base();
if (m_ACCCON_X)
{
- ram[offset + 0xb000] = data;
+ RAM[offset + 0xb000] = data;
}
else
{
if (m_ACCCON_E && bbcm_vdudriverset())
{
- ram[offset + 0xb000] = data;
+ RAM[offset + 0xb000] = data;
}
else
{
- ram[offset + 0x3000] = data;
+ RAM[offset + 0x3000] = data;
}
}
}
@@ -480,13 +480,13 @@ WRITE8_MEMBER(bbc_state::bbc_memorybm4_w)
{
if (m_pagedRAM)
{
- m_region_maincpu->base()[offset+0x8000]=data;
+ m_region_maincpu->base()[offset+0x8000] = data;
}
else
{
if (bbc_master_sideways_ram_banks[m_rombank])
{
- m_region_user1->base()[offset+(m_rombank<<14)]=data;
+ m_region_user1->base()[offset+(m_rombank<<14)] = data;
}
}
}
@@ -496,7 +496,7 @@ WRITE8_MEMBER(bbc_state::bbc_memorybm5_w)
{
if (bbc_master_sideways_ram_banks[m_rombank])
{
- m_region_user1->base()[offset+(m_rombank<<14)+0x1000]=data;
+ m_region_user1->base()[offset+(m_rombank<<14)+0x1000] = data;
}
}
@@ -505,7 +505,7 @@ WRITE8_MEMBER(bbc_state::bbc_memorybm7_w)
{
if (m_ACCCON_Y)
{
- m_region_maincpu->base()[offset+0x9000]=data;
+ m_region_maincpu->base()[offset+0x9000] = data;
}
}
@@ -513,29 +513,48 @@ WRITE8_MEMBER(bbc_state::bbc_memorybm7_w)
/******************************************************************************
&FC00-&FCFF FRED
+&FC00-&FC03 Byte-Wide Expansion RAM
+&FC08-&FC0F Ample M2000 MIDI Interface (see also FCF0)
+&FC10-&FC13 Teletext
+&FC14-&FC1F Prestel
+&FC20-&FC27 IEEE 488 Interface
+&FC28-&FC2F Acorn Expansion, currently unused
+&FC30-&FC3F Cambridge Ring Interface
+&FC40-&FC47 Winchester Disc Interface
+&FC48-&FC7F Acorn Expansion, currently unused
+&FC80-&FC8F Test Hardware
+&FC90-&FCBF Acorn Expansion, currently unused
+&FCC0-&FCFE User Applications
+&FCF0-&FCF7 JGH/ETI MIDI Control (see also FC08)
+&FCFC-&FCFF Page-Wide Expansion RAM
+
&FD00-&FDFF JIM
-&FE00-&FEFF SHEILA Read Write
-&00-&07 6845 CRTC Video controller Video Controller 8 ( 2 bytes x 4 )
-&08-&0F 6850 ACIA Serial controller Serial Controller 8 ( 2 bytes x 4 )
-&10-&17 Serial ULA - Serial system chip 8 ( 1 byte x 8 )
-&18-&1F uPD7002 A to D converter A to D converter 8 ( 4 bytes x 2 )
-&20-&23 Video ULA - Video system chip 4 ( 2 bytes x 2 )
-&24-&27 FDC Latch 1770 Control latch 1770 Control latch 4 ( 1 byte x 4 )
-&28-&2F 1770 registers 1770 Disc Controller 1170 Disc Controller 8 ( 4 bytes x 2 )
-&30-&33 ROMSEL - ROM Select 4 ( 1 byte x 4 )
-&34-&37 ACCCON ACCCON select reg. ACCCON select reg 4 ( 1 byte x 4 )
-&38-&3F NC - -
-&40-&5F 6522 VIA SYSTEM VIA SYSTEM VIA 32 (16 bytes x 2 ) 1MHz
-&60-&7F 6522 VIA USER VIA USER VIA 32 (16 bytes x 2 ) 1MHz
-&80-&9F Int. Modem Int. Modem Int Modem
-&A0-&BF 68B54 ADLC ECONET controller ECONET controller 32 ( 4 bytes x 8 ) 2MHz
-&C0-&DF NC - -
-&E0-&FF Tube ULA Tube system interface Tube system interface 32 (32 bytes x 1 ) 2MHz
+&FD00-&FDFF Page-wide expansion RAM window
+&FD40-&FD4F Torch SASI/SCSI Hard Drive Access
+&FDFE-&FDFF Reset Test vector
+
+&FE00-&FEFF SHEILA Read Write
+&FE00-&FE07 6845 CRTC Video controller Video Controller 8 ( 2 bytes x 4 )
+&FE08-&FE0F 6850 ACIA Serial controller Serial Controller 8 ( 2 bytes x 4 )
+&FE10-&FE17 Serial ULA - Serial system chip 8 ( 1 byte x 8 )
+&FE18-&FE1F uPD7002 A to D converter A to D converter 8 ( 4 bytes x 2 )
+&FE20-&FE23 Video ULA - Video system chip 4 ( 2 bytes x 2 )
+&FE24-&FE27 FDC Latch 1770 Control latch 1770 Control latch 4 ( 1 byte x 4 )
+&FE28-&FE2F 1770 registers 1770 Disc Controller 1170 Disc Controller 8 ( 4 bytes x 2 )
+&FE30-&FE33 ROMSEL - ROM Select 4 ( 1 byte x 4 )
+&FE34-&3FE7 ACCCON ACCCON select reg. ACCCON select reg 4 ( 1 byte x 4 )
+&FE38-&FE3F NC - -
+&FE40-&FE5F 6522 VIA SYSTEM VIA SYSTEM VIA 32 (16 bytes x 2 ) 1MHz
+&FE60-&FE7F 6522 VIA USER VIA USER VIA 32 (16 bytes x 2 ) 1MHz
+&FE80-&FE9F 8271 registers 8271 Disk Controller 8271 Disk Controller
+&FEA0-&FEBF 68B54 ADLC ECONET controller ECONET controller 32 ( 4 bytes x 8 ) 2MHz
+&FEC0-&FEDF 6854 ADLC ECONET controller ECONET controller 32 ( 4 bytes x 8 ) 2MHz
+&FEE0-&FEFF Tube ULA Tube system interface Tube system interface 32 (32 bytes x 1 ) 2MHz
******************************************************************************/
READ8_MEMBER(bbc_state::bbcm_r)
{
-long myo;
+ long myo;
/* Now handled in bbcm_ACCCON_write PHS - 2008-10-11 */
// if ( m_ACCCON_TST )
@@ -553,14 +572,13 @@ long myo;
return 0xff;
};
-
if ((offset>=0x200) && (offset<=0x2ff)) /* SHEILA */
{
via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
via6522_device *via_1 = machine().device<via6522_device>("via6522_1");
device_t *adlc = machine().device("mc6854");
- myo=offset-0x200;
+ myo = offset-0x200;
if ((myo>=0x00) && (myo<=0x07)) return bbc_6845_r(space, myo-0x00); /* Video Controller */
if ((myo>=0x08) && (myo<=0x0f))
{
@@ -569,16 +587,16 @@ long myo;
else
return m_acia->data_read(space,0);
}
- if ((myo>=0x10) && (myo<=0x17)) return 0xfe; /* Serial System Chip */
+ if ((myo>=0x10) && (myo<=0x17)) return 0xfe; /* Serial System Chip */
if ((myo>=0x18) && (myo<=0x1f)) return uPD7002_r(machine().device("upd7002"), space, myo-0x18); /* A to D converter */
- if ((myo>=0x20) && (myo<=0x23)) return 0xfe; /* VideoULA */
- if ((myo>=0x24) && (myo<=0x27)) return bbcm_wd1770l_read(space, myo-0x24); /* 1770 */
- if ((myo>=0x28) && (myo<=0x2f)) return bbcm_wd1770_read(space, myo-0x28); /* disc control latch */
- if ((myo>=0x30) && (myo<=0x33)) return 0xfe; /* page select */
+ if ((myo>=0x20) && (myo<=0x23)) return 0xfe; /* VideoULA */
+ if ((myo>=0x24) && (myo<=0x27)) return bbcm_wd1770l_read(space, myo-0x24); /* 1770 */
+ if ((myo>=0x28) && (myo<=0x2f)) return bbcm_wd1770_read(space, myo-0x28); /* disc control latch */
+ if ((myo>=0x30) && (myo<=0x33)) return 0xfe; /* page select */
if ((myo>=0x34) && (myo<=0x37)) return bbcm_ACCCON_read(space, myo-0x34); /* ACCCON */
- if ((myo>=0x38) && (myo<=0x3f)) return 0xfe; /* NC ?? */
- if ((myo>=0x40) && (myo<=0x5f)) return via_0->read(space,myo-0x40);
- if ((myo>=0x60) && (myo<=0x7f)) return via_1->read(space,myo-0x60);
+ if ((myo>=0x38) && (myo<=0x3f)) return 0xfe; /* NC ?? */
+ if ((myo>=0x40) && (myo<=0x5f)) return via_0->read(space, myo-0x40);
+ if ((myo>=0x60) && (myo<=0x7f)) return via_1->read(space, myo-0x60);
if ((myo>=0x80) && (myo<=0x9f)) return 0xfe;
if ((myo>=0xa0) && (myo<=0xbf)) return mc6854_r(adlc, space, myo & 0x03);
if ((myo>=0xc0) && (myo<=0xdf)) return 0xfe;
@@ -590,7 +608,7 @@ long myo;
WRITE8_MEMBER(bbc_state::bbcm_w)
{
-long myo;
+ long myo;
if ((offset>=0x200) && (offset<=0x2ff)) /* SHEILA */
{
@@ -599,7 +617,7 @@ long myo;
device_t *adlc = machine().device("mc6854");
myo=offset-0x200;
- if ((myo>=0x00) && (myo<=0x07)) bbc_6845_w(space, myo-0x00,data); /* Video Controller */
+ if ((myo>=0x00) && (myo<=0x07)) bbc_6845_w(space, myo-0x00, data); /* Video Controller */
if ((myo>=0x08) && (myo<=0x0f))
{
if ((myo - 0x08) & 1)
@@ -607,22 +625,21 @@ long myo;
else
m_acia->data_write(space, 0, data);
}
- if ((myo>=0x10) && (myo<=0x17)) bbc_SerialULA_w(space, myo-0x10,data); /* Serial System Chip */
- if ((myo>=0x18) && (myo<=0x1f)) uPD7002_w(machine().device("upd7002"),space,myo-0x18,data); /* A to D converter */
- if ((myo>=0x20) && (myo<=0x23)) bbc_videoULA_w(space, myo-0x20,data); /* VideoULA */
- if ((myo>=0x24) && (myo<=0x27)) bbcm_wd1770l_write(space, myo-0x24,data); /* 1770 */
- if ((myo>=0x28) && (myo<=0x2f)) bbcm_wd1770_write(space, myo-0x28,data); /* disc control latch */
- if ((myo>=0x30) && (myo<=0x33)) page_selectbm_w(space, myo-0x30,data); /* page select */
- if ((myo>=0x34) && (myo<=0x37)) bbcm_ACCCON_write(space, myo-0x34,data); /* ACCCON */
- //if ((myo>=0x38) && (myo<=0x3f)) /* NC ?? */
- if ((myo>=0x40) && (myo<=0x5f)) via_0->write(space,myo-0x40, data);
- if ((myo>=0x60) && (myo<=0x7f)) via_1->write(space,myo-0x60, data);
+ if ((myo>=0x10) && (myo<=0x17)) bbc_SerialULA_w(space, myo-0x10, data); /* Serial System Chip */
+ if ((myo>=0x18) && (myo<=0x1f)) uPD7002_w(machine().device("upd7002"), space, myo-0x18, data); /* A to D converter */
+ if ((myo>=0x20) && (myo<=0x23)) bbc_videoULA_w(space, myo-0x20, data); /* VideoULA */
+ if ((myo>=0x24) && (myo<=0x27)) bbcm_wd1770l_write(space, myo-0x24, data); /* 1770 */
+ if ((myo>=0x28) && (myo<=0x2f)) bbcm_wd1770_write(space, myo-0x28, data); /* disc control latch */
+ if ((myo>=0x30) && (myo<=0x33)) page_selectbm_w(space, myo-0x30, data); /* page select */
+ if ((myo>=0x34) && (myo<=0x37)) bbcm_ACCCON_write(space, myo-0x34, data); /* ACCCON */
+ //if ((myo>=0x38) && (myo<=0x3f)) /* NC ?? */
+ if ((myo>=0x40) && (myo<=0x5f)) via_0->write(space, myo-0x40, data);
+ if ((myo>=0x60) && (myo<=0x7f)) via_1->write(space, myo-0x60, data);
//if ((myo>=0x80) && (myo<=0x9f))
if ((myo>=0xa0) && (myo<=0xbf)) mc6854_w(adlc, space, myo & 0x03, data);
//if ((myo>=0xc0) && (myo<=0xdf))
//if ((myo>=0xe0) && (myo<=0xff))
}
-
}
@@ -647,25 +664,24 @@ PB0-PB2 outputs
These 3 outputs form the address to an 8 bit addressable latch.
(IC32 74LS259)
-
PB3 output
----------
This output holds the data to be written to the selected
addressable latch bit.
-
PB4 and PB5 inputs
+------------------
These are the inputs from the joystick FIRE buttons. They are
normally at logic 1 with no button pressed and change to 0
when a button is pressed.
-
PB6 and PB7 inputs from the speech processor
+--------------------------------------------
PB6 is the speech processor 'ready' output and PB7 is from the
speech processor 'interrupt' output.
-
CA1 input
+---------
This is the vertical sync input from the 6845. CA1 is set up to
interrupt the 6502 every 20ms (50Hz) as a vertical sync from
the video circuity is detected. The operation system changes
@@ -674,24 +690,23 @@ they maintain synchronisation with the rest of the picture.
----------------------------------------------------------------
This is required for a lot of time function within the machine
and must be triggered every 20ms. (Should check at some point
-how this 20ms signal is made, and see if none standard shapped
+how this 20ms signal is made, and see if none standard shaped
screen modes change this time period.)
-
CB1 input
+---------
The CB1 input is the end of conversion (EOC) signal from the
7002 analogue to digital converter. It can be used to interrupt
the 6502 whenever a conversion is complete.
-
CA2 input
+---------
This input comes from the keyboard circuit, and is used to
generate an interrupt whenever a key is pressed. See the
keyboard circuit section for more details.
-
-
CB2 input
+---------
This is the light pen strobe signal (LPSTB) from the light pen.
If also connects to the 6845 video processor,
CB2 can be programmed to interrupt the processor whenever
@@ -718,16 +733,15 @@ B3 - Keyboard write enable
B4,B5 - these two outputs define the number to be added to the
start of screen address in hardware to control hardware scrolling:-
Mode Size Start of screen Number to add B5 B4
-0,1,2 20K &3000 12K 1 1
-3 16K &4000 16K 0 0
-4,5 10K &5800 (or &1800) 22K 1 0
-6 8K &6000 (or &2000) 24K 0 1
+0,1,2 20K &3000 12K 1 1
+3 16K &4000 16K 0 0
+4,5 10K &5800 (or &1800) 22K 1 0
+6 8K &6000 (or &2000) 24K 0 1
B6 - Operates the CAPS lock LED (Pin 17 keyboard connector)
B7 - Operates the SHIFT lock LED (Pin 16 keyboard connector)
******************************************************************************/
-
INTERRUPT_GEN_MEMBER(bbc_state::bbcb_keyscan)
{
static const char *const colnames[] = {
@@ -756,7 +770,6 @@ INTERRUPT_GEN_MEMBER(bbc_state::bbcb_keyscan)
{
via_0->write_ca2(0);
}
-
}
else
{
@@ -796,7 +809,6 @@ INTERRUPT_GEN_MEMBER(bbc_state::bbcm_keyscan)
{
via_0->write_ca2(0);
}
-
}
else
{
@@ -853,19 +865,18 @@ int bbc_state::bbc_keyboard(address_space &space, int data)
void bbc_state::bbcb_IC32_initialise(bbc_state *state)
{
- m_b0_sound=0x01; // Sound is negative edge trigered
- m_b1_speech_read=0x01; // ????
- m_b2_speech_write=0x01; // ????
- m_b3_keyboard=0x01; // Keyboard is negative edge trigered
- m_b4_video0=0x01;
- m_b5_video1=0x01;
- m_b6_caps_lock_led=0x01;
- m_b7_shift_lock_led=0x01;
-
+ m_b0_sound=0x01; // Write Enable to the sound generator IC
+ m_b1_speech_read=0x01; // READ select on the speech processor
+ m_b2_speech_write=0x01; // WRITE select on the speech processor
+ m_b3_keyboard=0x01; // Keyboard write enable
+ m_b4_video0=0x01; // These two outputs define the number to be added to the start of screen address
+ m_b5_video1=0x01; // in hardware to control hardware scrolling
+ m_b6_caps_lock_led=0x01; // Operates the CAPS lock LED
+ m_b7_shift_lock_led=0x01; // Operates the SHIFT lock LED
}
-/* This the BBC Masters Real Time Clock and NVRam IC */
+/* This the BBC Masters Real Time Clock and NVRAM IC */
void bbc_state::MC146818_set(address_space &space)
{
logerror ("146181 WR=%d DS=%d AS=%d CE=%d \n",m_MC146818_WR,m_MC146818_DS,m_MC146818_AS,m_MC146818_CE);
@@ -907,7 +918,7 @@ WRITE8_MEMBER(bbc_state::bbcb_via_system_write_porta)
if (m_b0_sound == 0)
{
//logerror("Doing an unsafe write to the sound chip %d \n",data);
- m_sn->write(space, 0,m_via_system_porta);
+ m_sn->write(space, 0, m_via_system_porta);
}
if (m_b3_keyboard == 0)
{
@@ -924,7 +935,6 @@ WRITE8_MEMBER(bbc_state::bbcb_via_system_write_portb)
bit = data & 0x07;
value = (data >> 3) & 0x01;
-
//logerror("SYSTEM write portb %d %d %d\n",data,bit,value);
if (value)
@@ -942,7 +952,7 @@ WRITE8_MEMBER(bbc_state::bbcb_via_system_write_portb)
{
if (m_MC146818_WR == 0)
{
- /* BBC MASTER has NV RAM Here */
+ /* BBC MASTER has NVRAM Here */
m_MC146818_WR = 1;
MC146818_set(space);
}
@@ -961,7 +971,7 @@ WRITE8_MEMBER(bbc_state::bbcb_via_system_write_portb)
{
if (m_MC146818_DS == 0)
{
- /* BBC MASTER has NV RAM Here */
+ /* BBC MASTER has NVRAM Here */
m_MC146818_DS = 1;
MC146818_set(space);
}
@@ -1096,7 +1106,6 @@ WRITE8_MEMBER(bbc_state::bbcb_via_system_write_portb)
}
-
if (m_Master)
{
//set the Address Select
@@ -1146,9 +1155,9 @@ READ8_MEMBER(bbc_state::bbcb_via_system_read_portb)
//TMSint=(!tms5220_int_r())&1;
//TMSrdy=(!tms5220_readyq_r())&1;
- //logerror("SYSTEM read portb %d\n",0xf | input_port(machine, "IN0")|(TMSint<<6)|(TMSrdy<<7));
+ //logerror("SYSTEM read portb %d\n",0xf | input_port(machine, "IN0") | (TMSint<<6)|(TMSrdy<<7));
- return (0xf | ioport("IN0")->read()|(TMSint<<6)|(TMSrdy<<7));
+ return (0xf | ioport("IN0")->read() | (TMSint<<6)|(TMSrdy<<7));
}
@@ -1162,7 +1171,7 @@ READ8_MEMBER(bbc_state::bbcb_via_system_read_ca1)
/* joystick EOC */
READ8_MEMBER(bbc_state::bbcb_via_system_read_cb1)
{
- return uPD7002_EOC_r(machine().device("upd7002"),space,0);
+ return uPD7002_EOC_r(machine().device("upd7002"), space, 0);
}
@@ -1289,7 +1298,6 @@ const uPD7002_interface bbc_uPD7002 =
****************************************/
-
void bbc_state::MC6850_Receive_Clock(int new_clock)
{
m_rxd_cass = new_clock;
@@ -1367,7 +1375,6 @@ TIMER_CALLBACK_MEMBER(bbc_state::bbc_tape_timer_cb)
m_len2=0;
m_len3=0;
m_wav_len=0;
-
}
m_len3=m_len2;
@@ -1406,8 +1413,6 @@ TIMER_CALLBACK_MEMBER(bbc_state::bbc_tape_timer_cb)
m_len2=0;
m_len3=0;
}
-
-
}
m_wav_len++;
@@ -1623,8 +1628,6 @@ WRITE8_MEMBER(bbc_state::bbc_i8271_write)
***************************************/
-
-
/*
B/ B+ drive control:
@@ -1728,7 +1731,6 @@ WRITE8_MEMBER(bbc_state::bbc_wd177x_status_w)
wd17xx_dden_w(fdc, BIT(data, 3));
m_1770_IntEnabled=(((data>>4) & 0x01)==0);
-
}
@@ -1838,7 +1840,6 @@ WRITE8_MEMBER(bbc_state::bbc_opus_status_w)
wd17xx_dden_w(fdc, BIT(data, 5));
m_1770_IntEnabled=(data>>4) & 0x01;
-
}
READ8_MEMBER(bbc_state::bbc_opus_read)
@@ -1861,7 +1862,6 @@ READ8_MEMBER(bbc_state::bbc_opus_read)
case 0xfb:
return wd17xx_data_r(fdc, space, 0);
}
-
}
else
{
@@ -2003,7 +2003,7 @@ READ8_MEMBER(bbc_state::bbc_disc_r)
/* case 0 to 3 are all standard 8271 interfaces */
case 0: case 1: case 2: case 3:
return bbc_i8271_read(space, offset);
- /* case 4 is the acown 1770 interface */
+ /* case 4 is the acorn 1770 interface */
case 4:
return bbc_wd1770_read(space, offset);
/* case 5 is the watford 1770 interface */
@@ -2027,7 +2027,7 @@ WRITE8_MEMBER(bbc_state::bbc_disc_w)
case 0: case 1: case 2: case 3:
bbc_i8271_write(space, offset,data);
break;
- /* case 4 is the acown 1770 interface */
+ /* case 4 is the acorn 1770 interface */
case 4:
bbc_wd1770_write(space, offset,data);
break;
@@ -2052,7 +2052,7 @@ WRITE8_MEMBER(bbc_state::bbc_disc_w)
***************************************/
DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbcb_cart )
{
- UINT8 *mem = m_region_user1->base();
+ UINT8 *RAM = m_region_user1->base();
int size, read_;
int addr = 0;
int index = 0;
@@ -2084,14 +2084,14 @@ DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbcb_cart )
switch (size)
{
case 0x2000:
- read_ = image.fread(mem + addr, size);
+ read_ = image.fread(RAM + addr, size);
if (read_ != size)
return 1;
image.fseek(0, SEEK_SET);
- read_ = image.fread(mem + addr + 0x2000, size);
+ read_ = image.fread(RAM + addr + 0x2000, size);
break;
case 0x4000:
- read_ = image.fread(mem + addr, size);
+ read_ = image.fread(RAM + addr, size);
break;
default:
read_ = 0;
@@ -2105,6 +2105,62 @@ DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbcb_cart )
}
+/**************************************
+ BBC Master Rom loading functions
+***************************************/
+DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbcm_cart )
+{
+ UINT8 *RAM = m_region_user1->base();
+ int size, read_;
+ int addr = 0;
+ int index = 0;
+
+ size = image.length();
+
+ if (strcmp(image.device().tag(),":cart1") == 0)
+ {
+ index = 0;
+ }
+ if (strcmp(image.device().tag(),":cart2") == 0)
+ {
+ index = 1;
+ }
+ if (strcmp(image.device().tag(),":cart3") == 0)
+ {
+ index = 2;
+ }
+ if (strcmp(image.device().tag(),":cart4") == 0)
+ {
+ index = 3;
+ }
+ addr = 0x8000 + (0x4000 * index);
+
+
+ logerror("loading rom %s at %.4x size:%.4x\n", image.filename(), addr, size);
+
+
+ switch (size)
+ {
+ case 0x2000:
+ read_ = image.fread(RAM + addr, size);
+ if (read_ != size)
+ return 1;
+ image.fseek(0, SEEK_SET);
+ read_ = image.fread(RAM + addr + 0x2000, size);
+ break;
+ case 0x4000:
+ read_ = image.fread(RAM + addr, size);
+ break;
+ default:
+ read_ = 0;
+ logerror("bad rom file size of %.4x\n", size);
+ break;
+ }
+
+ if (read_ != size)
+ return 1;
+ return 0;
+}
/**************************************
@@ -2137,10 +2193,21 @@ MACHINE_START_MEMBER(bbc_state,bbca)
MACHINE_RESET_MEMBER(bbc_state,bbca)
{
- UINT8 *ram = m_region_maincpu->base();
- m_RAMSize = 1;
- m_bank1->set_base(ram);
- m_bank3->set_base(ram);
+ UINT8 *RAM = m_region_maincpu->base();
+
+ m_bank1->set_base(RAM);
+ if (m_ram->size() == 32*1024)
+ {
+ /* 32K Model A */
+ m_bank3->set_base(RAM + 0x4000);
+ m_memorySize=32;
+ }
+ else
+ {
+ /* 16K just repeat the lower 16K*/
+ m_bank3->set_base(RAM);
+ m_memorySize=16;
+ }
m_bank4->set_base(m_region_user1->base()); /* bank 4 is the paged ROMs from 8000 to bfff */
m_bank7->set_base(m_region_user1->base()+0x10000); /* bank 7 points at the OS rom from c000 to ffff */
@@ -2151,58 +2218,25 @@ MACHINE_RESET_MEMBER(bbc_state,bbca)
MACHINE_START_MEMBER(bbc_state,bbcb)
{
m_mc6850_clock = 0;
- //removed from here because MACHINE_START can no longer read DIP swiches.
- //put in machine_reset instead.
- //m_DFSType= (ioport("BBCCONFIG")->read()>>0)&0x07;
- //m_SWRAMtype=(ioport("BBCCONFIG")->read()>>3)&0x03;
- //m_RAMSize= (ioport("BBCCONFIG")->read()>>5)&0x01;
-
- /*set up the required disc controller*/
- //switch (m_DFSType) {
- //case 0: case 1: case 2: case 3:
- m_previous_i8271_int_state=0;
- // break;
- //case 4: case 5: case 6:
- m_previous_wd177x_int_state=1;
- // break;
- //}
+ m_previous_i8271_int_state=0;
+ m_previous_wd177x_int_state=1;
}
MACHINE_RESET_MEMBER(bbc_state,bbcb)
{
- UINT8 *ram = m_region_maincpu->base();
+ UINT8 *RAM = m_region_maincpu->base();
m_DFSType= (ioport("BBCCONFIG")->read() >> 0) & 0x07;
m_SWRAMtype = (ioport("BBCCONFIG")->read() >> 3) & 0x03;
- m_RAMSize= (ioport("BBCCONFIG")->read() >> 5) & 0x01;
+ m_bank1->set_base(RAM);
+ m_bank3->set_base(RAM + 0x4000);
+ m_memorySize=32;
- m_bank1->set_base(ram);
- if (m_RAMSize)
- {
- /* 32K Model B */
- m_bank3->set_base(ram + 0x4000);
- m_memorySize=32;
- }
- else
- {
- /* 16K just repeat the lower 16K*/
- m_bank3->set_base(ram);
- m_memorySize=16;
- }
-
- m_bank4->set_base(m_region_user1->base()); /* bank 4 is the paged ROMs from 8000 to bfff */
+ m_bank4->set_base(m_region_user1->base()); /* bank 4 is the paged ROMs from 8000 to bfff */
m_bank7->set_base(m_region_user1->base() + 0x40000); /* bank 7 points at the OS rom from c000 to ffff */
bbcb_IC32_initialise(this);
-
m_opusbank = 0;
- /*set up the required disc controller*/
- //switch (m_DFSType) {
- //case 0: case 1: case 2: case 3:
- // break;
- //case 4: case 5: case 6:
- // break;
- //}
}
@@ -2213,32 +2247,30 @@ MACHINE_START_MEMBER(bbc_state,bbcbp)
m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(bbc_state::bbcbp_direct_handler), this));
/* bank 6 is the paged ROMs from b000 to bfff */
- m_bank6->configure_entries(0, 16, m_region_user1->base() + 0x3000, 1<<14);
+ m_bank6->configure_entries(0, 16, m_region_user1->base()+0x3000, 1<<14);
}
MACHINE_RESET_MEMBER(bbc_state,bbcbp)
{
m_bank1->set_base(m_region_maincpu->base());
m_bank2->set_base(m_region_maincpu->base()+0x03000); /* bank 2 screen/shadow ram from 3000 to 7fff */
- m_bank4->set_base(m_region_user1->base()); /* bank 4 is paged ROM or RAM from 8000 to afff */
+ m_bank4->set_base(m_region_user1->base()); /* bank 4 is paged ROM or RAM from 8000 to afff */
m_bank6->set_entry(0);
- m_bank7->set_base(m_region_user1->base()+0x40000); /* bank 7 points at the OS rom from c000 to ffff */
+ m_bank7->set_base(m_region_user1->base()+0x40000); /* bank 7 points at the OS rom from c000 to ffff */
bbcb_IC32_initialise(this);
-
m_previous_wd177x_int_state=1;
}
-
MACHINE_START_MEMBER(bbc_state,bbcm)
{
m_mc6850_clock = 0;
m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(bbc_state::bbcm_direct_handler), this));
- /* bank 5 is the paged ROMs from 9000 to bfff */
+ /* bank 5 is the paged ROMs from 9000 to bfff */
m_bank5->configure_entries(0, 16, m_region_user1->base()+0x01000, 1<<14);
/* Set ROM/IO bank to point to rom */
@@ -2250,12 +2282,11 @@ MACHINE_RESET_MEMBER(bbc_state,bbcm)
{
m_bank1->set_base(m_region_maincpu->base()); /* bank 1 regular lower ram from 0000 to 2fff */
m_bank2->set_base(m_region_maincpu->base() + 0x3000); /* bank 2 screen/shadow ram from 3000 to 7fff */
- m_bank4->set_base(m_region_user1->base()); /* bank 4 is paged ROM or RAM from 8000 to 8fff */
+ m_bank4->set_base(m_region_user1->base()); /* bank 4 is paged ROM or RAM from 8000 to 8fff */
m_bank5->set_entry(0);
- m_bank7->set_base(m_region_user1->base() + 0x40000); /* bank 6 OS rom of RAM from c000 to dfff */
+ m_bank7->set_base(m_region_user1->base() + 0x40000); /* bank 6 OS rom of RAM from c000 to dfff */
bbcb_IC32_initialise(this);
-
m_previous_wd177x_int_state=1;
}