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Diffstat (limited to 'src/mess/includes/dm7000.h')
-rw-r--r--src/mess/includes/dm7000.h50
1 files changed, 25 insertions, 25 deletions
diff --git a/src/mess/includes/dm7000.h b/src/mess/includes/dm7000.h
index b9b23621225..b7141fca791 100644
--- a/src/mess/includes/dm7000.h
+++ b/src/mess/includes/dm7000.h
@@ -11,7 +11,7 @@ public:
dm7000_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
- m_terminal(*this, TERMINAL_TAG) { }
+ m_terminal(*this, TERMINAL_TAG) { }
required_device<cpu_device> m_maincpu;
required_device<generic_terminal_device> m_terminal;
@@ -37,30 +37,30 @@ public:
DECLARE_WRITE16_MEMBER ( dm7000_enet_w );
DECLARE_READ16_MEMBER ( dm7000_enet_r );
- UINT16 m_enet_regs[32];
+ UINT16 m_enet_regs[32];
- UINT32 dcr[1024];
+ UINT32 dcr[1024];
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update_dm7000(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};
/* */
-#define UART_DLL 0
-#define UART_RBR 0
-#define UART_THR 0
-#define UART_DLH 1
-#define UART_IER 1
-#define UART_IIR 2
-#define UART_FCR 2
-#define UART_LCR 3
-#define UART_LCR_DLAB 0x80
-#define UART_MCR 4
-#define UART_LSR 5
-#define UART_LSR_TEMT 0x20
-#define UART_LSR_THRE 0x40
-#define UART_MSR 6
-#define UART_SCR 7
+#define UART_DLL 0
+#define UART_RBR 0
+#define UART_THR 0
+#define UART_DLH 1
+#define UART_IER 1
+#define UART_IIR 2
+#define UART_FCR 2
+#define UART_LCR 3
+#define UART_LCR_DLAB 0x80
+#define UART_MCR 4
+#define UART_LSR 5
+#define UART_LSR_TEMT 0x20
+#define UART_LSR_THRE 0x40
+#define UART_MSR 6
+#define UART_SCR 7
/* */
#define SCP_SPMODE 0
@@ -68,16 +68,16 @@ public:
#define SCP_TXDATA 2
#define SCP_SPCOM 3
#define SCP_STATUS 4
-#define SCP_STATUS_RXRDY 1
+#define SCP_STATUS_RXRDY 1
#define SCP_CDM 6
/* STB045xxx DCRs */
-#define DCRSTB045_CICVCR 0x033 /* CIC Video Control Register */
-#define DCRSTB045_SCCR 0x120 /* Serial Clock Control Register */
-#define DCRSTB045_VIDEO_CNTL 0x140 /* Video Control Register */
-#define DCRSTB045_CMD_STAT 0x14a /* Command status */
-#define DCRSTB045_DISP_MODE 0x154 /* Display Mode Register */
-#define DCRSTB045_FRAME_BUFR_BASE 0x179 /* Frame Buffers Base Address Register */
+#define DCRSTB045_CICVCR 0x033 /* CIC Video Control Register */
+#define DCRSTB045_SCCR 0x120 /* Serial Clock Control Register */
+#define DCRSTB045_VIDEO_CNTL 0x140 /* Video Control Register */
+#define DCRSTB045_CMD_STAT 0x14a /* Command status */
+#define DCRSTB045_DISP_MODE 0x154 /* Display Mode Register */
+#define DCRSTB045_FRAME_BUFR_BASE 0x179 /* Frame Buffers Base Address Register */
#endif /* DM7000_H_ */