diff options
Diffstat (limited to 'src/mess/drivers/ngen.c')
-rw-r--r-- | src/mess/drivers/ngen.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mess/drivers/ngen.c b/src/mess/drivers/ngen.c index ab2d3249c0f..6ba901c161b 100644 --- a/src/mess/drivers/ngen.c +++ b/src/mess/drivers/ngen.c @@ -406,7 +406,7 @@ READ16_MEMBER(ngen_state::peripheral_r) // X-bus module select // The bootstrap ROM creates a table at 0:FC9h, with a count, followed by the module IDs of each -// expansion module. The base I/O address for the currently selected module is set by writing to +// expansion module. The base I/O address for the currently selected module is set by writing to // this register (bits 0-7 are ignored) // TODO: make expansion modules slot devices WRITE16_MEMBER(ngen_state::xbus_w) @@ -435,7 +435,7 @@ WRITE16_MEMBER(ngen_state::xbus_w) READ16_MEMBER(ngen_state::xbus_r) { UINT16 ret = 0xffff; - + switch(m_xbus_current) { case 0x00: @@ -647,8 +647,8 @@ WRITE_LINE_MEMBER( ngen_state::dack3_w ) { set_dma_channel(3, state); } READ8_MEMBER(ngen_state::dma_3_dack_r) { - UINT16 ret = 0xffff; - + UINT16 ret = 0xffff; + if((m_hdc_control & 0x04) && m_disk_rom) { ret = m_disk_rom->base()[m_disk_rom_ptr++] << 8; @@ -659,7 +659,7 @@ READ8_MEMBER(ngen_state::dma_3_dack_r) //m_dmac->dreq3_w(0); } } - m_dma_high_byte = ret & 0xff00; + m_dma_high_byte = ret & 0xff00; return ret; } @@ -737,16 +737,16 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( ngen_io, AS_IO, 16, ngen_state ) AM_RANGE(0x0000, 0x0001) AM_READWRITE(xbus_r,xbus_w) - + // Floppy/Hard disk module -// AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff) // a guess for now -// AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff) -// AM_RANGE(0x010a, 0x010b) AM_WRITE8(hdc_control_w,0x00ff) -// AM_RANGE(0x010e, 0x010f) AM_WRITE8(disk_addr_ext,0x00ff) // X-Bus extended address register -// AM_RANGE(0x0110, 0x0117) AM_DEVREADWRITE8("fdc_timer",pit8253_device,read,write,0x00ff) +// AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff) // a guess for now +// AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff) +// AM_RANGE(0x010a, 0x010b) AM_WRITE8(hdc_control_w,0x00ff) +// AM_RANGE(0x010e, 0x010f) AM_WRITE8(disk_addr_ext,0x00ff) // X-Bus extended address register +// AM_RANGE(0x0110, 0x0117) AM_DEVREADWRITE8("fdc_timer",pit8253_device,read,write,0x00ff) // 0x0120-0x012f - WD1010 Winchester disk controller (unemulated) -// AM_RANGE(0x0130, 0x0137) AM_DEVREADWRITE8("hdc_timer",pit8253_device,read,write,0x00ff) - +// AM_RANGE(0x0130, 0x0137) AM_DEVREADWRITE8("hdc_timer",pit8253_device,read,write,0x00ff) + ADDRESS_MAP_END static ADDRESS_MAP_START( ngen386_mem, AS_PROGRAM, 32, ngen_state ) @@ -851,7 +851,7 @@ static MACHINE_CONFIG_START( ngen, ngen_state ) // keyboard UART (patent says i8251 is used for keyboard communications, it is located on the video board) MCFG_DEVICE_ADD("videouart", I8251, 0) // main clock unknown, Rx/Tx clocks are 19.53kHz -// MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) +// MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) MCFG_I8251_TXD_HANDLER(DEVWRITELINE("keyboard", rs232_port_device, write_txd)) MCFG_RS232_PORT_ADD("keyboard", keyboard, "ngen") MCFG_RS232_RXD_HANDLER(DEVWRITELINE("videouart", i8251_device, write_rxd)) @@ -865,12 +865,12 @@ static MACHINE_CONFIG_START( ngen, ngen_state ) MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w)) MCFG_WD_FDC_FORCE_READY MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0) - MCFG_PIT8253_CLK0(XTAL_20MHz / 20) + MCFG_PIT8253_CLK0(XTAL_20MHz / 20) MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) // clocked on FDC data register access MCFG_PIT8253_CLK1(XTAL_20MHz / 20) MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) // 1MHz MCFG_PIT8253_CLK2(XTAL_20MHz / 10) - MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) + MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) // TODO: WD1010 HDC (not implemented), use WD2010 for now MCFG_DEVICE_ADD("hdc", WD2010, XTAL_20MHz / 4) MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r)) |