diff options
Diffstat (limited to 'src/mame/sun/sun2_mt1.cpp')
| -rw-r--r-- | src/mame/sun/sun2_mt1.cpp | 401 |
1 files changed, 249 insertions, 152 deletions
diff --git a/src/mame/sun/sun2_mt1.cpp b/src/mame/sun/sun2_mt1.cpp index 69d28292df8..cb42d43d592 100644 --- a/src/mame/sun/sun2_mt1.cpp +++ b/src/mame/sun/sun2_mt1.cpp @@ -4,13 +4,20 @@ /* * Sun-2 machine type 1 processor. * - * 501-1007 2/100U, 2/150U - * 501-1051 2/120, 2/170 + * - Sun-2 Multibus 501-1007 + * - Sun-2 Multibus Prime 501-1051 + * + * - backplanes + * - Sun-2/120 501-1090 + * - Sun-2/170 501-1050 + * - Sun-2/120 501-1049 Prime + * - Sun-2/170 501-1150 Prime * * MULTIBUS * 370-0502 ? 0167 Computer Products Corporation TAPEMASTER * 370-1012 Xylogics 450 SMD controller * 370-1021 Sky Floating Point Processor Multibus + * * 501-0288 3COM 3C400 Ethernet * 501-0289 color video * 501-1003 monochrome video/keyboard/mouse ECL only @@ -105,26 +112,34 @@ How the architecture works: See http://sunstuff.org/Sun-Hardware-Ref/s2hr/part2 ****************************************************************************/ -/* - * bus errors - * - protection - * - timeout - * - parity - */ - #include "emu.h" #include "sun2_mt1.h" #include "sun2_mmu.h" +#include "bus/rs232/rs232.h" #include "cpu/m68000/m68010.h" #include "machine/am9513.h" +#include "machine/input_merger.h" #include "machine/mm58167.h" #include "machine/z80scc.h" -#include "machine/input_merger.h" -#include "bus/rs232/rs232.h" + +#define VERBOSE (LOG_GENERAL) +#include "logmacro.h" namespace { +enum enable_mask : u8 +{ + EN_PARGEN = 0x01, // enable parity generation + EN_INT1 = 0x02, // interrupt level 1 + EN_INT2 = 0x04, // interrupt level 2 + EN_INT3 = 0x08, // interrupt level 3 + EN_PARERR = 0x10, // enable parity checking + EN_DVMA = 0x20, // enable direct virtual memory access + EN_INT = 0x40, // enable interrupts + EN_BOOT_ = 0x80, // boot state (0=boot, 1=normal) +}; + class sun2_mt1_device : public device_t , public device_multibus_interface @@ -135,12 +150,14 @@ public: , device_multibus_interface(mconfig, *this) , m_cpu(*this, "cpu") , m_mmu(*this, "mmu") - , m_boot(*this, "boot") - , m_id(*this, "id") + , m_stc(*this, "stc") , m_scc(*this, "scc") , m_port(*this, "port%u", 0U) - , m_stc(*this, "stc") , m_rtc(*this, "rtc") + , m_irq(*this, "irq%u", 0U) + , m_boot(*this, "boot") + , m_id(*this, "id") + , m_dvma(*this, "dvma") , m_led(*this, "led%u", 0U) { } @@ -152,107 +169,149 @@ protected: virtual ioport_constructor device_input_ports() const override ATTR_COLD; virtual void device_start() override ATTR_COLD; virtual void device_reset() override ATTR_COLD; + virtual void device_reset_after_children() override ATTR_COLD; + + void cpu_map(address_map &map) ATTR_COLD; + void obi_map(address_map &map) ATTR_COLD; + + u16 mmu_r(offs_t offset, u16 mem_mask); + void mmu_w(offs_t offset, u16 data, u16 mem_mask); + + void enable_w(u8 data); + template <unsigned I> void interrupt_w(int state); private: required_device<m68010_device> m_cpu; required_device<sun2_mmu_device> m_mmu; - required_region_ptr<u16> m_boot; - required_region_ptr<u8> m_id; + required_device<am9513_device> m_stc; required_device<scc8530_device> m_scc; required_device_array<rs232_port_device, 2> m_port; - required_device<am9513_device> m_stc; required_device<mm58167_device> m_rtc; + required_device_array<input_merger_any_high_device, 8> m_irq; + + required_region_ptr<u16> m_boot; + required_region_ptr<u8> m_id; + memory_view m_dvma; + output_finder<8> m_led; - memory_access<24, 1, 0, ENDIANNESS_LITTLE>::specific m_bus_mem; - memory_access<16, 1, 0, ENDIANNESS_LITTLE>::specific m_bus_pio; + u8 m_enable; + u8 m_int; +}; - u16 mmu_r(offs_t offset, u16 mem_mask); - void mmu_w(offs_t offset, u16 data, u16 mem_mask); +void sun2_mt1_device::device_add_mconfig(machine_config &config) +{ + M68010(config, m_cpu, 39.3216_MHz_XTAL / 4); + m_cpu->set_addrmap(AS_PROGRAM, &sun2_mt1_device::cpu_map); - u16 dvma_r(offs_t offset, u16 mem_mask); - void dvma_w(offs_t offset, u16 data, u16 mem_mask); + INPUT_MERGER_ANY_HIGH(config, m_irq[0]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<0>)); + INPUT_MERGER_ANY_HIGH(config, m_irq[1]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<1>)); // soft 1 + INPUT_MERGER_ANY_HIGH(config, m_irq[2]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<2>)); // soft 2, scsi + INPUT_MERGER_ANY_HIGH(config, m_irq[3]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<3>)); // soft 3, net + INPUT_MERGER_ANY_HIGH(config, m_irq[4]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<4>)); // video + INPUT_MERGER_ANY_HIGH(config, m_irq[5]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<5>)); // stc 2,3,4,5 + INPUT_MERGER_ANY_HIGH(config, m_irq[6]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<6>)); // scc + INPUT_MERGER_ANY_HIGH(config, m_irq[7]).output_handler().set(FUNC(sun2_mt1_device::interrupt_w<7>)); // stc 1 + + // Multibus interrupts + int_callback<1>().set(m_irq[1], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<2>().set(m_irq[2], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<3>().set(m_irq[3], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<4>().set(m_irq[4], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<5>().set(m_irq[5], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<6>().set(m_irq[6], FUNC(input_merger_any_high_device::in_w<0>)).invert(); + int_callback<7>().set(m_irq[7], FUNC(input_merger_any_high_device::in_w<0>)).invert(); - void cpu_map(address_map &map) ATTR_COLD; - void mbustype1space_map(address_map &map) ATTR_COLD; + SUN2_MMU(config, m_mmu); + m_mmu->set_boot_prom(m_boot); + m_mmu->set_addrmap(sun2_mmu_device::OBI, &sun2_mt1_device::obi_map); + m_mmu->berr().set( + [this](offs_t offset, u8 data) + { + u8 const fc = m_cpu->get_fc(); - uint16_t m_sysenable; -}; + m_cpu->set_buserror_details(offset, data & sun2_mmu_device::READ, fc, data & sun2_mmu_device::FAULT); -u16 sun2_mt1_device::mmu_r(offs_t offset, u16 mem_mask) + if (!(data & sun2_mmu_device::FAULT)) + m_cpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); + }); + + AM9513A(config, m_stc, 39.3216_MHz_XTAL / 8); + m_stc->fout_cb().set(m_stc, FUNC(am9513_device::gate1_w)); + m_stc->out1_cb().set(m_irq[7], FUNC(input_merger_any_high_device::in_w<1>)); + m_stc->out2_cb().set(m_irq[5], FUNC(input_merger_any_high_device::in_w<1>)); + m_stc->out3_cb().set(m_irq[5], FUNC(input_merger_any_high_device::in_w<2>)); + m_stc->out4_cb().set(m_irq[5], FUNC(input_merger_any_high_device::in_w<3>)); + m_stc->out5_cb().set(m_irq[5], FUNC(input_merger_any_high_device::in_w<4>)); + + SCC8530(config, m_scc, 39.3216_MHz_XTAL / 8); + m_scc->out_txda_callback().set(m_port[0], FUNC(rs232_port_device::write_txd)); + m_scc->out_txdb_callback().set(m_port[1], FUNC(rs232_port_device::write_txd)); + m_scc->out_int_callback().set(m_irq[6], FUNC(input_merger_any_high_device::in_w<1>)); + + RS232_PORT(config, m_port[0], default_rs232_devices, nullptr); + m_port[0]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxa_w)); + m_port[0]->dcd_handler().set(m_scc, FUNC(z80scc_device::dcda_w)); + m_port[0]->cts_handler().set(m_scc, FUNC(z80scc_device::ctsa_w)); + + RS232_PORT(config, m_port[1], default_rs232_devices, nullptr); + m_port[1]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxb_w)); + m_port[1]->dcd_handler().set(m_scc, FUNC(z80scc_device::dcdb_w)); + m_port[1]->cts_handler().set(m_scc, FUNC(z80scc_device::ctsb_w)); + + MM58167(config, m_rtc, 32.768_kHz_XTAL); +} + +void sun2_mt1_device::device_config_complete() { - u8 const fc = m_cpu->get_fc(); - offs_t const va = offset << 1; + // 00'0000-03'f800 dvma + // 04'0000-07'f800 ethernet memory #1 + // 08'0000-08'3800 scsi #1 + // 08'4000-08'7800 scsi #2 + // 08'8000-08'b800 ethernet control #1 + // 08'c000-08'f800 ethernet control #2 + // 0a'0000-0a'f800 ethernet memory #2 + // 0c'0000-0d'f800 frame buffer - if (!machine().side_effects_disabled()) - { - switch (fc) - { - case 3: - switch (offset & 7) - { - case 0: return m_mmu->page_r(va); - case 1: return m_mmu->page_r(va); - case 2: return m_mmu->segment_r(va); - case 3: return m_mmu->context_r(); - case 4: return m_id[(offset >> 10) & 0x1f] << 8; - case 6: return m_mmu->buserror_r(); - case 7: return m_sysenable; - } - break; + // 0e'8000-0f'7800 sun color - case 6: - // boot mode - if (!(m_sysenable & 0x80)) - return m_boot[offset & 0x7fff]; - break; - } - } + // FIXME: avoid crash in validate + m_bus.lookup()->set_p2(m_mmu, sun2_mmu_device::OBM); - return m_mmu->mmu_r(fc, va, mem_mask); + m_mmu.lookup()->set_p1m(m_bus, AS_PROGRAM); + m_mmu.lookup()->set_p1i(m_bus, AS_IO); } -void sun2_mt1_device::mmu_w(offs_t offset, u16 data, u16 mem_mask) +void sun2_mt1_device::device_start() { - u8 const fc = m_cpu->get_fc(); - offs_t const va = offset << 1; + m_led.resolve(); - switch (fc) - { - case 3: - switch (offset & 7) - { - case 0: m_mmu->page_w(va, data); break; - case 1: m_mmu->page_w(va, data); break; - case 2: m_mmu->segment_w(va, data); break; - case 3: m_mmu->context_w(0, data, mem_mask); break; + save_item(NAME(m_enable)); + save_item(NAME(m_int)); - case 5: - // 0=on - for (unsigned i = 0; i < 8; i++) - m_led[i] = BIT(data, i); - break; + m_bus->space(AS_PROGRAM).install_view(0x0'0000, 0x3'ffff, m_dvma); - case 7: - COMBINE_DATA(&m_sysenable); - break; - } - break; + m_dvma[0].install_readwrite_handler(0x0'0000, 0x3'ffff, + emu::rw_delegate(m_mmu, FUNC(sun2_mmu_device::dvma_r)), + emu::rw_delegate(m_mmu, FUNC(sun2_mmu_device::dvma_w))); - default: - m_mmu->mmu_w(fc, va, data, mem_mask); - break; - } + m_int = 0; } -u16 sun2_mt1_device::dvma_r(offs_t offset, u16 mem_mask) +void sun2_mt1_device::device_reset() { - return m_mmu->mmu_r(5, offset << 1, mem_mask); + m_enable = 0; + + m_dvma.disable(); + + for (auto &led : m_led) + led = 0; } -void sun2_mt1_device::dvma_w(offs_t offset, u16 data, u16 mem_mask) + +void sun2_mt1_device::device_reset_after_children() { - m_mmu->mmu_w(5, offset << 1, data, mem_mask); + m_cpu->set_emmu_enable(true); } void sun2_mt1_device::cpu_map(address_map &map) @@ -260,102 +319,135 @@ void sun2_mt1_device::cpu_map(address_map &map) map(0x00'0000, 0xff'ffff).rw(FUNC(sun2_mt1_device::mmu_r), FUNC(sun2_mt1_device::mmu_w)); } -// type 1 device space -void sun2_mt1_device::mbustype1space_map(address_map &map) +// on-board I/O (type 1) +void sun2_mt1_device::obi_map(address_map &map) { map(0x00'0000, 0x00'07ff).rom().region("boot", 0); // uses MMU loophole to read 32k from a 2k window - // 001000-0017ff: AM9518 encryption processor + // 000800-000fff: reserved + // 001000-0017ff: AM9518 encryption processor (not fitted) // 001800-001fff: Parallel port map(0x00'2000, 0x00'27ff).rw(m_scc, FUNC(z80scc_device::ab_dc_r), FUNC(z80scc_device::ab_dc_w)).umask16(0xff00); map(0x00'2800, 0x00'2803).mirror(0x7fc).rw(m_stc, FUNC(am9513_device::read16), FUNC(am9513_device::write16)); + // 003000-0037ff: RasterOp processor (not fitted) map(0x00'3800, 0x00'383f).mirror(0x7c0).rw(m_rtc, FUNC(mm58167_device::read), FUNC(mm58167_device::write)).umask16(0xff00); // 12 wait states generated by PAL16R6 (U415) } -void sun2_mt1_device::device_start() +u16 sun2_mt1_device::mmu_r(offs_t offset, u16 mem_mask) { - m_led.resolve(); + u8 const fc = m_cpu->get_fc(); + offs_t const va = offset << 1; - m_bus->space(AS_PROGRAM).specific(m_bus_mem); - m_bus->space(AS_IO).specific(m_bus_pio); + switch (fc) + { + case 3: + switch (offset & 7) + { + case 0: return m_mmu->page_r(va); + case 1: return m_mmu->page_r(va); + case 2: return m_mmu->segment_r(va); + case 3: return m_mmu->context_r(); + case 4: return m_id[(offset >> 10) & 0x1f] << 8; + case 6: return m_mmu->buserror_r(); + case 7: return m_enable; + } + break; - m_bus->space(AS_PROGRAM).install_readwrite_handler(0x0'0000, 0x3'ffff, - emu::rw_delegate(*this, FUNC(sun2_mt1_device::dvma_r)), - emu::rw_delegate(*this, FUNC(sun2_mt1_device::dvma_w))); -} + case 6: + // boot mode + if (!(m_enable & EN_BOOT_)) + return m_boot[offset & 0x7fff]; + break; + } -void sun2_mt1_device::device_reset() -{ - m_sysenable = 0; + return m_mmu->mmu_r(fc, va, mem_mask); } -void sun2_mt1_device::device_add_mconfig(machine_config &config) +void sun2_mt1_device::mmu_w(offs_t offset, u16 data, u16 mem_mask) { - /* basic machine hardware */ - M68010(config, m_cpu, 39.3216_MHz_XTAL / 4); - m_cpu->set_addrmap(AS_PROGRAM, &sun2_mt1_device::cpu_map); + u8 const fc = m_cpu->get_fc(); + offs_t const va = offset << 1; - SUN2_MMU(config, m_mmu); - //m_mmu->set_ob_mem(m_bus, AS_DATA); // FIXME: share P2 from MMU to Multibus - m_mmu->set_addrmap(sun2_mmu_device::OB_PIO, &sun2_mt1_device::mbustype1space_map); - //m_mmu->set_p1_mem(m_bus, AS_PROGRAM); - //m_mmu->set_p1_pio(m_bus, AS_IO); - m_mmu->set_boot_prom(m_boot); - m_mmu->berr().set( - [this](offs_t offset, u8 data) + switch (fc) + { + case 3: + switch (offset & 7) { - u8 const fc = m_cpu->get_fc(); + case 0: m_mmu->page_w(va, data, mem_mask); break; + case 1: m_mmu->page_w(va, data, mem_mask); break; + case 2: m_mmu->segment_w(va, data); break; + case 3: m_mmu->context_w(0, data, mem_mask); break; + case 5: + for (unsigned i = 0; i < 8; i++) + m_led[i] = BIT(data, i); + break; + case 7: + if (mem_mask & 0x00ffU) + enable_w(data); + break; + } + break; - m_cpu->set_buserror_details(offset, (data & 2), fc, (data & 1)); + default: + m_mmu->mmu_w(fc, va, data, mem_mask); + break; + } +} - if (!(data & 1)) - m_cpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); - }); +void sun2_mt1_device::enable_w(u8 data) +{ + LOG("%s: enable_w 0x%02x\n", machine().describe_context(), data); - input_merger_any_high_device &irq5(INPUT_MERGER_ANY_HIGH(config, "irq5")); - irq5.output_handler().set_inputline(m_cpu, M68K_IRQ_5); // 74LS05 open collectors + if ((m_enable ^ data) & EN_DVMA) + { + if (data & EN_DVMA) + m_dvma.select(0); + else + m_dvma.disable(); + } - AM9513A(config, m_stc, 39.3216_MHz_XTAL / 8); - m_stc->fout_cb().set(m_stc, FUNC(am9513_device::gate1_w)); - m_stc->out1_cb().set_inputline(m_cpu, M68K_IRQ_7); - m_stc->out2_cb().set(irq5, FUNC(input_merger_device::in_w<0>)); - m_stc->out3_cb().set(irq5, FUNC(input_merger_device::in_w<1>)); - m_stc->out4_cb().set(irq5, FUNC(input_merger_device::in_w<2>)); - m_stc->out5_cb().set(irq5, FUNC(input_merger_device::in_w<3>)); + // handle interrupt disable + if ((m_enable & EN_INT) && !(data & EN_INT)) + { + // clear active interrupts + for (unsigned i = 1; i < 8; i++) + if (BIT(m_int, i)) + m_cpu->set_input_line(INPUT_LINE_IRQ0 + i, CLEAR_LINE); - SCC8530(config, m_scc, 39.3216_MHz_XTAL / 8); - m_scc->out_txda_callback().set(m_port[0], FUNC(rs232_port_device::write_txd)); - m_scc->out_txdb_callback().set(m_port[1], FUNC(rs232_port_device::write_txd)); - m_scc->out_int_callback().set_inputline(m_cpu, M68K_IRQ_6); + m_enable &= ~EN_INT; + } - RS232_PORT(config, m_port[0], default_rs232_devices, nullptr); - m_port[0]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxa_w)); - m_port[0]->dcd_handler().set(m_scc, FUNC(z80scc_device::dcda_w)); - m_port[0]->cts_handler().set(m_scc, FUNC(z80scc_device::ctsa_w)); + // handle soft interrupts 1-3 + if ((m_enable ^ data) & EN_INT1) + m_irq[1]->in_w<1>(data & EN_INT1); + if ((m_enable ^ data) & EN_INT2) + m_irq[2]->in_w<1>(data & EN_INT2); + if ((m_enable ^ data) & EN_INT3) + m_irq[3]->in_w<1>(data & EN_INT3); - RS232_PORT(config, m_port[1], default_rs232_devices, nullptr); - m_port[1]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxb_w)); - m_port[1]->dcd_handler().set(m_scc, FUNC(z80scc_device::dcdb_w)); - m_port[1]->cts_handler().set(m_scc, FUNC(z80scc_device::ctsb_w)); + // handle interrupt enable + if (!(m_enable & EN_INT) && (data & EN_INT)) + { + // assert active interrupts + for (unsigned i = 1; i < 8; i++) + if (BIT(m_int, i)) + m_cpu->set_input_line(INPUT_LINE_IRQ0 + i, ASSERT_LINE); + } - MM58167(config, m_rtc, 32.768_kHz_XTAL); + m_enable = data; } -void sun2_mt1_device::device_config_complete() +template <unsigned I> void sun2_mt1_device::interrupt_w(int state) { - m_mmu.lookup()->set_ob_mem(m_bus, AS_DATA); // FIXME: share P2 from MMU to Multibus + if (BIT(m_int, I) != state) + { + if (state) + m_int |= 1U << I; + else + m_int &= ~(1U << I); - // 00'0000-03'f800 dvma - // 04'0000-07'f800 ethernet memory #1 - // 08'0000-08'3800 scsi #1 - // 08'4000-08'7800 scsi #2 - // 08'8000-08'b800 ethernet control #1 - // 08'c000-08'f800 ethernet control #2 - // 0a'0000-0a'f800 ethernet memory #2 - // 0c'0000-0d'f800 frame buffer - // - // 0e'8000-0f'7800 sun color - m_mmu.lookup()->set_p1_mem(m_bus, AS_PROGRAM); - m_mmu.lookup()->set_p1_pio(m_bus, AS_IO); + if (m_enable & EN_INT) + m_cpu->set_input_line(INPUT_LINE_IRQ0 + I, state ? ASSERT_LINE : CLEAR_LINE); + } } static INPUT_PORTS_START(sun2_mt1) @@ -368,11 +460,13 @@ ioport_constructor sun2_mt1_device::device_input_ports() const ROM_START(sun2_mt1) // ROMs are located on the '501-1007' CPU PCB at locations B11 and B10; J400 is set to 1-2 for 27128 EPROMs and 3-4 for 27256 EPROMs ROM_REGION16_BE(0x10000, "boot", ROMREGION_ERASEFF) + // There is an undumped revision 1.1.2, which uses 27256 EPROMs - ROM_SYSTEM_BIOS(0, "rev10f", "Bootrom Rev 1.0F") + ROM_SYSTEM_BIOS(0, "rev10f", "Bootrom Rev 1.0F") // 87/12/29 Copyr 1986 Sun Micro ROMX_LOAD("1.0f.b11", 0x0000, 0x8000, CRC(8fb0050a) SHA1(399cdb894b2a66d847d76d8a5d266906fb1d3430), ROM_SKIP(1) | ROM_BIOS(0)) // actual rom stickers had fallen off ROMX_LOAD("1.0f.b10", 0x0001, 0x8000, CRC(70de816d) SHA1(67e980497f463dbc529f64ec5f3e0046b3901b7e), ROM_SKIP(1) | ROM_BIOS(0)) // " + // Rev R, @(#)version.c 2.8 85/02/19 Copyright (c) 1985 by Sun Microsystems, Inc. ROM_SYSTEM_BIOS(1, "revr", "Bootrom Rev R") ROMX_LOAD("520-1102-03.b11", 0x0000, 0x4000, CRC(020bb0a8) SHA1(a7b60e89a40757975a5d345d57ea02781dea4f89), ROM_SKIP(1) | ROM_BIOS(1)) ROMX_LOAD("520-1101-03.b10", 0x0001, 0x4000, CRC(b97c61f7) SHA1(9f08fe232cfc3da48539fa66673fc1f89a362b1e), ROM_SKIP(1) | ROM_BIOS(1)) @@ -382,16 +476,19 @@ ROM_START(sun2_mt1) // ROMs are located on the '501-1007' CPU PCB at locations B // ROMX_LOAD( "520-1104-02.b11", 0x0000, 0x4000, NO_DUMP, ROM_SKIP(1) | ROM_BIOS(8)) // ROMX_LOAD( "520-1103-02.b10", 0x0001, 0x4000, NO_DUMP, ROM_SKIP(1) | ROM_BIOS(8)) + // Rev N, @(#)version.c 2.7 84/02/06 Copyright (c) 1984 by Sun Microsystems, Inc. ROM_SYSTEM_BIOS( 2, "revn", "Bootrom Rev N") // SunOS 2.0 requires this bootrom version at a minimum; this version supports the sun-2 keyboard ROMX_LOAD("revn.b11", 0x0000, 0x4000, CRC(b1e70965) SHA1(726b3ed9323750a1ae238cf6dccaed6ff5981ad1), ROM_SKIP(1) | ROM_BIOS(2)) // actual rom stickers had fallen off ROMX_LOAD("revn.b10", 0x0001, 0x4000, CRC(95fd9242) SHA1(1eee2d291f4b18f6aafdde1a9521d88e454843b9), ROM_SKIP(1) | ROM_BIOS(2)) // " + // Rev M, @(#)version.c 2.6 83/09/19 Copyright (c) 1983 by Sun Microsystems, Inc. ROM_SYSTEM_BIOS( 3, "revm", "Bootrom Rev M") // SunOS 1.0 apparently requires this bootrom revision; this version might only support the sun-1 keyboard? ROMX_LOAD("sun2-revm-8.b11", 0x0000, 0x4000, CRC(98b8ae55) SHA1(55485f4d8fd1ebc218aa8527c8bb62752c34abf7), ROM_SKIP(1) | ROM_BIOS(3)) // handwritten label: "SUN2-RevM-8" ROMX_LOAD("sun2-revm-0.b10", 0x0001, 0x4000, CRC(5117f431) SHA1(fce85c11ada1614152dde35bb329350f6fb2ecd9), ROM_SKIP(1) | ROM_BIOS(3)) // handwritten label: "SUN2-RevM-0" ROM_REGION(0x20, "id", ROMREGION_ERASEFF) ROM_LOAD("sun2120-idprom.bin", 0x000000, 0x000020, CRC(eec8cd1d) SHA1(6a78dc0ea6f9cc7687cffea754d65864fb751ebf)) + //ROM_LOAD("idprom.u411", 0x000000, 0x000020, CRC(73f4c19e) SHA1(c672b6bf0028dae1c31ca87fbd75dad53864c060)) ROM_END const tiny_rom_entry *sun2_mt1_device::device_rom_region() const |
