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Diffstat (limited to 'src/mame/misc/39in1.cpp')
-rw-r--r--src/mame/misc/39in1.cpp131
1 files changed, 62 insertions, 69 deletions
diff --git a/src/mame/misc/39in1.cpp b/src/mame/misc/39in1.cpp
index 570428fe790..da0b1f90e94 100644
--- a/src/mame/misc/39in1.cpp
+++ b/src/mame/misc/39in1.cpp
@@ -62,6 +62,7 @@ public:
, m_eeprom(*this, "eeprom")
, m_ram(*this, "ram")
, m_mcu_ipt(*this, "MCUIPT")
+ , m_dsw(*this, "DSW")
{ }
void _39in1(machine_config &config);
@@ -83,66 +84,50 @@ public:
void init_plutus();
void init_pokrwild();
+ DECLARE_INPUT_CHANGED_MEMBER(set_flip_dip);
+ DECLARE_INPUT_CHANGED_MEMBER(set_res_dip);
+ DECLARE_INPUT_CHANGED_MEMBER(set_hiscore_dip);
+
+protected:
+ virtual void machine_reset() override;
+
private:
- uint32_t m_seed;
- uint32_t m_magic;
- uint32_t m_state;
- uint32_t m_mcu_ipt_pc;
+ u32 m_seed;
+ u32 m_magic;
+ u32 m_state;
+ u32 m_mcu_ipt_pc;
required_device<cpu_device> m_maincpu;
required_device<pxa255_periphs_device> m_pxa_periphs;
- required_device<eeprom_serial_93cxx_device> m_eeprom;
- required_shared_ptr<uint32_t> m_ram;
+ required_device<eeprom_serial_93c66_16bit_device> m_eeprom;
+ required_shared_ptr<u32> m_ram;
required_ioport m_mcu_ipt;
+ required_ioport m_dsw;
- uint32_t eeprom_r();
- void eeprom_w(uint32_t data, uint32_t mem_mask = ~0);
-
- uint32_t _39in1_cpld_r(offs_t offset);
- void _39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- uint32_t _39in1_prot_cheater_r();
+ u32 cpld_r(offs_t offset);
+ void cpld_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ u32 prot_cheater_r();
void _39in1_map(address_map &map);
void base_map(address_map &map);
- inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
-
- void decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t xor08, uint8_t xor10, uint8_t xor20, uint8_t xor40, uint8_t xor80, uint8_t bit7, uint8_t bit6, uint8_t bit5, uint8_t bit4, uint8_t bit3, uint8_t bit2, uint8_t bit1, uint8_t bit0);
- void further_decrypt(uint8_t xor400, uint8_t xor800, uint8_t xor1000, uint8_t xor2000, uint8_t xor4000, uint8_t xor8000);
+ void decrypt(u8 xor00, u8 xor02, u8 xor04, u8 xor08, u8 xor10, u8 xor20, u8 xor40, u8 xor80, u8 bit7, u8 bit6, u8 bit5, u8 bit4, u8 bit3, u8 bit2, u8 bit1, u8 bit0);
+ void further_decrypt(u8 xor400, u8 xor800, u8 xor1000, u8 xor2000, u8 xor4000, u8 xor8000);
};
-
-#define VERBOSE_LEVEL (0)
-
-inline void ATTR_PRINTF(3,4) _39in1_state::verboselog(int n_level, const char *s_fmt, ... )
+void _39in1_state::machine_reset()
{
- if (VERBOSE_LEVEL >= n_level)
- {
- va_list v;
- char buf[32768];
- va_start( v, s_fmt );
- vsprintf( buf, s_fmt, v );
- va_end( v );
- logerror("%s: %s", machine().describe_context(), buf);
- }
-}
+ m_pxa_periphs->gpio_in<1>(1);
-uint32_t _39in1_state::eeprom_r()
-{
- return (m_eeprom->do_read() << 5) | (1 << 1); // Must be on. Probably a DIP switch.
-}
+ const u32 dsw = m_dsw->read();
+ m_pxa_periphs->gpio_in<53>(BIT(dsw, 0));
+ m_pxa_periphs->gpio_in<54>(BIT(dsw, 1));
+ m_pxa_periphs->gpio_in<56>(BIT(dsw, 2));
-void _39in1_state::eeprom_w(uint32_t data, uint32_t mem_mask)
-{
- if (BIT(mem_mask, 2))
- m_eeprom->cs_write(ASSERT_LINE);
- if (BIT(mem_mask, 3))
- m_eeprom->clk_write(BIT(data, 3) ? ASSERT_LINE : CLEAR_LINE);
- if (BIT(mem_mask, 4))
- m_eeprom->di_write(BIT(data, 4));
+ m_eeprom->di_write(ASSERT_LINE);
}
-uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
+u32 _39in1_state::cpld_r(offs_t offset)
{
// if (m_maincpu->pc() != m_mcu_ipt_pc) printf("CPLD read @ %x (PC %x state %d)\n", offset, m_maincpu->pc(), m_state);
@@ -177,8 +162,8 @@ uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
}
else if (m_state == 2) // 29c0: 53 ac 0c 2b a2 07 e6 be 31
{
- uint32_t seed = m_seed;
- uint32_t magic = m_magic;
+ u32 seed = m_seed;
+ u32 magic = m_magic;
magic = ( (((~(seed >> 16)) ^ (magic >> 1)) & 0x01) |
(((~((seed >> 19) << 1)) ^ ((magic >> 5) << 1)) & 0x02) |
@@ -197,7 +182,7 @@ uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
return 0;
}
-void _39in1_state::_39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+void _39in1_state::cpld_w(offs_t offset, u32 data, u32 mem_mask)
{
if (mem_mask == 0xffff)
{
@@ -224,7 +209,7 @@ void _39in1_state::_39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask
#endif
}
-uint32_t _39in1_state::_39in1_prot_cheater_r()
+u32 _39in1_state::prot_cheater_r()
{
return 0x37;
}
@@ -233,12 +218,7 @@ void _39in1_state::base_map(address_map &map)
{
map(0x00000000, 0x0007ffff).rom();
map(0x00400000, 0x007fffff).rom().region("data", 0);
- map(0x40000000, 0x400002ff).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::dma_r), FUNC(pxa255_periphs_device::dma_w));
- map(0x40400000, 0x40400083).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::i2s_r), FUNC(pxa255_periphs_device::i2s_w));
- map(0x40a00000, 0x40a0001f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::ostimer_r), FUNC(pxa255_periphs_device::ostimer_w));
- map(0x40d00000, 0x40d00017).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::intc_r), FUNC(pxa255_periphs_device::intc_w));
- map(0x40e00000, 0x40e0006b).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::gpio_r), FUNC(pxa255_periphs_device::gpio_w));
- map(0x44000000, 0x4400021f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::lcd_r), FUNC(pxa255_periphs_device::lcd_w));
+ map(0x40000000, 0x47ffffff).m(m_pxa_periphs, FUNC(pxa255_periphs_device::map));
map(0xa0000000, 0xa07fffff).ram().share("ram");
}
@@ -246,8 +226,8 @@ void _39in1_state::_39in1_map(address_map &map)
{
base_map(map);
- map(0x04000000, 0x047fffff).rw(FUNC(_39in1_state::_39in1_cpld_r), FUNC(_39in1_state::_39in1_cpld_w));
- map(0xa0151648, 0xa015164b).r(FUNC(_39in1_state::_39in1_prot_cheater_r));
+ map(0x04000000, 0x047fffff).rw(FUNC(_39in1_state::cpld_r), FUNC(_39in1_state::cpld_w));
+ map(0xa0151648, 0xa015164b).r(FUNC(_39in1_state::prot_cheater_r));
}
static INPUT_PORTS_START( 39in1 )
@@ -288,23 +268,35 @@ static INPUT_PORTS_START( 39in1 )
// The following dips apply to 39in1 and 48in1. 60in1 is the same but the last unused dipsw#4 is test mode off/on.
PORT_START("DSW") // 1x 4-position DIP switch labelled SW3
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW3:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW3:1") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_flip_dip, 0)
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x00, "Display Mode" ) PORT_DIPLOCATION("SW3:2")
+ PORT_DIPNAME( 0x02, 0x00, "Display Mode" ) PORT_DIPLOCATION("SW3:2") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_res_dip, 0)
PORT_DIPSETTING( 0x02, "VGA 31.5kHz" )
PORT_DIPSETTING( 0x00, "CGA 15.75kHz" )
- PORT_DIPNAME( 0x04, 0x04, "High Score Saver" ) PORT_DIPLOCATION("SW3:3")
+ PORT_DIPNAME( 0x04, 0x04, "High Score Saver" ) PORT_DIPLOCATION("SW3:3") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_hiscore_dip, 0)
PORT_DIPSETTING( 0x04, "Disabled" )
PORT_DIPSETTING( 0x00, "Enabled" )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW3:4")
- PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
-void _39in1_state::decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t xor08, uint8_t xor10, uint8_t xor20, uint8_t xor40, uint8_t xor80, uint8_t bit7, uint8_t bit6, uint8_t bit5, uint8_t bit4, uint8_t bit3, uint8_t bit2, uint8_t bit1, uint8_t bit0)
+INPUT_CHANGED_MEMBER(_39in1_state::set_flip_dip)
+{
+ m_pxa_periphs->gpio_in<53>(BIT(m_dsw->read(), 0));
+}
+
+INPUT_CHANGED_MEMBER(_39in1_state::set_res_dip)
+{
+ m_pxa_periphs->gpio_in<54>(BIT(m_dsw->read(), 1));
+}
+
+INPUT_CHANGED_MEMBER(_39in1_state::set_hiscore_dip)
+{
+ m_pxa_periphs->gpio_in<56>(BIT(m_dsw->read(), 2));
+}
+
+void _39in1_state::decrypt(u8 xor00, u8 xor02, u8 xor04, u8 xor08, u8 xor10, u8 xor20, u8 xor40, u8 xor80, u8 bit7, u8 bit6, u8 bit5, u8 bit4, u8 bit3, u8 bit2, u8 bit1, u8 bit0)
{
- uint8_t *rom = memregion("maincpu")->base();
+ u8 *rom = memregion("maincpu")->base();
for (int i = 0; i < 0x80000; i += 2)
{
@@ -327,9 +319,9 @@ void _39in1_state::decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t
}
}
-void _39in1_state::further_decrypt(uint8_t xor400, uint8_t xor800, uint8_t xor1000, uint8_t xor2000, uint8_t xor4000, uint8_t xor8000) // later versions have more conditional XORs
+void _39in1_state::further_decrypt(u8 xor400, u8 xor800, u8 xor1000, u8 xor2000, u8 xor4000, u8 xor8000) // later versions have more conditional XORs
{
- uint8_t *rom = memregion("maincpu")->base();
+ u8 *rom = memregion("maincpu")->base();
for (int i = 0; i < 0x80000; i += 2)
{
@@ -370,12 +362,13 @@ void _39in1_state::base(machine_config &config)
PXA255(config, m_maincpu, 200'000'000);
m_maincpu->set_addrmap(AS_PROGRAM, &_39in1_state::base_map);
- EEPROM_93C66_16BIT(config, "eeprom");
+ EEPROM_93C66_16BIT(config, m_eeprom);
+ m_eeprom->do_callback().set(m_pxa_periphs, FUNC(pxa255_periphs_device::gpio_in<5>));
PXA255_PERIPHERALS(config, m_pxa_periphs, 200'000'000, m_maincpu);
- m_pxa_periphs->gpio0_write().set(FUNC(_39in1_state::eeprom_w));
- m_pxa_periphs->gpio0_read().set(FUNC(_39in1_state::eeprom_r));
- m_pxa_periphs->gpio1_read().set_ioport("DSW").lshift(21);
+ m_pxa_periphs->gpio_out<4>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::di_write));
+ m_pxa_periphs->gpio_out<2>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::cs_write));
+ m_pxa_periphs->gpio_out<3>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::clk_write));
}
void _39in1_state::_39in1(machine_config &config)