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Diffstat (limited to 'src/mame/machine/mips_rambo.h')
-rw-r--r--src/mame/machine/mips_rambo.h39
1 files changed, 35 insertions, 4 deletions
diff --git a/src/mame/machine/mips_rambo.h b/src/mame/machine/mips_rambo.h
index 34a659ea319..f3703cbabc3 100644
--- a/src/mame/machine/mips_rambo.h
+++ b/src/mame/machine/mips_rambo.h
@@ -21,9 +21,12 @@ public:
auto buzzer_out() { return m_buzzer_out_cb.bind(); }
template <typename T> void set_ram(T &&tag) { m_ram.set_tag(std::forward<T>(tag)); }
+ template <unsigned Channel> auto dma_r() { return m_channel[Channel].read_cb.bind(); }
+ template <unsigned Channel> auto dma_w() { return m_channel[Channel].write_cb.bind(); }
+
// input lines
template <unsigned Interrupt> DECLARE_WRITE_LINE_MEMBER(irq_w) {}
- template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(drq_w) {}
+ template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(drq_w);
void map(address_map &map);
u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@@ -37,11 +40,27 @@ protected:
template <unsigned Channel> DECLARE_READ32_MEMBER(diag_r) { return 0; }
template <unsigned Channel> DECLARE_READ16_MEMBER(fifo_r) { return 0; }
template <unsigned Channel> DECLARE_READ32_MEMBER(mode_r) { return m_channel[Channel].mode; }
- template <unsigned Channel> DECLARE_READ16_MEMBER(block_count_r) { return m_channel[Channel].block_count; }
- template <unsigned Channel> DECLARE_READ32_MEMBER(current_address_r) { return 0; }
+ template <unsigned Channel> DECLARE_READ16_MEMBER(block_count_r)
+ {
+ if ((Channel == 0) || !(m_channel[Channel].mode & MODE_CHANNEL_EN))
+ return m_channel[0].block_count;
+
+ /*
+ * HACK: The RISC/os boot sequence tests the dma channel 1 block count
+ * when configuring the monochrome graphics option. This hack simulates
+ * decrementing the block count for the video dma channel assuming a
+ * transfer of 1152x900 1-bit pixels at 72 Hz. With a device clock of
+ * 6.25 MHz, this is one block (64 bytes) approximately every 43 device
+ * cycles.
+ */
+ u64 const block_cycles = attotime_to_clocks(machine().time()) / 43;
+
+ return m_channel[Channel].block_count - (block_cycles % (m_channel[Channel].block_count + 1));
+ }
+ template <unsigned Channel> DECLARE_READ32_MEMBER(current_address_r) { return m_channel[Channel].current_address; }
DECLARE_READ32_MEMBER(tcount_r);
- DECLARE_READ32_MEMBER(tbreak_r) { return 0; }
+ DECLARE_READ32_MEMBER(tbreak_r) { return m_tbreak; }
DECLARE_READ32_MEMBER(error_r) { return 0; }
DECLARE_READ32_MEMBER(control_r) { return 0; }
@@ -54,6 +73,7 @@ protected:
DECLARE_WRITE32_MEMBER(tbreak_w);
DECLARE_WRITE32_MEMBER(control_w);
+ TIMER_CALLBACK_MEMBER(timer);
TIMER_CALLBACK_MEMBER(buzzer_toggle);
private:
@@ -73,6 +93,8 @@ private:
MODE_DMA_ERROR = 0x00000200, // parity error during transfer
MODE_DMA_INTR = 0x00000100, // channel interrupt pending
MODE_COUNT_MASK = 0x000000ff, // halfword count bits
+
+ MODE_WRITE_MASK = 0xff000000,
};
enum control_mask : u32
@@ -97,16 +119,25 @@ private:
u32 diag;
u32 mode;
u16 block_count;
+ u16 reload_count;
u32 current_address;
+
+ bool drq_asserted;
+
+ // FIXME: 16 bit dma
+ devcb_read8 read_cb;
+ devcb_write8 write_cb;
}
m_channel[2];
+ emu_timer *m_timer;
emu_timer *m_buzzer_timer;
int m_irq_out_state;
int m_buzzer_out_state;
attotime m_tcount;
+ u32 m_tbreak;
};
DECLARE_DEVICE_TYPE(MIPS_RAMBO, mips_rambo_device)