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Diffstat (limited to 'src/mame/machine/amstrad.cpp')
-rw-r--r--src/mame/machine/amstrad.cpp49
1 files changed, 26 insertions, 23 deletions
diff --git a/src/mame/machine/amstrad.cpp b/src/mame/machine/amstrad.cpp
index 022ff0b5c39..280c4a2cb28 100644
--- a/src/mame/machine/amstrad.cpp
+++ b/src/mame/machine/amstrad.cpp
@@ -505,9 +505,9 @@ void amstrad_state::amstrad_plus_dma_parse(int channel)
{
case 0x0000: // Load PSG register
{
- m_ay->address_w((command & 0x0f00) >> 8);
- m_ay->data_w(command & 0x00ff);
- m_ay->address_w(m_prev_reg);
+ m_ay->address_w(generic_space(), 0, (command & 0x0f00) >> 8);
+ m_ay->data_w(generic_space(), 0, command & 0x00ff);
+ m_ay->address_w(generic_space(), 0, m_prev_reg);
}
logerror("DMA %i: LOAD %i, %i\n",channel,(command & 0x0f00) >> 8, command & 0x00ff);
break;
@@ -1867,9 +1867,9 @@ READ8_MEMBER(amstrad_state::amstrad_cpc_io_r)
{
case 0x02:
// CRTC Type 1 (UM6845R) only!!
- //data = m_crtc->status_r();
+ //data = m_crtc->status_r( space, 0 );
if ( m_system_type == SYSTEM_PLUS || m_system_type == SYSTEM_GX4000 ) // All Plus systems are Type 3 (AMS40489)
- data = m_crtc->register_r();
+ data = m_crtc->register_r( space, 0 );
else
data = 0xff; // Type 0 (HD6845S/UM6845) and Type 2 (MC6845) return 0xff
#if 0
@@ -1890,7 +1890,7 @@ READ8_MEMBER(amstrad_state::amstrad_cpc_io_r)
break;
case 0x03:
/* All CRTC type : Read from selected internal 6845 register Read only */
- data = m_crtc->register_r();
+ data = m_crtc->register_r( space, 0 );
break;
}
}
@@ -1939,10 +1939,10 @@ The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which
switch (b8b0)
{
case 0x02:
- data = m_fdc->msr_r();
+ data = m_fdc->msr_r(space, 0);
break;
case 0x03:
- data = m_fdc->fifo_r();
+ data = m_fdc->fifo_r(space, 0);
break;
default:
break;
@@ -2043,7 +2043,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
switch ((offset & 0x0300) >> 8) // r1r0
{
case 0x00: /* Select internal 6845 register Write Only */
- m_crtc->address_w(data);
+ m_crtc->address_w( space, 0, data );
if ( m_system_type == SYSTEM_PLUS || m_system_type == SYSTEM_GX4000 )
amstrad_plus_seqcheck(data);
@@ -2058,7 +2058,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
timer_set(attotime::from_usec(0), TIMER_VIDEO_UPDATE, 1);
else
timer_set(attotime::from_usec(0), TIMER_VIDEO_UPDATE, 0);
- m_crtc->register_w(data);
+ m_crtc->register_w( space, 0, data );
/* printer port bit 8 */
if (m_printer_bit8_selected && m_system_type == SYSTEM_PLUS)
@@ -2158,7 +2158,7 @@ The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which
break;
case 0x03: /* Write Data register of FDC */
- m_fdc->fifo_w(data);
+ m_fdc->fifo_w(space, 0,data);
break;
default:
@@ -2196,6 +2196,7 @@ The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which
/* load CPCEMU style snapshots */
void amstrad_state::amstrad_handle_snapshot(unsigned char *pSnapshot)
{
+ address_space &space = m_maincpu->space(AS_PROGRAM);
int RegData;
int i;
@@ -2283,11 +2284,11 @@ void amstrad_state::amstrad_handle_snapshot(unsigned char *pSnapshot)
/* init CRTC */
for (i=0; i<18; i++)
{
- m_crtc->address_w(i);
- m_crtc->register_w(pSnapshot[0x043+i] & 0xff);
+ m_crtc->address_w( space, 0, i );
+ m_crtc->register_w( space, 0, pSnapshot[0x043+i] & 0xff );
}
- m_crtc->address_w(i);
+ m_crtc->address_w( space, 0, i );
/* upper rom selection */
m_gate_array.upper_bank = pSnapshot[0x055];
@@ -2302,11 +2303,11 @@ void amstrad_state::amstrad_handle_snapshot(unsigned char *pSnapshot)
/* PSG */
for (i=0; i<16; i++)
{
- m_ay->address_w(i);
- m_ay->data_w(pSnapshot[0x05b + i] & 0x0ff);
+ m_ay->address_w(space, 0, i);
+ m_ay->data_w(space, 0, pSnapshot[0x05b + i] & 0x0ff);
}
- m_ay->address_w(pSnapshot[0x05a]);
+ m_ay->address_w(space, 0, pSnapshot[0x05a]);
{
int MemSize;
@@ -2485,18 +2486,20 @@ BDIR BC1 |
/* PSG function selected */
void amstrad_state::update_psg()
{
+ address_space &space = m_maincpu->space(AS_PROGRAM);
+
if(m_aleste_mode & 0x20) // RTC selected
{
switch(m_aleste_rtc_function)
{
case 0x02: // AS
- m_rtc->write(0, m_ppi_port_outputs[amstrad_ppi_PortA]);
+ m_rtc->write(space, 0,m_ppi_port_outputs[amstrad_ppi_PortA]);
break;
case 0x04: // DS write
- m_rtc->write(1, m_ppi_port_outputs[amstrad_ppi_PortA]);
+ m_rtc->write(space, 1,m_ppi_port_outputs[amstrad_ppi_PortA]);
break;
case 0x05: // DS read
- m_ppi_port_inputs[amstrad_ppi_PortA] = m_rtc->read(1);
+ m_ppi_port_inputs[amstrad_ppi_PortA] = m_rtc->read(space, 1);
break;
}
return;
@@ -2508,12 +2511,12 @@ void amstrad_state::update_psg()
} break;
case 1:
{/* b6 = 1 ? : Read from selected PSG register and make the register data available to PPI Port A */
- m_ppi_port_inputs[amstrad_ppi_PortA] = m_ay->data_r();
+ m_ppi_port_inputs[amstrad_ppi_PortA] = m_ay->data_r(space, 0);
}
break;
case 2:
{/* b7 = 1 ? : Write to selected PSG register and write data to PPI Port A */
- m_ay->data_w(m_ppi_port_outputs[amstrad_ppi_PortA]);
+ m_ay->data_w(space, 0, m_ppi_port_outputs[amstrad_ppi_PortA]);
}
break;
case 3:
@@ -2521,7 +2524,7 @@ void amstrad_state::update_psg()
/* ignore if an invalid PSG register is selected, usually when the PPI port directions are changed after selecting the PSG register */
if(m_ppi_port_outputs[amstrad_ppi_PortA] <= 15)
{
- m_ay->address_w(m_ppi_port_outputs[amstrad_ppi_PortA]);
+ m_ay->address_w(space, 0, m_ppi_port_outputs[amstrad_ppi_PortA]);
m_prev_reg = m_ppi_port_outputs[amstrad_ppi_PortA];
}
}