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-rw-r--r--src/mame/includes/stlforce.h8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/mame/includes/stlforce.h b/src/mame/includes/stlforce.h
index 119b14c27af..f97e6e1ee5d 100644
--- a/src/mame/includes/stlforce.h
+++ b/src/mame/includes/stlforce.h
@@ -1,10 +1,8 @@
-class stlforce_state : public driver_data_t
+class stlforce_state : public driver_device
{
public:
- static driver_data_t *alloc(running_machine &machine) { return auto_alloc_clear(&machine, stlforce_state(machine)); }
-
- stlforce_state(running_machine &machine)
- : driver_data_t(machine) { }
+ stlforce_state(running_machine &machine, const driver_device_config_base &config)
+ : driver_device(machine, config) { }
tilemap_t *bg_tilemap;
tilemap_t *mlow_tilemap;
d='n115' href='#n115'>115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
// license:BSD-3-Clause
// copyright-holders:Luca Elia
/***************************************************************************

    The Dealer (Visco Games)

    Driver by Luca Elia
    This game runs on Seta Hardware

    P0-040A PCB:

    R65C02P2 x 2
    X0-009 (Intel 8742 MCU)

    X1-001
    X1-002
    X1-003
    X1-004
    X1-006

    Yamaha YM2149F

    MC68B50P ACIA

    DSW8 x 4, Reset Button
    CR2032 3V Battery
    XTAL 16MHz

***************************************************************************/

#include "emu.h"
#include "cpu/m6502/r65c02.h"
#include "machine/nvram.h"
#include "machine/timer.h"
#include "machine/watchdog.h"
#include "sound/ay8910.h"
#include "video/seta001.h"
#include "emupal.h"
#include "screen.h"
#include "speaker.h"


class thedealr_state : public driver_device
{
public:
	thedealr_state(const machine_config &mconfig, device_type type, const char *tag) :
		driver_device(mconfig, type, tag),
		m_maincpu(*this, "maincpu"),
		m_subcpu(*this, "subcpu"),
		m_seta001(*this, "spritegen"),
		m_palette(*this, "palette"),
		m_iox_io(*this, "IOX"),
		m_leds(*this, "led%u", 0U)
	{ }

	void thedealr(machine_config &config);

private:
	// IOX
	DECLARE_READ8_MEMBER(iox_r);
	DECLARE_WRITE8_MEMBER(iox_w);
	DECLARE_READ8_MEMBER(iox_status_r);
	uint8_t m_iox_cmd, m_iox_ret, m_iox_status, m_iox_leds, m_iox_coins;
	void iox_reset();

	// memory map
	DECLARE_READ8_MEMBER(irq_ack_r);
	DECLARE_WRITE8_MEMBER(unk_w);

	// machine
	TIMER_DEVICE_CALLBACK_MEMBER(thedealr_interrupt);

	// video
	DECLARE_PALETTE_INIT(thedealr);
	uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	DECLARE_WRITE_LINE_MEMBER(screen_vblank);

	void thedealr(address_map &map);
	void thedealr_sub(address_map &map);

	virtual void machine_start() override;
	virtual void machine_reset() override;

	// devices
	required_device<cpu_device> m_maincpu;
	required_device<cpu_device> m_subcpu;
	required_device<seta001_device> m_seta001;
	required_device<palette_device> m_palette;
	optional_ioport m_iox_io;
	output_finder<8> m_leds;
};

/***************************************************************************

    Video

***************************************************************************/

PALETTE_INIT_MEMBER(thedealr_state,thedealr)
{
	const uint8_t *color_prom = memregion("proms")->base();

	for (int i = 0; i < palette.entries(); i++)
	{
		int col = (color_prom[i] << 8) + color_prom[i + 512];
		palette.set_pen_color(i, pal5bit(col >> 10), pal5bit(col >> 5), pal5bit(col >> 0));
	}
}

uint32_t thedealr_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
	bitmap.fill(0x1f0, cliprect);

	m_seta001->set_bg_yoffsets(  0x11+1, -0x10 );   // + is up (down with flip)
	m_seta001->set_fg_yoffsets( -0x12+1, -0x01 );

	m_seta001->draw_sprites(screen, bitmap, cliprect, 0x1000, 1);
	return 0;
}

WRITE_LINE_MEMBER(thedealr_state::screen_vblank)
{
	// rising edge
	if (state)
		m_seta001->setac_eof();
}

/***************************************************************************

    IOX (i8742 MCU) Simulation

***************************************************************************/

#define IOX_OUT_FULL 0x01
#define IOX_IN_FULL  0x02
#define IOX_WAITDATA 0x80

void thedealr_state::iox_reset()
{
	m_iox_status    =   0x00;
	m_iox_ret       =   0x00;
	m_iox_cmd       =   0xff;
	m_iox_leds      =   0x00;
	m_iox_coins     =   0x00;
}

void thedealr_state::machine_reset()
{
	iox_reset();
}

// 3400
READ8_MEMBER(thedealr_state::iox_r)
{
	uint8_t ret = m_iox_ret;
	m_iox_status &= ~IOX_OUT_FULL;

	logerror("%s: IOX read %02X\n", machine().describe_context(), ret);
	return ret;
}
WRITE8_MEMBER(thedealr_state::iox_w)
{
	if (m_iox_status & IOX_WAITDATA)
	{
		m_iox_status &= ~IOX_WAITDATA;
		logerror("%s: IOX data %02X <- %02X\n", machine().describe_context(), m_iox_cmd, data);

		switch (m_iox_cmd)
		{
			case 0x20:  // leds
				m_iox_leds = data;
				m_leds[0] = BIT(data, 0);  // bet
				m_leds[1] = BIT(data, 1);  // deal
				m_leds[2] = BIT(data, 2);
				m_leds[3] = BIT(data, 3);
				m_leds[4] = BIT(data, 4);  // hold 1-5?
				m_leds[5] = BIT(data, 5);
				m_leds[6] = BIT(data, 6);
				m_leds[7] = BIT(data, 7);
				break;

			case 0x40:  // coin counters
				m_iox_coins = data;
				machine().bookkeeping().coin_counter_w(0, (~data) & 0x02); // coin1 or service coin
				machine().bookkeeping().coin_counter_w(1, (~data) & 0x04); // coupon
				machine().bookkeeping().coin_counter_w(2, (~data) & 0x08); // service coin
				machine().bookkeeping().coin_counter_w(3, (~data) & 0x10); // coin-out
				if ((~data) & 0xe1)
					logerror("%s: unknown bits written to command %02X: %02X\n", machine().describe_context(), m_iox_cmd, data);
				break;

			default:
				logerror("%s: data for unknown command written %02X = %02X\n", machine().describe_context(), m_iox_cmd, data);
				break;
		}

//      popmessage("LED: %02X COIN: %02X", m_iox_leds, m_iox_coins);
	}
	else
	{
		m_iox_cmd = data;
		logerror("%s: IOX command %02X\n", machine().describe_context(), m_iox_cmd);

		switch (m_iox_cmd)
		{
			case 0x01:  // inputs?
			{
				uint16_t buttons = m_iox_io->read();
				m_iox_ret = 0;
				for (int i = 0; i < 16; ++i)
				{
					if (buttons & (1<<i))
					{
						m_iox_ret = i + 1;
						break;
					}
				}
				m_iox_status |= IOX_OUT_FULL;
				break;
			}

//          case 0x04:  // ? at boot

			case 0x08:  // return iox version
				m_iox_ret = 0x54;
				m_iox_status |= IOX_OUT_FULL;
				break;

			case 0x20:  // leds
				m_iox_status |= IOX_WAITDATA;
				break;

			case 0x40:  // coin counters
				m_iox_status |= IOX_WAITDATA;
				break;

			case 0x80:  // store param?
				m_iox_status |= IOX_WAITDATA;
				break;

			case 0x81:  // store param?
				m_iox_status |= IOX_WAITDATA;
				break;

			case 0xff:  // reset
				iox_reset();
				break;

			default:
				logerror("%s: IOX unknown command %02X\n", machine().describe_context(), m_iox_cmd);
		}
	}
}

// 3401
READ8_MEMBER(thedealr_state::iox_status_r)
{
	// bit 0 - Out buff full?
	// bit 1 - In  buff full?
	// bit 7 - Ready for more data?
	return m_iox_status;
}

/***************************************************************************

    Memory Maps - Main CPU

***************************************************************************/

READ8_MEMBER(thedealr_state::irq_ack_r)
{
	m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
	return 0;
}

WRITE8_MEMBER(thedealr_state::unk_w)
{
	// bit 1 - ? 1 during game
	// bit 2 - ? 0 during game
	// bit 3 - ? 1 during game
	// bit 7 - ? 0 during game
//  popmessage("UNK %02x", data);
}

void thedealr_state::thedealr(address_map &map)
{
	map(0x0000, 0x07ff).ram().share("nvram");

	map(0x2000, 0x2000).ram(); // w ff at boot (after clearing commram)

	map(0x2400, 0x2400).r(FUNC(thedealr_state::irq_ack_r)); // r = irq ack.
	map(0x2400, 0x2400).w(FUNC(thedealr_state::unk_w));    // w = ?

	map(0x2800, 0x2800).portr("COINS").nopw();  // rw

	map(0x2801, 0x2801).portr("DSW4");
	map(0x2c00, 0x2c00).portr("DSW3");

	map(0x3400, 0x3400).rw(FUNC(thedealr_state::iox_r), FUNC(thedealr_state::iox_w));
	map(0x3401, 0x3401).r(FUNC(thedealr_state::iox_status_r));

	map(0x3000, 0x3000).ram(); // rw, comm in test mode
	map(0x3001, 0x3001).ram(); // rw, ""

	map(0x3800, 0x3bff).ram().share("commram");

	map(0x3c00, 0x3c00).rw("aysnd", FUNC(ay8910_device::data_r), FUNC(ay8910_device::address_w));
	map(0x3c01, 0x3c01).w("aysnd", FUNC(ay8910_device::data_w));

	map(0x8000, 0x8000).w("watchdog", FUNC(watchdog_timer_device::reset_w));
	map(0x8000, 0xffff).rom().region("maincpu", 0);
}

/***************************************************************************

    Memory Maps - Sub CPU

***************************************************************************/

void thedealr_state::thedealr_sub(address_map &map)
{
	// Work RAM
	map(0x0000, 0x00ff).ram();
	map(0x0100, 0x01ff).ram();

	// Sprites
	map(0x0800, 0x27ff).ram().rw(m_seta001, FUNC(seta001_device::spritecodelow_r8), FUNC(seta001_device::spritecodelow_w8));
	map(0x2800, 0x3fff).ram().rw(m_seta001, FUNC(seta001_device::spritecodehigh_r8), FUNC(seta001_device::spritecodehigh_w8));
	map(0x4000, 0x42ff).ram().rw(m_seta001, FUNC(seta001_device::spriteylow_r8), FUNC(seta001_device::spriteylow_w8));
	map(0x4300, 0x4303).w(m_seta001, FUNC(seta001_device::spritectrl_w8));
	map(0x4800, 0x4800).w(m_seta001, FUNC(seta001_device::spritebgflag_w8));   // enable / disable background transparency

	// Comm RAM
	map(0x5800, 0x5bff).ram().share("commram");

	// ROM
	map(0x6000, 0x7fff).rom().region("subcpu", 0x0000);
	map(0x8000, 0xffff).rom().region("subcpu", 0x8000);
}

/***************************************************************************

    Input Ports

***************************************************************************/

static INPUT_PORTS_START( thedealr )
	PORT_START("IOX")
	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_POKER_HOLD5   ) // HL5 (hold 5)
	PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_GAMBLE_HALF   ) // 1/2 (half gamble)
	PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_GAMBLE_LOW    ) PORT_NAME("Small") // SML (small)
	PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SERVICE1      ) PORT_NAME("Reset") // RST (reset)
	PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_GAMBLE_KEYOUT ) // PAY
	PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_SERVICE2      ) // (unused?)
	PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_POKER_BET     ) // BET (bet)
	PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_POKER_CANCEL  ) // MET (cancel? keep pressed to show stats)
	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_GAMBLE_HIGH   ) PORT_NAME("Big") // BIG (big)
	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_GAMBLE_D_UP   ) // D.U (double up?)
	PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_GAMBLE_DEAL   ) PORT_NAME("Deal / Draw") // D.D (deal/draw, advance in test mode, trigger leds)
	PORT_BIT( 0x0800, IP_ACTIVE_HIGH, IPT_GAMBLE_TAKE   ) // T.S (take score?)
	PORT_BIT( 0x1000, IP_ACTIVE_HIGH, IPT_POKER_HOLD4   ) // HL4 (hold 4)
	PORT_BIT( 0x2000, IP_ACTIVE_HIGH, IPT_POKER_HOLD3   ) // HL3 (hold 3)
	PORT_BIT( 0x4000, IP_ACTIVE_HIGH, IPT_POKER_HOLD2   ) // HL2 (hold 2)
	PORT_BIT( 0x8000, IP_ACTIVE_HIGH, IPT_POKER_HOLD1   ) // HL1 (hold 1)
	// DRP in test mode is an optional (via DSW) coin drop sensor?

	PORT_START("COINS")
	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SERVICE3 ) PORT_NAME("MSN?") // !MSN
	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_NAME("Attendant Clear?") // !ACL (reset jackpots, only if there are no credits)
	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT ) // A.P (attendant payout? clears credits, port 0 = ef)
	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_TILT          ) // TLT (tilt)
	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_CUSTOM       ) // HOV (hopper?)
	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN  ) // CPN (coupon, port 3 = fb)
	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2         ) PORT_IMPULSE(5) // CS2
	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1         ) PORT_IMPULSE(5) // CS1 (coin1, port 3 = fd)

	PORT_START("DSW1")
	PORT_DIPNAME( 0x07, 0x07, "SW1:1,2,3" ) PORT_DIPLOCATION("SW1:1,2,3") // table at EEFC
	PORT_DIPSETTING(    0x07, "0" )
	PORT_DIPSETTING(    0x06, "1" )
	PORT_DIPSETTING(    0x05, "2" )
	PORT_DIPSETTING(    0x04, "3" )
	PORT_DIPSETTING(    0x03, "4" )
	PORT_DIPSETTING(    0x02, "5" )
	PORT_DIPSETTING(    0x01, "6" )
	PORT_DIPSETTING(    0x00, "7" )
	PORT_DIPNAME( 0x18, 0x18, "SW1:4,5" ) PORT_DIPLOCATION("SW1:4,5")
	PORT_DIPSETTING(    0x18, "0" )
	PORT_DIPSETTING(    0x10, "1" )
	PORT_DIPSETTING(    0x08, "2" )
	PORT_DIPSETTING(    0x00, "3" )
	PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW1:6" )
/*
 Switches 7 & 8 control the payout as follows:

            Off/Off Off/On  On/Off  On/On   Notes
            ---------------------------------------------------------------------------------------------
Jackpot MB   5000    5000    5000    2000   Ryl Flush bonus at Max Bet
   Jackpot   2500    2500    2500    1000   Ryl Flush bonus at 5 coins + 500 (or 200) per coin up to Max Bet
   Mini JP   1500    1500    1000     500   Str Flush bonus at Max Bet
 Ryl Flush    500     500     500     200   x Bet
 Str Flush    150     150     100      50   x Bet
        4K     60      60      40      25   x Bet
Full House     10      10      10       8   x Bet
     Flush      7       6       7       6   x Bet
  Straight      5       5       5       5   x Bet
        3K      3       3       3       4   x Bet
  Two pair      2       2       2       2   x Bet
    Jacks+      1       1       1       1   x Bet (When enabled - DSW 3-2)

Return Rate 111.9%  110.7%  106.6%  105.8%  Jacks or Better
Return Rate  94.7%   92.9%   89.4%   87.8%  Two Pair

NOTE: Jackpot & Mini Jackpot values based on 10 Coin Max Bet. Values increase with higher Max Bet values.

Calculated returns based on 1 coin bet and paytable as shown above, Two Pair through Royal Flush without bonuses.
*/
	PORT_DIPNAME( 0xc0, 0xc0, "Payout Percentage" ) PORT_DIPLOCATION("SW1:7,8")
	PORT_DIPSETTING(    0x00, "87.8%" )  PORT_CONDITION("DSW3", 0x02, EQUALS, 0x02)
	PORT_DIPSETTING(    0x40, "89.4%" )  PORT_CONDITION("DSW3", 0x02, EQUALS, 0x02)
	PORT_DIPSETTING(    0x80, "92.9%" )  PORT_CONDITION("DSW3", 0x02, EQUALS, 0x02)
	PORT_DIPSETTING(    0xc0, "94.7%" )  PORT_CONDITION("DSW3", 0x02, EQUALS, 0x02)
	PORT_DIPSETTING(    0x00, "105.8%" ) PORT_CONDITION("DSW3", 0x02, EQUALS, 0x00)
	PORT_DIPSETTING(    0x40, "106.6%" ) PORT_CONDITION("DSW3", 0x02, EQUALS, 0x00)
	PORT_DIPSETTING(    0x80, "110.7%" ) PORT_CONDITION("DSW3", 0x02, EQUALS, 0x00)
	PORT_DIPSETTING(    0xc0, "111.9%" ) PORT_CONDITION("DSW3", 0x02, EQUALS, 0x00)

	PORT_START("DSW2")
	PORT_SERVICE_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW2:1" )
	PORT_DIPNAME( 0x06, 0x06, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW2:2,3")
	PORT_DIPSETTING(    0x06, DEF_STR( 1C_1C ) )
	PORT_DIPSETTING(    0x04, DEF_STR( 1C_2C ) )
	PORT_DIPSETTING(    0x02, DEF_STR( 1C_5C ) )
	PORT_DIPSETTING(    0x00, "1 Coin/10 Credits" )
	PORT_DIPNAME( 0x18, 0x18, "SW2:4,5" ) PORT_DIPLOCATION("SW2:4,5")
	PORT_DIPSETTING(    0x18, "0" )
	PORT_DIPSETTING(    0x10, "1" )
	PORT_DIPSETTING(    0x08, "2" )
	PORT_DIPSETTING(    0x00, "3" )
	PORT_DIPNAME( 0xe0, 0xe0, "Max Bet" ) PORT_DIPLOCATION("SW2:6,7,8")
	PORT_DIPSETTING(    0xc0, "5" )
	PORT_DIPSETTING(    0xe0, "10" )
	PORT_DIPSETTING(    0xa0, "20" )
	PORT_DIPSETTING(    0x80, "20 Duplicate" )
	PORT_DIPSETTING(    0x40, "30" )
	PORT_DIPSETTING(    0x00, "30 Duplicate" )
	PORT_DIPSETTING(    0x60, "60" )
	PORT_DIPSETTING(    0x20, "60 Duplicate" )

	PORT_START("DSW3")
	PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW3:1" )
	PORT_DIPNAME( 0x02, 0x02, "Lowest Paid Hand" ) PORT_DIPLOCATION("SW3:2")
	PORT_DIPSETTING(    0x02, "Two Pair" )
	PORT_DIPSETTING(    0x00, "Jacks or Better" )
	PORT_DIPNAME( 0x04, 0x04, "Double Up" ) PORT_DIPLOCATION("SW3:3")
	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW3:4" )
	PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW3:5" )
/*
Fever Mode:
  Overrides Jacks or Better
  3 of a Kind winning hand Jacks or higher enters Fever Mode
  You start with a pair of your 3 of a Kind cards & you draw 3 cards each hand.
    Jacks through Kings get 5 Fever Mode Draws
    Aces get 15 Fever Mode Draws
*/
	PORT_DIPNAME( 0x20, 0x20, "Fever Mode" ) PORT_DIPLOCATION("SW3:6")
	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW3:7" ) /* Overrides Coinage - 1C / 1C */
	PORT_DIPNAME( 0x80, 0x80, "Coin In / Coin Out" ) PORT_DIPLOCATION("SW3:8") /* No credit - payout waiting for hopper??? */
	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
	PORT_DIPSETTING(    0x00, DEF_STR( On ) )

	PORT_START("DSW4")
	PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW4:7" )   // X in service mode
	PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW4:8" )   // ""
	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW4:1")
	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW4:2" )   // "Excess switch time" error
	PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW4:3" )
	PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW4:4" )
	PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW4:5" )
	PORT_DIPUNKNOWN_DIPLOC( 0x80, 0x80, "SW4:6" )
INPUT_PORTS_END

/***************************************************************************

    Graphics Layouts

***************************************************************************/

// The bitplanes are separated (but there are 2 per rom)
static const gfx_layout layout_planes_2roms =
{
	16,16,
	RGN_FRAC(1,2),
	4,
	{RGN_FRAC(1,2)+8, RGN_FRAC(1,2)+0, 8, 0},
	{0,1,2,3,4,5,6,7, 128,129,130,131,132,133,134,135},
	{0*16,1*16,2*16,3*16,4*16,5*16,6*16,7*16,
		16*16,17*16,18*16,19*16,20*16,21*16,22*16,23*16 },
	16*16*2
};

static GFXDECODE_START( gfx_thedealr )
	GFXDECODE_ENTRY( "gfx1", 0, layout_planes_2roms, 0, 32 )
GFXDECODE_END

/***************************************************************************

    Machine Drivers

***************************************************************************/

void thedealr_state::machine_start()
{
	m_leds.resolve();

	save_item(NAME(m_iox_status));
	save_item(NAME(m_iox_ret));
	save_item(NAME(m_iox_cmd));
	save_item(NAME(m_iox_leds));
	save_item(NAME(m_iox_coins));
}

/*
    It takes $19 IRQs to cycle through the IOX routines (read version/inputs, write outputs).
    With a single IRQ per frame this would translate to acknowledging inputs only every 0.4 seconds!
    Hence we generate more IRQs than that in a frame. Besides, with a single VBLANK IRQ,
    the two 65C02 fail to sync properly on boot with error $26 and/or $27 (commram[0]) !?
*/
TIMER_DEVICE_CALLBACK_MEMBER(thedealr_state::thedealr_interrupt)
{
	int scanline = param;

	if((scanline % 8) == 0)
		m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
}

MACHINE_CONFIG_START(thedealr_state::thedealr)

	// basic machine hardware
	MCFG_DEVICE_ADD("maincpu", R65C02, XTAL(16'000'000)/8)   // 2 MHz?
	MCFG_DEVICE_PROGRAM_MAP(thedealr)
	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", thedealr_state, thedealr_interrupt, "screen", 0, 1)

	MCFG_DEVICE_ADD("subcpu", R65C02, XTAL(16'000'000)/8)    // 2 MHz?
	MCFG_DEVICE_PROGRAM_MAP(thedealr_sub)

	MCFG_NVRAM_ADD_0FILL("nvram")

	MCFG_WATCHDOG_ADD("watchdog")

	MCFG_DEVICE_ADD("spritegen", SETA001_SPRITE, 0)
	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")

	// video hardware
	MCFG_SCREEN_ADD("screen", RASTER)
	MCFG_SCREEN_REFRESH_RATE(60)
	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	MCFG_SCREEN_SIZE(512, 256)
	MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0+30, 256-1)
	MCFG_SCREEN_UPDATE_DRIVER(thedealr_state, screen_update)
	MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, thedealr_state, screen_vblank))
	MCFG_DEVCB_CHAIN_OUTPUT(INPUTLINE("subcpu", INPUT_LINE_NMI))
	MCFG_SCREEN_PALETTE("palette")

	MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_thedealr)
	MCFG_PALETTE_ADD("palette", 512)
	MCFG_PALETTE_INIT_OWNER(thedealr_state,thedealr)

	// sound hardware
	SPEAKER(config, "mono").front_center();
	MCFG_DEVICE_ADD("aysnd", YM2149, XTAL(16'000'000)/8)   // 2 MHz?
	MCFG_AY8910_PORT_A_READ_CB(IOPORT("DSW2"))
	MCFG_AY8910_PORT_B_READ_CB(IOPORT("DSW1"))
	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MACHINE_CONFIG_END

/***************************************************************************

    ROMs Loading

***************************************************************************/

ROM_START( thedealr )
	ROM_REGION( 0x8000, "maincpu", 0 )
	ROM_LOAD( "xb4_002", 0x00000, 0x08000, CRC(022fc8c4) SHA1(f29909ac22df9390f5bc1dec5f4dc5ae2c4d2e61) )

	ROM_REGION( 0x10000, "subcpu", 0 )
	ROM_LOAD( "xb3_002", 0x00000, 0x10000, CRC(53a37fa4) SHA1(2adfea2dd08f298cda885bc72606d03f8af886a0) )

	// To do: hook up
	ROM_REGION( 0x0800, "iocpu", 0 )
	ROM_LOAD( "x0-009",  0x0000, 0x0800, CRC(e8b86d5a) SHA1(ad12e8f4411c30cd691792c6b0b3429db786d8b5) )

	ROM_REGION( 0x100000, "gfx1", 0 )
	ROM_LOAD( "xb0-002-w45.u42", 0x00000, 0x80000, CRC(41ec6a57) SHA1(d3f0508d5f4054fd2b0ee5227325a95fd1272aad) )
	ROM_LOAD( "xb0-001-w44.u41", 0x80000, 0x80000, CRC(bdaca555) SHA1(5ae1dc1514993fd804a101182735d5fb6815f720) )

	ROM_REGION( 0x0400, "proms", 0 )
	ROM_LOAD( "xb0-u65.u65", 0x000, 0x200, CRC(5969a133) SHA1(f92f17949c1974d779d31741afd137f9217af3b9) )
	ROM_LOAD( "xb0-u68.u68", 0x200, 0x200, CRC(c0c54d43) SHA1(5ce352fb888c8e683014c73e6da00ec95f2ae572) )
ROM_END

GAME( 1988?, thedealr, 0, thedealr, thedealr, thedealr_state, empty_init, ROT0, "Visco Games", "The Dealer (Visco)", MACHINE_SUPPORTS_SAVE )
"> s3.cursor_fg_ptr %= 4; break; /* 3d4h index 4Bh (R/W): Hardware Graphics Cursor Background Stack (80x +) bit 0-7 The Background Cursor color. Three bytes (4 for the 864/964) are stacked here. When the Cursor Mode register (3d4h index 45h) is read the stackpointer is reset. When a byte is written the byte is written into the current top of stack and the stackpointer is increased. The first byte written (item 0) is allways used, the other two(3) only when Hardware Cursor Horizontal Stretch (3d4h index 45h bit 2-3) is enabled. */ case 0x4b: s3.cursor_bg[s3.cursor_bg_ptr++] = data; s3.cursor_bg_ptr %= 4; break; /* 3d4h index 4Ch M(R/W): CR4C/D Hardware Graphics Cursor Storage Start Address bit 0-9 (911,924) HCS_STADR. Hardware Graphics Cursor Storage Start Address 0-11 (80x,928) HWGC_STA. Hardware Graphics Cursor Storage Start Address 0-12 (864,964) HWGC_STA. Hardware Graphics Cursor Storage Start Address Address of the HardWare Cursor Map in units of 1024 bytes (256 bytes for planar modes). The cursor map is a 64x64 bitmap with 2 bits (A and B) per pixel. The map is stored as one word (16 bits) of bit A, followed by one word with the corresponding 16 B bits. The bits are interpreted as: A B MS-Windows: X-11: 0 0 Background Screen data 0 1 Foreground Screen data 1 0 Screen data Background 1 1 Inverted screen Foreground The Windows/X11 switch is only available for the 80x +. (911/24) For 64k color modes the cursor is stored as one byte (8 bits) of A bits, followed by the 8 B-bits, and each bit in the cursor should be doubled to provide a consistent cursor image. (801/5,928) For Hi/True color modes use the Horizontal Stretch bits (3d4h index 45h bits 2 and 3). */ case 0x4c: s3.cursor_start_addr = (s3.cursor_start_addr & 0x00ff) | (data << 8); LOGREG("HW Cursor Address: %08x\n",s3.cursor_start_addr); break; case 0x4d: s3.cursor_start_addr = (s3.cursor_start_addr & 0xff00) | data; LOGREG("HW Cursor Address: %08x\n",s3.cursor_start_addr); break; /* 3d4h index 4Eh (R/W): CR4E HGC Pattern Disp Start X-Pixel Position bit 0-5 Pattern Display Start X-Pixel Position. */ case 0x4e: s3.cursor_pattern_x = data; break; /* 3d4h index 4Fh (R/W): CR4F HGC Pattern Disp Start Y-Pixel Position bit 0-5 Pattern Display Start Y-Pixel Position. */ case 0x4f: s3.cursor_pattern_y = data; break; case 0x51: s3.cr51 = data; vga.crtc.start_addr_latch &= ~0xc0000; vga.crtc.start_addr_latch |= ((data & 0x3) << 18); svga.bank_w = (svga.bank_w & 0xcf) | ((data & 0x0c) << 2); svga.bank_r = svga.bank_w; if((data & 0x30) != 0x00) vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x30) << 4); else vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((s3.cr43 & 0x04) << 6); s3_define_video_mode(); break; case 0x53: s3.cr53 = data; break; /* 3d4h index 55h (R/W): Extended Video DAC Control Register (80x +) bit 0-1 DAC Register Select Bits. Passed to the RS2 and RS3 pins on the RAMDAC, allowing access to all 8 or 16 registers on advanced RAMDACs. If this field is 0, 3d4h index 43h bit 1 is active. 2 Enable General Input Port Read. If set DAC reads are disabled and the STRD strobe for reading the General Input Port is enabled for reading while DACRD is active, if clear DAC reads are enabled. 3 (928) Enable External SID Operation if set. If set video data is passed directly from the VRAMs to the DAC rather than through the VGA chip 4 Hardware Cursor MS/X11 Mode. If set the Hardware Cursor is in X11 mode, if clear in MS-Windows mode 5 (80x,928) Hardware Cursor External Operation Mode. If set the two bits of cursor data ,is output on the HC[0-1] pins for the video DAC The SENS pin becomes HC1 and the MID2 pin becomes HC0. 6 ?? 7 (80x,928) Disable PA Output. If set PA[0-7] and VCLK are tristated. (864/964) TOFF VCLK. Tri-State Off VCLK Output. VCLK output tri -stated if set */ case 0x55: s3.extended_dac_ctrl = data; break; case 0x58: s3virge.linear_address_size = data & 0x03; s3virge.linear_address_enable = data & 0x10; switch(data & 0x03) { case LAW_64K: s3virge.linear_address_size_full = 0x10000; break; case LAW_1MB: s3virge.linear_address_size_full = 0x100000; break; case LAW_2MB: s3virge.linear_address_size_full = 0x200000; break; case LAW_4MB: s3virge.linear_address_size_full = 0x400000; break; } LOGREG("CR58: write %02x\n", data); break; case 0x59: s3virge.linear_address = (s3virge.linear_address & 0x00ff0000) | (data << 24); LOGREG("Linear framebuffer address = %08x\n",s3virge.linear_address); break; case 0x5a: s3virge.linear_address = (s3virge.linear_address & 0xff000000) | (data << 16); LOGREG("Linear framebuffer address = %08x\n",s3virge.linear_address); break; /* 3d4h index 5Dh (R/W): Extended Horizontal Overflow Register (80x +) bit 0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h index 0) 1 Horizontal Display End bit 8. Bit 8 of the Horizontal Display End register (3d4h index 1) 2 Start Horizontal Blank bit 8. Bit 8 of the Horizontal Start Blanking register (3d4h index 2). 3 (864,964) EHB+64. End Horizontal Blank +64. If set the /BLANK pulse is extended by 64 DCLKs. Note: Is this bit 6 of 3d4h index 3 or does it really extend by 64 ? 4 Start Horizontal Sync Position bit 8. Bit 8 of the Horizontal Start Retrace register (3d4h index 4). 5 (864,964) EHS+32. End Horizontal Sync +32. If set the HSYNC pulse is extended by 32 DCLKs. Note: Is this bit 5 of 3d4h index 5 or does it really extend by 32 ? 6 (928,964) Data Transfer Position bit 8. Bit 8 of the Data Transfer Position register (3d4h index 3Bh) 7 (928,964) Bus-Grant Terminate Position bit 8. Bit 8 of the Bus Grant Termination register (3d4h index 5Fh). */ case 0x5d: vga.crtc.horz_total = (vga.crtc.horz_total & 0xfeff) | ((data & 0x01) << 8); vga.crtc.horz_disp_end = (vga.crtc.horz_disp_end & 0xfeff) | ((data & 0x02) << 7); vga.crtc.horz_blank_start = (vga.crtc.horz_blank_start & 0xfeff) | ((data & 0x04) << 6); vga.crtc.horz_blank_end = (vga.crtc.horz_blank_end & 0xffbf) | ((data & 0x08) << 3); vga.crtc.horz_retrace_start = (vga.crtc.horz_retrace_start & 0xfeff) | ((data & 0x10) << 4); vga.crtc.horz_retrace_end = (vga.crtc.horz_retrace_end & 0xffdf) | (data & 0x20); s3_define_video_mode(); break; /* 3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +) bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5. 1 Vertical Display End bit 10. Bit 10 of the Vertical Display End register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1 and 6 2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9 in 3d4h index 9 bit 5 4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2 and 7. 6 Line Compare Position bit 10. Bit 10 of the Line Compare register (3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h index 9 bit 6. */ case 0x5e: vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) | ((data & 0x01) << 10); vga.crtc.vert_disp_end = (vga.crtc.vert_disp_end & 0xfbff) | ((data & 0x02) << 9); vga.crtc.vert_blank_start = (vga.crtc.vert_blank_start & 0xfbff) | ((data & 0x04) << 8); vga.crtc.vert_retrace_start = (vga.crtc.vert_retrace_start & 0xfbff) | ((data & 0x10) << 6); vga.crtc.line_compare = (vga.crtc.line_compare & 0xfbff) | ((data & 0x40) << 4); s3_define_video_mode(); break; case 0x67: s3.ext_misc_ctrl_2 = data; s3_define_video_mode(); //printf("%02x X\n",data); break; case 0x68: if(s3.reg_lock2 == 0xa5) { s3.strapping = (s3.strapping & 0xff00ffff) | (data << 16); LOGREG("CR68: Strapping data = %08x\n",s3.strapping); } break; case 0x69: vga.crtc.start_addr_latch &= ~0x1f0000; vga.crtc.start_addr_latch |= ((data & 0x1f) << 16); s3_define_video_mode(); break; case 0x6a: svga.bank_w = data & 0x3f; svga.bank_r = svga.bank_w; break; case 0x6f: if(s3.reg_lock2 == 0xa5) { s3.strapping = (s3.strapping & 0x00ffffff) | (data << 24); LOGREG("CR6F: Strapping data = %08x\n",s3.strapping); } break; default: LOGREG("S3: CR%02X write %02x\n",index,data); break; } } } READ8_MEMBER(s3virge_vga_device::port_03b0_r) { uint8_t res = 0xff; if (CRTC_PORT_ADDR == 0x3b0) { switch(offset) { case 5: res = s3_crtc_reg_read(vga.crtc.index); break; default: res = vga_device::port_03b0_r(space,offset,mem_mask); break; } } return res; } WRITE8_MEMBER(s3virge_vga_device::port_03b0_w) { if (CRTC_PORT_ADDR == 0x3b0) { switch(offset) { case 5: vga.crtc.data[vga.crtc.index] = data; s3_crtc_reg_write(vga.crtc.index,data); break; default: vga_device::port_03b0_w(space,offset,data,mem_mask); break; } } } READ8_MEMBER(s3virge_vga_device::port_03c0_r) { uint8_t res; switch(offset) { default: res = s3_vga_device::port_03c0_r(space,offset,mem_mask); break; } return res; } WRITE8_MEMBER(s3virge_vga_device::port_03c0_w) { switch(offset) { default: s3_vga_device::port_03c0_w(space,offset,data,mem_mask); break; } } READ8_MEMBER(s3virge_vga_device::port_03d0_r) { uint8_t res = 0xff; if (CRTC_PORT_ADDR == 0x3d0) { switch(offset) { case 5: res = s3_crtc_reg_read(vga.crtc.index); break; default: res = vga_device::port_03d0_r(space,offset,mem_mask); break; } } return res; } WRITE8_MEMBER(s3virge_vga_device::port_03d0_w) { if (CRTC_PORT_ADDR == 0x3d0) { switch(offset) { case 5: vga.crtc.data[vga.crtc.index] = data; s3_crtc_reg_write(vga.crtc.index,data); break; default: vga_device::port_03d0_w(space,offset,data,mem_mask); break; } } } READ8_MEMBER(s3virge_vga_device::mem_r) { if (svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb24_en || svga.rgb32_en) { uint8_t data; if(offset & 0x10000) return 0; data = 0xff; if(vga.sequencer.data[4] & 0x8) { if(offset + (svga.bank_r*0x10000) < vga.svga_intf.vram_size) data = vga.memory[offset + (svga.bank_r*0x10000)]; } else { int i; for(i=0;i<4;i++) { if(vga.sequencer.map_mask & 1 << i) { if(offset*4+i+(svga.bank_r*0x10000) < vga.svga_intf.vram_size) data |= vga.memory[offset*4+i+(svga.bank_r*0x10000)]; } } } return data; } if((offset + (svga.bank_r*0x10000)) < vga.svga_intf.vram_size) return vga_device::mem_r(space,offset,mem_mask); else return 0xff; } WRITE8_MEMBER(s3virge_vga_device::mem_w) { // bit 4 of CR53 enables memory-mapped I/O if(s3.cr53 & 0x10) { // TODO } if (svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb32_en) { // printf("%08x %02x (%02x %02x) %02X\n",offset,data,vga.sequencer.map_mask,svga.bank_w,(vga.sequencer.data[4] & 0x08)); if(offset & 0x10000) return; if(vga.sequencer.data[4] & 0x8) { if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size) vga.memory[(offset + (svga.bank_w*0x10000))] = data; } else { int i; for(i=0;i<4;i++) { if(vga.sequencer.map_mask & 1 << i) { if((offset*4+i+(svga.bank_w*0x10000)) < vga.svga_intf.vram_size) vga.memory[(offset*4+i+(svga.bank_w*0x10000))] = data; } } } return; } if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size) vga_device::mem_w(space,offset,data,mem_mask); } READ8_MEMBER(s3virge_vga_device::fb_r) { if(offset < s3virge.linear_address_size_full) return vga.memory[offset % vga.svga_intf.vram_size]; return 0xff; } WRITE8_MEMBER(s3virge_vga_device::fb_w) { if(offset < s3virge.linear_address_size_full) vga.memory[offset % vga.svga_intf.vram_size] = data; } void s3virge_vga_device::add_command(int cmd_type) { // add command to S3D FIFO if(s3virge.s3d.cmd_fifo_slots_free == 0) { LOGMMIO("Attempt to add command when all command slots are full\n"); return; } memcpy(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_next_ptr].reg,s3virge.s3d.reg[cmd_type],256*4); s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_next_ptr].op_type = cmd_type; LOGMMIO("Added command type %i cmd %08x ptr %u\n",s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_next_ptr].op_type,s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_next_ptr].reg[S3D_REG_COMMAND],s3virge.s3d.cmd_fifo_next_ptr); s3virge.s3d.cmd_fifo_next_ptr++; if(s3virge.s3d.cmd_fifo_next_ptr >= 16) s3virge.s3d.cmd_fifo_next_ptr = 0; if(s3virge.s3d.cmd_fifo_slots_free == 16) // if all slots are free, start command now command_start(); s3virge.s3d.cmd_fifo_slots_free--; // TODO: handle full FIFO } void s3virge_vga_device::command_start() { // start next command in FIFO int cmd_type = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].op_type; switch(cmd_type) { case OP_BITBLT: s3virge.s3d.state = S3D_STATE_BITBLT; s3virge.s3d.busy = true; s3virge.s3d.bitblt_x_src = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RSRC_XY] & 0x07ff0000) >> 16; s3virge.s3d.bitblt_y_src = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RSRC_XY] & 0x000007ff); s3virge.s3d.bitblt_x_dst = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RDEST_XY] & 0x07ff0000) >> 16; s3virge.s3d.bitblt_y_dst = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RDEST_XY] & 0x000007ff); s3virge.s3d.bitblt_width = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RWIDTH_HEIGHT] & 0xffff0000) >> 16; s3virge.s3d.bitblt_height = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_RWIDTH_HEIGHT] & 0x0000ffff); s3virge.s3d.bitblt_x_current = s3virge.s3d.bitblt_x_dst; s3virge.s3d.bitblt_x_src_current = s3virge.s3d.bitblt_x_src; s3virge.s3d.bitblt_y_current = s3virge.s3d.bitblt_y_dst; s3virge.s3d.bitblt_y_src_current = s3virge.s3d.bitblt_y_src; s3virge.s3d.bitblt_pat_x = s3virge.s3d.bitblt_x_current % 8; s3virge.s3d.bitblt_pat_y = s3virge.s3d.bitblt_y_current % 8; s3virge.s3d.clip_r = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_CLIP_L_R] & 0x000007ff; s3virge.s3d.clip_l = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_CLIP_L_R] & 0x07ff0000) >> 16; s3virge.s3d.clip_b = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_CLIP_T_B] & 0x000007ff; s3virge.s3d.clip_t = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_CLIP_T_B] & 0x07ff0000) >> 16; if(!(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x00000080)) m_draw_timer->adjust(attotime::from_nsec(250),0,attotime::from_nsec(250)); s3virge.s3d.bitblt_step_count = 0; s3virge.s3d.bitblt_mono_pattern = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_MONO_PAT_0] | (uint64_t)(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_MONO_PAT_1]) << 32; s3virge.s3d.bitblt_current_pixel = 0; s3virge.s3d.bitblt_pixel_pos = 0; s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR] = 0xffffffff; // win31 never sets this? LOGMMIO("Started BitBLT command [%u]\n", s3virge.s3d.cmd_fifo_current_ptr); //if(((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x01fe0000) >> 17) == 0xf0) machine().debug_break(); break; } } void s3virge_vga_device::command_finish() { s3virge.s3d.state = S3D_STATE_IDLE; s3virge.s3d.cmd_fifo_current_ptr++; if(s3virge.s3d.cmd_fifo_current_ptr >= 16) s3virge.s3d.cmd_fifo_current_ptr = 0; s3virge.s3d.cmd_fifo_slots_free++; if(s3virge.s3d.cmd_fifo_slots_free > 16) s3virge.s3d.cmd_fifo_slots_free = 16; m_draw_timer->adjust(attotime::never); // check if there is another command in the FIFO if(s3virge.s3d.cmd_fifo_slots_free < 16) command_start(); else s3virge.s3d.busy = false; //machine().debug_break(); LOGMMIO("Command finished [%u] (%u slots free)\n",s3virge.s3d.cmd_fifo_current_ptr,s3virge.s3d.cmd_fifo_slots_free); } uint32_t s3virge_vga_device::GetROP(uint8_t rop, uint32_t src, uint32_t dst, uint32_t pat) { uint32_t ret = 0; switch(rop) { case 0x00: // 0 ret = 0; break; case 0x55: // Dn ret = ~dst; break; case 0x5a: // DPx ret = dst ^ pat; break; case 0x66: // DSx ret = dst ^ src; break; case 0x88: // DSa ret = dst & src; break; case 0xb8: // PSDPxax ret = ((dst ^ pat) & src) ^ pat; // machine().debug_break(); break; case 0xcc: ret = src; break; case 0xf0: ret = pat; break; case 0xff: // 1 ret = 0xffffffff; break; default: popmessage("Unimplemented ROP 0x%02x",rop); } return ret; } bool s3virge_vga_device::advance_pixel() { bool xpos, ypos; int16_t top, left, right, bottom; // advance src/dst and pattern location xpos = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x02000000; // X Positive ypos = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x04000000; // Y Positive if(xpos) { left = s3virge.s3d.bitblt_x_dst; right = s3virge.s3d.bitblt_x_dst + s3virge.s3d.bitblt_width + 1; s3virge.s3d.bitblt_x_current++; s3virge.s3d.bitblt_x_src_current++; s3virge.s3d.bitblt_pat_x++; } else { left = s3virge.s3d.bitblt_x_dst - s3virge.s3d.bitblt_width - 1; right = s3virge.s3d.bitblt_x_dst; s3virge.s3d.bitblt_x_current--; s3virge.s3d.bitblt_x_src_current--; s3virge.s3d.bitblt_pat_x--; // machine().debug_break(); } if(ypos) { top = s3virge.s3d.bitblt_y_dst; bottom = s3virge.s3d.bitblt_y_dst + s3virge.s3d.bitblt_height; } else { top = s3virge.s3d.bitblt_y_dst - s3virge.s3d.bitblt_height; bottom = s3virge.s3d.bitblt_y_dst; } if(s3virge.s3d.bitblt_pat_x < 0 || s3virge.s3d.bitblt_pat_x >= 8) s3virge.s3d.bitblt_pat_x = s3virge.s3d.bitblt_x_current % 8; if((s3virge.s3d.bitblt_x_current >= right) || (s3virge.s3d.bitblt_x_current <= left)) { s3virge.s3d.bitblt_x_current = s3virge.s3d.bitblt_x_dst; s3virge.s3d.bitblt_x_src_current = s3virge.s3d.bitblt_x_src; if(ypos) { s3virge.s3d.bitblt_y_current++; s3virge.s3d.bitblt_y_src_current++; s3virge.s3d.bitblt_pat_y++; } else { s3virge.s3d.bitblt_y_current--; s3virge.s3d.bitblt_y_src_current--; s3virge.s3d.bitblt_pat_y--; } s3virge.s3d.bitblt_pat_x = s3virge.s3d.bitblt_x_current % 8; if(s3virge.s3d.bitblt_pat_y >= 8 || s3virge.s3d.bitblt_pat_y < 0) s3virge.s3d.bitblt_pat_y = s3virge.s3d.bitblt_y_current % 8; logerror("SRC: %i,%i DST: %i,%i PAT: %i,%i Bounds: %i,%i,%i,%i\n", s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,s3virge.s3d.bitblt_pat_x,s3virge.s3d.bitblt_pat_y, left,right,top,bottom); if((s3virge.s3d.bitblt_y_current >= bottom) || (s3virge.s3d.bitblt_y_current <= top)) return true; } return false; } void s3virge_vga_device::bitblt_step() { if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x40)) bitblt_monosrc_step(); else bitblt_colour_step(); } void s3virge_vga_device::bitblt_colour_step() { // progress current BitBLT operation // get source and destination addresses uint32_t src_base = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_BASE] & 0x003ffff8; uint32_t dst_base = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_BASE] & 0x003ffff8; uint8_t pixel_size = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x0000001c) >> 2; uint8_t rop = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x01fe0000) >> 17; uint32_t src = 0; uint32_t dst = 0; uint32_t pat = 0; int align = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x000000c00) >> 10; int x; bool done = false; switch(pixel_size) { case 0: // 8bpp for(x=0;x<4;x++) { if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = s3virge.s3d.image_xfer >> (x*8); else src = read_pixel8(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x100) { pat = (s3virge.s3d.bitblt_mono_pattern & (1 << ((s3virge.s3d.bitblt_pat_y*8) + (7-s3virge.s3d.bitblt_pat_x))) ? s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_FG_CLR] : s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR]); } else pat = (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*8) + s3virge.s3d.bitblt_pat_x]) << 8; dst = read_pixel8(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); write_pixel8(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, src, dst, pat) & 0xff); done = advance_pixel(); if(done) { command_finish(); break; } if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst) { if(align == 2) // doubleword aligned, end here break; if(align == 1) // word aligned, move to next word { if(x < 2) x = 2; else break; } } } break; case 1: // 16bpp if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = s3virge.s3d.image_xfer; else src = read_pixel16(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x100) { pat = (s3virge.s3d.bitblt_mono_pattern & (1 << ((s3virge.s3d.bitblt_pat_y*8) + (7-s3virge.s3d.bitblt_pat_x))) ? s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_FG_CLR] : s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR]); } else pat = s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*16) + (s3virge.s3d.bitblt_pat_x*2)] | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*16) + (s3virge.s3d.bitblt_pat_x*2) + 1]) << 8; write_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, src, dst, pat) & 0xffff); done = advance_pixel(); if(done) { command_finish(); break; } if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst && align == 2) break; // if a new line of an image transfer, and is dword aligned, stop here if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = s3virge.s3d.image_xfer >> 16; else src = read_pixel16(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x100) { pat = (s3virge.s3d.bitblt_mono_pattern & (1 << ((s3virge.s3d.bitblt_pat_y*8) + (7-s3virge.s3d.bitblt_pat_x))) ? s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_FG_CLR] : s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR]); } else pat = s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*16) + (s3virge.s3d.bitblt_pat_x*2)] | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*16) + (s3virge.s3d.bitblt_pat_x*2) + 1]) << 8; write_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, src, dst, pat) & 0xffff); if(advance_pixel()) command_finish(); break; case 2: // 24bpp if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) { src = s3virge.s3d.image_xfer; for(x=0;x<4;x++) { s3virge.s3d.bitblt_current_pixel |= ((s3virge.s3d.image_xfer >> (x*8)) & 0xff) << s3virge.s3d.bitblt_pixel_pos*8; s3virge.s3d.bitblt_pixel_pos++; if(s3virge.s3d.bitblt_pixel_pos > 2) { s3virge.s3d.bitblt_pixel_pos = 0; dst = read_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x100) { pat = (s3virge.s3d.bitblt_mono_pattern & (1 << ((s3virge.s3d.bitblt_pat_y*8) + (7-s3virge.s3d.bitblt_pat_x))) ? s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_FG_CLR] : s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR]); } else pat = s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3)] | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3) + 1]) << 8 | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3) + 2]) << 16; write_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.bitblt_current_pixel, dst, pat)); s3virge.s3d.bitblt_current_pixel = 0; done = advance_pixel(); if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst) { if(align == 2) // doubleword aligned, end here x = 4; if(align == 1) // word aligned, move to next word { if(x < 2) x = 2; else x = 4; } } if(done) command_finish(); } } break; } else { src = read_pixel24(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x100) { pat = (s3virge.s3d.bitblt_mono_pattern & (1 << ((s3virge.s3d.bitblt_pat_y*8) + (7-s3virge.s3d.bitblt_pat_x))) ? s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_FG_CLR] : s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_PAT_BG_CLR]); } else pat = s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3)] | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3) + 1]) << 8 | (s3virge.s3d.pattern[(s3virge.s3d.bitblt_pat_y*24) + (s3virge.s3d.bitblt_pat_x*3) + 2]) << 16; } write_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, src, dst, pat)); if(advance_pixel()) command_finish(); break; } s3virge.s3d.bitblt_step_count++; } void s3virge_vga_device::bitblt_monosrc_step() { // progress current monochrome source BitBLT operation uint32_t src_base = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_BASE] & 0x003ffff8; uint32_t dst_base = s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_DEST_BASE] & 0x003ffff8; uint8_t pixel_size = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x0000001c) >> 2; uint8_t rop = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x01fe0000) >> 17; uint32_t src = 0; uint32_t dst = 0; uint32_t pat = 0; int align = (s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x000000c00) >> 10; int x; bool done = false; switch(pixel_size) { case 0: // 8bpp for(x=31;x>=0;x--) { if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = bitswap<32>(s3virge.s3d.image_xfer,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24); else src = read_pixel8(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel8(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(src & (1 << x)) write_pixel8(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_FG_CLR], dst, pat) & 0xff); else if(!(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x200)) // only draw background colour if transparency is not set write_pixel8(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_BG_CLR], dst, pat) & 0xff); //printf("Pixel write(%i): X: %i Y: %i SRC: %04x DST: %04x PAT: %04x ROP: %02x\n",x,s3virge.s3d.bitblt_x_current, s3virge.s3d.bitblt_y_current, src, dst, pat, rop); done = advance_pixel(); if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst) { switch(align) { case 0: x &= ~7; break; case 1: x &= ~15; break; case 2: x = -1; break; } if(done) { command_finish(); break; } } } break; case 1: // 16bpp for(x=31;x>=0;x--) { if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = bitswap<32>(s3virge.s3d.image_xfer,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24); else src = read_pixel16(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(src & (1 << x)) write_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_FG_CLR], dst, pat) & 0xffff); else if(!(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x200)) // only draw background colour if transparency is not set write_pixel16(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_BG_CLR], dst, pat) & 0xffff); //printf("Pixel write(%i): X: %i Y: %i SRC: %04x DST: %04x PAT: %04x ROP: %02x\n",x,s3virge.s3d.bitblt_x_current, s3virge.s3d.bitblt_y_current, src, dst, pat, rop); done = advance_pixel(); if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst) { switch(align) { case 0: x &= ~7; break; case 1: x &= ~15; break; case 2: x = -1; break; } if(done) { command_finish(); break; } } } break; case 2: // 24bpp for(x=31;x>=0;x--) { if(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) src = bitswap<32>(s3virge.s3d.image_xfer,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24); else src = read_pixel24(src_base,s3virge.s3d.bitblt_x_src_current,s3virge.s3d.bitblt_y_src_current); dst = read_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current); if(src & (1 << x)) write_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_FG_CLR], dst, pat)); else if(!(s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x200)) // only draw background colour if transparency is not set write_pixel24(dst_base,s3virge.s3d.bitblt_x_current,s3virge.s3d.bitblt_y_current,GetROP(rop, s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_SRC_BG_CLR], dst, pat)); //printf("Pixel write(%i): X: %i Y: %i SRC: %04x DST: %04x PAT: %04x ROP: %02x\n",x,s3virge.s3d.bitblt_x_current, s3virge.s3d.bitblt_y_current, src, dst, pat, rop); done = advance_pixel(); if((s3virge.s3d.cmd_fifo[s3virge.s3d.cmd_fifo_current_ptr].reg[S3D_REG_COMMAND] & 0x80) && s3virge.s3d.bitblt_x_current == s3virge.s3d.bitblt_x_dst) { switch(align) { case 0: x &= ~7; break; case 1: x &= ~15; break; case 2: x = -1; break; } if(done) { command_finish(); break; } } } break; } s3virge.s3d.bitblt_step_count++; } void s3virge_vga_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { // TODO: S3D state timing if(id == TIMER_DRAW_STEP) { switch(s3virge.s3d.state) { case S3D_STATE_IDLE: m_draw_timer->adjust(attotime::zero); break; case S3D_STATE_BITBLT: bitblt_step(); break; } } } // 2D command register format - A500 (BitBLT), A900 (2D line), AD00 (2D Polygon) // bit 0 - Autoexecute, if set command is executed when the highest relevant register is written to (A50C / A97C / AD7C) // bit 1 - Enable hardware clipping // bits 2-4 - Destination colour format - (0 = 8bpp palettised, 1 = 16bpp RGB1555 or RGB565, 2 = 24bpp RGB888 // bit 5 - Draw enable - if reset, doesn't draw anything, but is still executed // bit 6 - Image source Mono transfer, if set source is mono, otherwise source is the same pixel depth as the destination // bit 7 - Image data source - 0 = source is in video memory, 1 = source is from the image transfer port (CPU / system memory) // bit 8 - Mono pattern - if set, pattern data is mono, otherwise pattern data is the same pixel depth as the destination // Cleared to 0 if using an ROP with a colour source Must be set to 1 if doing a rectangle fill operation // bit 9 - Transparency - if set, does not update if a background colour is selected. Effectively only if bit 7 is set, Typically used for text display. // bits 10-11 - Image transfer alignment - Data for an image transfer is byte (0), word (1), or doubleword (2) aligned. All image transfers are doubleword in size. // bits 12-13 - First doubleword offset - (Image transfers) - start with the given byte (+1) in a doubleword for an image transfer // bits 17-24 - MS Windows Raster Operation // bit 25 - X Positive - if set, BitBLT is performed from left to right, otherwise, from right to left // bit 26 - Y Positive - if set, BitBLT is performed from top to bottom, otherwise from bottom to top // bits 27-30 - 2D Command - 0000 = BitBLT, 0010 = Rectangle Fill, 0011 = Line Draw, 0101 = Polygon Fill, 1111 = NOP (Turns off autoexecute without executing a command) // bit 31 - 2D / 3D Select READ32_MEMBER(s3virge_vga_device::s3d_sub_status_r) { uint32_t res = 0x00000000; if(!s3virge.s3d.busy) res |= 0x00002000; // S3d engine is idle //res |= (s3virge.s3d.cmd_fifo_slots_free << 8); if(s3virge.s3d.cmd_fifo_slots_free == 16) res |= 0x1f00; return res; } WRITE32_MEMBER(s3virge_vga_device::s3d_sub_control_w) { s3virge.interrupt_enable = data & 0x00003f80; // TODO: bits 14-15==10 - reset engine LOGMMIO("Sub control = %08x\n", data); } READ32_MEMBER(s3virge_vga_device::s3d_func_ctrl_r) { uint32_t ret = 0; ret |= (s3virge.s3d.cmd_fifo_slots_free << 6); return ret; } READ32_MEMBER(s3virge_vga_device::s3d_register_r) { uint32_t res = 0; int op_type = (((offset*4) & 0x1c00) >> 10) - 1; // unused registers if(offset < 0x100/4) return 0; if(offset >= 0x1c0/4 && offset < 0x400/4) return 0; // handle BitBLT pattern registers if((offset >= 0x100/4) && (offset < 0x1c0/4)) return s3virge.s3d.pattern[offset - (0x100/4)]; res = s3virge.s3d.reg[op_type][((offset*4) & 0x03ff) / 4]; LOGMMIO("MM%04X returning %08x\n", (offset*4)+0xa000, res); return res; } WRITE32_MEMBER(s3virge_vga_device::s3d_register_w) { int op_type = (((offset*4) & 0x1c00) >> 10) - 1; // unused registers if(offset < 0x100/4) return; if(offset >= 0x1c0/4 && offset < 0x400/4) return; // handle BitBLT pattern registers if((offset >= 0x100/4) && (offset < 0x1c0/4)) { //COMBINE_DATA(&s3virge.s3d.pattern[(offset*4) - (0x100/4)]); s3virge.s3d.pattern[((offset - 0x100/4)*4)+3] = (data & 0xff000000) >> 24; s3virge.s3d.pattern[((offset - 0x100/4)*4)+2] = (data & 0x00ff0000) >> 16; s3virge.s3d.pattern[((offset - 0x100/4)*4)+1] = (data & 0x0000ff00) >> 8; s3virge.s3d.pattern[((offset - 0x100/4)*4)] = (data & 0x000000ff); return; } s3virge.s3d.reg[op_type][((offset*4) & 0x03ff) / 4] = data; LOGMMIO("MM%04X = %08x\n", (offset*4)+0xa000, data); switch(offset) { case 0x500/4: if(!(data & 0x00000001)) add_command(op_type); break; case 0x50c/4: if(s3virge.s3d.reg[op_type][S3D_REG_COMMAND] & 0x00000001) // autoexecute enabled add_command(op_type); break; } }