diff options
Diffstat (limited to 'src/mame/drivers/ti99_4p.cpp')
-rw-r--r-- | src/mame/drivers/ti99_4p.cpp | 91 |
1 files changed, 50 insertions, 41 deletions
diff --git a/src/mame/drivers/ti99_4p.cpp b/src/mame/drivers/ti99_4p.cpp index 7c53c585c31..00774139e37 100644 --- a/src/mame/drivers/ti99_4p.cpp +++ b/src/mame/drivers/ti99_4p.cpp @@ -165,28 +165,31 @@ private: DECLARE_WRITE_LINE_MEMBER( ready_line ); DECLARE_WRITE_LINE_MEMBER( extint ); DECLARE_WRITE_LINE_MEMBER( notconnected ); - uint8_t interrupt_level(); + DECLARE_READ8_MEMBER( interrupt_level ); - uint8_t setoffset(offs_t offset); - uint16_t memread(offs_t offset); - void memwrite(offs_t offset, uint16_t data); + DECLARE_READ8_MEMBER( setoffset ); + DECLARE_READ16_MEMBER( memread ); + DECLARE_WRITE16_MEMBER( memwrite ); DECLARE_WRITE_LINE_MEMBER( dbin_in ); - void external_operation(offs_t offset, uint8_t data); + DECLARE_READ16_MEMBER( samsmem_read ); + DECLARE_WRITE16_MEMBER( samsmem_write ); + + DECLARE_WRITE8_MEMBER(external_operation); DECLARE_WRITE_LINE_MEMBER( clock_out ); DECLARE_WRITE_LINE_MEMBER( dbin_line ); // CRU (Communication Register Unit) handling - uint8_t cruread(offs_t offset); - void cruwrite(offs_t offset, uint8_t data); - uint8_t read_by_9901(offs_t offset); + DECLARE_READ8_MEMBER( cruread ); + DECLARE_WRITE8_MEMBER( cruwrite ); + DECLARE_READ8_MEMBER( read_by_9901 ); DECLARE_WRITE_LINE_MEMBER(keyC0); DECLARE_WRITE_LINE_MEMBER(keyC1); DECLARE_WRITE_LINE_MEMBER(keyC2); DECLARE_WRITE_LINE_MEMBER(cs_motor); DECLARE_WRITE_LINE_MEMBER(audio_gate); DECLARE_WRITE_LINE_MEMBER(cassette_output); - void tms9901_interrupt(offs_t offset, uint8_t data); + DECLARE_WRITE8_MEMBER(tms9901_interrupt); DECLARE_WRITE_LINE_MEMBER(alphaW); DECLARE_WRITE_LINE_MEMBER(video_interrupt_in); @@ -210,8 +213,8 @@ private: required_ioport m_alpha; int decode_address(int address); - uint16_t debugger_read(offs_t offset); - void debugger_write(offs_t offset, uint16_t data); + DECLARE_READ16_MEMBER( debugger_read ); + DECLARE_WRITE16_MEMBER( debugger_write ); void ready_join(); void set_keyboard_column(int number, int data); @@ -254,6 +257,9 @@ private: // Incoming Ready level int m_sysready; + // Saves a pointer to the address space + address_space* m_spacep; + // Internal DSR mapped in bool m_internal_dsr_active; @@ -303,8 +309,11 @@ void ti99_4p_state::memmap_setoffset(address_map &map) void ti99_4p_state::crumap(address_map &map) { - map(0x0000, 0x1fff).rw(FUNC(ti99_4p_state::cruread), FUNC(ti99_4p_state::cruwrite)); - map(0x0000, 0x03ff).rw(m_tms9901, FUNC(tms9901_device::read), FUNC(tms9901_device::write)); + map(0x0000, 0x01ff).r(FUNC(ti99_4p_state::cruread)); + map(0x0000, 0x003f).r(m_tms9901, FUNC(tms9901_device::read)); + + map(0x0000, 0x0fff).w(FUNC(ti99_4p_state::cruwrite)); + map(0x0000, 0x01ff).w(m_tms9901, FUNC(tms9901_device::write)); } /* @@ -431,7 +440,7 @@ int ti99_4p_state::decode_address(int address) Called when the memory access starts by setting the address bus. From that point on, we suspend the CPU until all operations are done. */ -uint8_t ti99_4p_state::setoffset(offs_t offset) +READ8_MEMBER( ti99_4p_state::setoffset ) { m_addr_buf = offset; m_waitcount = 0; @@ -440,6 +449,7 @@ uint8_t ti99_4p_state::setoffset(offs_t offset) m_decode = SGCPU_NONE; m_muxready = true; + m_spacep = &space; m_decode = decode_address(m_addr_buf); @@ -452,7 +462,7 @@ uint8_t ti99_4p_state::setoffset(offs_t offset) m_waitcount = 5; m_muxready = false; m_peribox->memen_in(ASSERT_LINE); - m_peribox->setaddress_dbin(m_addr_buf+1, m_dbin); + m_peribox->setaddress_dbin(space, m_addr_buf+1, m_dbin); } ready_join(); @@ -460,7 +470,7 @@ uint8_t ti99_4p_state::setoffset(offs_t offset) return 0; } -uint16_t ti99_4p_state::memread(offs_t offset) +READ16_MEMBER( ti99_4p_state::memread ) { int address = 0; uint8_t hbyte = 0; @@ -513,10 +523,10 @@ uint16_t ti99_4p_state::memread(offs_t offset) break; case SGCPU_PEB: - if (machine().side_effects_disabled()) return debugger_read(offset); + if (machine().side_effects_disabled()) return debugger_read(space, offset); // The byte from the odd address has already been read into the latch // Reading the even address now - m_peribox->readz(m_addr_buf, &hbyte); + m_peribox->readz(space, m_addr_buf, &hbyte); m_peribox->memen_in(CLEAR_LINE); LOGMASKED(LOG_MEM, "Read even byte from address %04x -> %02x\n", m_addr_buf, hbyte); value = (hbyte<<8) | m_latch; @@ -526,7 +536,7 @@ uint16_t ti99_4p_state::memread(offs_t offset) } -void ti99_4p_state::memwrite(offs_t offset, uint16_t data) +WRITE16_MEMBER( ti99_4p_state::memwrite ) { int address = 0; @@ -575,7 +585,7 @@ void ti99_4p_state::memwrite(offs_t offset, uint16_t data) break; case SGCPU_PEB: - if (machine().side_effects_disabled()) { debugger_write(offset, data); return; } + if (machine().side_effects_disabled()) { debugger_write(space, offset, data); return; } // Writing the even address now (addr) // The databus multiplexer puts the even value into the latch and outputs the odd value now. @@ -583,7 +593,7 @@ void ti99_4p_state::memwrite(offs_t offset, uint16_t data) // write odd byte LOGMASKED(LOG_MEM, "datamux: write odd byte to address %04x <- %02x\n", m_addr_buf+1, data & 0xff); - m_peribox->write(m_addr_buf+1, data & 0xff); + m_peribox->write(space, m_addr_buf+1, data & 0xff); m_peribox->memen_in(CLEAR_LINE); } } @@ -591,14 +601,14 @@ void ti99_4p_state::memwrite(offs_t offset, uint16_t data) /* Used when the debugger is reading values from PEB cards. */ -uint16_t ti99_4p_state::debugger_read(offs_t offset) +READ16_MEMBER( ti99_4p_state::debugger_read ) { uint8_t lval = 0; uint8_t hval = 0; uint16_t addrb = offset << 1; m_peribox->memen_in(ASSERT_LINE); - m_peribox->readz(addrb+1, &lval); - m_peribox->readz(addrb, &hval); + m_peribox->readz(space, addrb+1, &lval); + m_peribox->readz(space, addrb, &hval); m_peribox->memen_in(CLEAR_LINE); return ((hval << 8)&0xff00) | (lval & 0xff); } @@ -606,12 +616,12 @@ uint16_t ti99_4p_state::debugger_read(offs_t offset) /* Used when the debugger is writing values to PEB cards. */ -void ti99_4p_state::debugger_write(offs_t offset, uint16_t data) +WRITE16_MEMBER( ti99_4p_state::debugger_write ) { int addrb = offset << 1; m_peribox->memen_in(ASSERT_LINE); - m_peribox->write(addrb+1, data & 0xff); - m_peribox->write(addrb, (data>>8) & 0xff); + m_peribox->write(space, addrb+1, data & 0xff); + m_peribox->write(space, addrb, (data>>8) & 0xff); m_peribox->memen_in(CLEAR_LINE); } @@ -652,14 +662,14 @@ WRITE_LINE_MEMBER( ti99_4p_state::datamux_clock_in ) if (m_waitcount==2) { // read odd byte - m_peribox->readz(m_addr_buf+1, &m_latch); + m_peribox->readz(*m_spacep, m_addr_buf+1, &m_latch); m_peribox->memen_in(CLEAR_LINE); LOGMASKED(LOG_MEM, "datamux: read odd byte from address %04x -> %02x\n", m_addr_buf+1, m_latch); // do the setaddress for the even address m_peribox->memen_in(ASSERT_LINE); - m_peribox->setaddress_dbin(m_addr_buf, m_dbin); + m_peribox->setaddress_dbin(*m_spacep, m_addr_buf, m_dbin); } } } @@ -679,11 +689,11 @@ WRITE_LINE_MEMBER( ti99_4p_state::datamux_clock_in ) { // do the setaddress for the even address m_peribox->memen_in(ASSERT_LINE); - m_peribox->setaddress_dbin(m_addr_buf, m_dbin); + m_peribox->setaddress_dbin(*m_spacep, m_addr_buf, m_dbin); // write even byte LOGMASKED(LOG_MEM, "datamux: write even byte to address %04x <- %02x\n", m_addr_buf, m_latch); - m_peribox->write(m_addr_buf, m_latch); + m_peribox->write(*m_spacep, m_addr_buf, m_latch); m_peribox->memen_in(CLEAR_LINE); } } @@ -701,7 +711,7 @@ WRITE_LINE_MEMBER( ti99_4p_state::datamux_clock_in ) /* CRU write */ -void ti99_4p_state::cruwrite(offs_t offset, uint8_t data) +WRITE8_MEMBER( ti99_4p_state::cruwrite ) { int addroff = offset<<1; @@ -722,13 +732,13 @@ void ti99_4p_state::cruwrite(offs_t offset, uint8_t data) } // No match - pass to peribox - m_peribox->cruwrite(addroff, data); + m_peribox->cruwrite(space, addroff, data); } -uint8_t ti99_4p_state::cruread(offs_t offset) +READ8_MEMBER( ti99_4p_state::cruread ) { uint8_t value = 0; - m_peribox->crureadz(offset<<4, &value); + m_peribox->crureadz(space, offset<<4, &value); return value; } @@ -736,7 +746,7 @@ uint8_t ti99_4p_state::cruread(offs_t offset) Keyboard/tape control ****************************************************************************/ -uint8_t ti99_4p_state::read_by_9901(offs_t offset) +READ8_MEMBER( ti99_4p_state::read_by_9901 ) { int answer=0; @@ -909,12 +919,11 @@ WRITE_LINE_MEMBER( ti99_4p_state::notconnected ) */ WRITE_LINE_MEMBER( ti99_4p_state::clock_out ) { - m_tms9901->phi_line(state); datamux_clock_in(state); m_peribox->clock_in(state); } -void ti99_4p_state::tms9901_interrupt(offs_t offset, uint8_t data) +WRITE8_MEMBER( ti99_4p_state::tms9901_interrupt ) { // offset contains the interrupt level (0-15) // However, the TI board just ignores that level and hardwires it to 1 @@ -922,14 +931,14 @@ void ti99_4p_state::tms9901_interrupt(offs_t offset, uint8_t data) m_cpu->set_input_line(INT_9900_INTREQ, data); } -uint8_t ti99_4p_state::interrupt_level() +READ8_MEMBER( ti99_4p_state::interrupt_level ) { // On the TI-99 systems these IC lines are not used; the input lines // at the CPU are hardwired to level 1. return 1; } -void ti99_4p_state::external_operation(offs_t offset, uint8_t data) +WRITE8_MEMBER( ti99_4p_state::external_operation ) { static char const *const extop[8] = { "inv1", "inv2", "IDLE", "RSET", "inv3", "CKON", "CKOF", "LREX" }; if (offset != IDLE_OP) logerror("External operation %s not implemented on the SGCPU board\n", extop[offset]); @@ -1011,7 +1020,7 @@ void ti99_4p_state::ti99_4p_60hz(machine_config& config) m_cpu->dbin_cb().set(FUNC(ti99_4p_state::dbin_line)); // tms9901 - TMS9901(config, m_tms9901, 0); + TMS9901(config, m_tms9901, 3000000); m_tms9901->read_cb().set(FUNC(ti99_4p_state::read_by_9901)); m_tms9901->p_out_cb(2).set(FUNC(ti99_4p_state::keyC0)); m_tms9901->p_out_cb(3).set(FUNC(ti99_4p_state::keyC1)); |