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path: root/src/mame/drivers/simple_st0016.cpp
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Diffstat (limited to 'src/mame/drivers/simple_st0016.cpp')
-rw-r--r--src/mame/drivers/simple_st0016.cpp89
1 files changed, 47 insertions, 42 deletions
diff --git a/src/mame/drivers/simple_st0016.cpp b/src/mame/drivers/simple_st0016.cpp
index 6610ee49509..591d2585d7c 100644
--- a/src/mame/drivers/simple_st0016.cpp
+++ b/src/mame/drivers/simple_st0016.cpp
@@ -38,18 +38,20 @@ void st0016_state::machine_start()
m_mainbank->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
}
-ADDRESS_MAP_START(st0016_state::st0016_mem)
- AM_RANGE(0x0000, 0x7fff) AM_ROM
- AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("mainbank")
- AM_RANGE(0xe000, 0xe7ff) AM_RAM
- AM_RANGE(0xe800, 0xe87f) AM_RAM /* common ram */
- AM_RANGE(0xf000, 0xffff) AM_RAM /* work ram */
-ADDRESS_MAP_END
+void st0016_state::st0016_mem(address_map &map)
+{
+ map(0x0000, 0x7fff).rom();
+ map(0x8000, 0xbfff).bankr("mainbank");
+ map(0xe000, 0xe7ff).ram();
+ map(0xe800, 0xe87f).ram(); /* common ram */
+ map(0xf000, 0xffff).ram(); /* work ram */
+}
-ADDRESS_MAP_START(st0016_state::renju_mem)
- AM_IMPORT_FROM( st0016_mem )
- AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0x200000 )
-ADDRESS_MAP_END
+void st0016_state::renju_mem(address_map &map)
+{
+ st0016_mem(map);
+ map(0x0000, 0x7fff).rom().region("maincpu", 0x200000);
+}
READ8_MEMBER(st0016_state::mux_r)
@@ -87,17 +89,18 @@ WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
// st0016_rom_bank = data;
}
-ADDRESS_MAP_START(st0016_state::st0016_io)
- ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0xc0, 0xc0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
- AM_RANGE(0xc1, 0xc1) AM_READ_PORT("P2") AM_WRITENOP
- AM_RANGE(0xc2, 0xc2) AM_READ(mux_r) AM_WRITENOP
- AM_RANGE(0xc3, 0xc3) AM_READ_PORT("P2") AM_WRITENOP
- AM_RANGE(0xe0, 0xe0) AM_WRITENOP /* renju = $40, neratte = 0 */
- AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
- AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
- AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
-ADDRESS_MAP_END
+void st0016_state::st0016_io(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0xc0, 0xc0).portr("P1").w(this, FUNC(st0016_state::mux_select_w));
+ map(0xc1, 0xc1).portr("P2").nopw();
+ map(0xc2, 0xc2).r(this, FUNC(st0016_state::mux_r)).nopw();
+ map(0xc3, 0xc3).portr("P2").nopw();
+ map(0xe0, 0xe0).nopw(); /* renju = $40, neratte = 0 */
+ map(0xe1, 0xe1).w(this, FUNC(st0016_state::st0016_rom_bank_w));
+ map(0xe6, 0xe6).nopw(); /* banking ? ram bank ? shared rambank ? */
+ map(0xe7, 0xe7).nopw(); /* watchdog */
+}
/*************************************
@@ -138,26 +141,28 @@ WRITE8_MEMBER(st0016_state::latch8_w)
machine().scheduler().synchronize();
}
-ADDRESS_MAP_START(st0016_state::v810_mem)
- AM_RANGE(0x00000000, 0x0001ffff) AM_RAM
- AM_RANGE(0x80000000, 0x8001ffff) AM_RAM
- AM_RANGE(0xc0000000, 0xc001ffff) AM_RAM
- AM_RANGE(0x40000000, 0x4000000f) AM_READ(latch32_r) AM_WRITE(latch32_w)
- AM_RANGE(0xfff80000, 0xffffffff) AM_ROMBANK("bank2")
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(st0016_state::st0016_m2_io)
- ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0xc0, 0xc3) AM_READ(latch8_r) AM_WRITE(latch8_w)
- AM_RANGE(0xd0, 0xd0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
- AM_RANGE(0xd1, 0xd1) AM_READ_PORT("P2") AM_WRITENOP
- AM_RANGE(0xd2, 0xd2) AM_READ(mux_r) AM_WRITENOP
- AM_RANGE(0xd3, 0xd3) AM_READ_PORT("P2") AM_WRITENOP
- AM_RANGE(0xe0, 0xe0) AM_WRITENOP
- AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
- AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
- AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
-ADDRESS_MAP_END
+void st0016_state::v810_mem(address_map &map)
+{
+ map(0x00000000, 0x0001ffff).ram();
+ map(0x80000000, 0x8001ffff).ram();
+ map(0xc0000000, 0xc001ffff).ram();
+ map(0x40000000, 0x4000000f).r(this, FUNC(st0016_state::latch32_r)).w(this, FUNC(st0016_state::latch32_w));
+ map(0xfff80000, 0xffffffff).bankr("bank2");
+}
+
+void st0016_state::st0016_m2_io(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0xc0, 0xc3).r(this, FUNC(st0016_state::latch8_r)).w(this, FUNC(st0016_state::latch8_w));
+ map(0xd0, 0xd0).portr("P1").w(this, FUNC(st0016_state::mux_select_w));
+ map(0xd1, 0xd1).portr("P2").nopw();
+ map(0xd2, 0xd2).r(this, FUNC(st0016_state::mux_r)).nopw();
+ map(0xd3, 0xd3).portr("P2").nopw();
+ map(0xe0, 0xe0).nopw();
+ map(0xe1, 0xe1).w(this, FUNC(st0016_state::st0016_rom_bank_w));
+ map(0xe6, 0xe6).nopw(); /* banking ? ram bank ? shared rambank ? */
+ map(0xe7, 0xe7).nopw(); /* watchdog */
+}
/*************************************
*