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Diffstat (limited to 'src/mame/drivers/rainbow.cpp')
-rw-r--r--src/mame/drivers/rainbow.cpp139
1 files changed, 73 insertions, 66 deletions
diff --git a/src/mame/drivers/rainbow.cpp b/src/mame/drivers/rainbow.cpp
index 8a5a415c846..440f474545b 100644
--- a/src/mame/drivers/rainbow.cpp
+++ b/src/mame/drivers/rainbow.cpp
@@ -12,7 +12,7 @@ To unlock floppy drives A-D compile with WORKAROUND_RAINBOW_B (prevents a side e
Native single sided 5.25" images with 80 tracks, 10 sectors are well tested (*.IMD / *.TD0=TeleDisk / *.IMG with 400 K).
VT180 images (184.320 Bytes) are very unreliable in CP/M - though a real machine can read them.
5.25 MFM PC style drives and 720 K (3.5 " DS-DD MFM PC formatted disks) (on slots 3 + 4) show regressions / bugs
- as of Dec.2018 (file content bad while dir is OK, seek errors, write fault errors when copying _to_ hard disk).
+ as of Dec.2018 (file content bad while dir is OK, seek errors, write fault errors when copying _to_ hard disk).
ALWAYS USE THE RIGHT SLOT AND SAVE YOUR DATA BEFORE MOUNTING FOREIGN DISK FORMATS!
@@ -27,7 +27,7 @@ The public domain file RBCONVERT.ZIP documents how model 'A' differs from versio
NVRAM files from -A and -B machines are not interchangeable. If problems arise, delete the NVRAM file.
Venix 86-R (BSW) is working, just follow https://github.com/bsdimp/venix/blob/master/doc/MESS-RB-INSTALL.md
-
+
CPM 2.1 / DOS2.11 / DOS 3.x / diag disks boot. UCSD systems (fort_sys, pas_sys) boot, but expect 4 QD drives
loaded with disks (reassign slots, reset and mount three empty 400 K images before startup at #2, #3, #4).
@@ -802,7 +802,7 @@ private:
UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
{
- if(m_inp7->read() == 0)
+ if(m_inp7->read() == 0)
return;
const rgb_t *paletteX = m_palette2->palette()->entry_list_raw();
@@ -1417,10 +1417,10 @@ WRITE_LINE_MEMBER(rainbow_state::mpsc_irq)
// PORT 0x06 : Communication bit rates (see page 21 of PC 100 SPEC)
WRITE8_MEMBER(rainbow_state::comm_bitrate_w)
{
- m_dbrg->str_w(data & 0x0f); // PDF is wrong, low nibble is RECEIVE clock (verified in SETUP).
+ m_dbrg->write_str(data & 0x0f); // PDF is wrong, low nibble is RECEIVE clock (verified in SETUP).
logerror("\n(COMM.) receive bitrate = %d ($%02x)\n", comm_rates[data & 0x0f] , data & 0x0f);
- m_dbrg->stt_w( ((data & 0xf0) >> 4) );
+ m_dbrg->write_stt( ((data & 0xf0) >> 4) );
logerror("(COMM.) transmit bitrate = %d ($%02x)\n", comm_rates[((data & 0xf0) >> 4)] ,(data & 0xf0) >> 4);
}
@@ -1548,16 +1548,16 @@ WRITE8_MEMBER(rainbow_state::rtc_w)
{
case 0x00: // Write to 0xED0FE
if (m_rtc->chip_enable())
- m_rtc->write_data(offset & 0x01); // Transfer data to DS1315 (data = offset):
+ m_rtc->write_data(space, offset & 0x01); // Transfer data to DS1315 (data = offset):
else
- m_rtc->read_0(); // (RTC ACTIVATION) read magic pattern 0
+ m_rtc->read_0(space, 0); // (RTC ACTIVATION) read magic pattern 0
break;
case 0x01: // Write to 0xED0FF
if (m_rtc->chip_enable())
- m_rtc->write_data(offset & 0x01); // Transfer data to DS1315 (data = offset):
+ m_rtc->write_data(space, offset & 0x01); // Transfer data to DS1315 (data = offset):
else
- m_rtc->read_1(); // (RTC ACTIVATION) read magic pattern 1
+ m_rtc->read_1(space, 0); // (RTC ACTIVATION) read magic pattern 1
break;
}
}
@@ -1576,7 +1576,7 @@ READ8_MEMBER(rainbow_state::rtc_r)
#ifdef ASSUME_RAINBOW_A_HARDWARE
case 0x00: // read time/date from 0xED000 (ClikClok for 100-A)
if (m_rtc->chip_enable())
- return m_rtc->read_data() & 0x01;
+ return m_rtc->read_data(space, 0) & 0x01;
else
m_rtc->chip_reset();
#else
@@ -1586,25 +1586,25 @@ READ8_MEMBER(rainbow_state::rtc_r)
case 0x0001: // RTC_WRITE_DATA_1 0xFC001
case 0x2001: // RTC_WRITE_DATA_1 0xFE001 (MIRROR)
- m_rtc->write_data(offset & 0x01);
+ m_rtc->write_data(space, offset & 0x01);
break;
// Read actual time/date from ClikClok:
case 0x0004: // 0xFC004
case 0x2004: // 0xFE004 (MIRROR)
if (m_rtc->chip_enable())
- return (m_rtc->read_data() & 0x01);
+ return (m_rtc->read_data(space, 0) & 0x01);
// (RTC ACTIVATION) read magic pattern 0
case 0x0100: // 0xFC100
case 0x2100: // 0xFE100 (MIRROR)
- m_rtc->read_0();
+ m_rtc->read_0(space, 0);
break;
// (RTC ACTIVATION) read magic pattern 1
case 0x0101: // 0xFC101
case 0x2101: // 0xFE101 (MIRROR)
- m_rtc->read_1();
+ m_rtc->read_1(space, 0);
break;
// RESET
@@ -1741,7 +1741,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
if (!m_hdc_write_gate) // do not read when WRITE GATE is on
{
- uint8_t sdh = (m_hdc->read(0x06));
+ uint8_t sdh = (m_hdc->read(generic_space(), 0x06));
int drv = (sdh & (8 + 16)) >> 3; // get DRIVE from SDH register
if ((state == 0) && (last_state == 1) && (drv == 0))
@@ -1750,9 +1750,9 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
output().set_value("led1", 0);
switch_off_timer->adjust(attotime::from_msec(500));
- int hi = (m_hdc->read(0x05)) & 0x07;
- uint16_t cylinder = (m_hdc->read(0x04)) | (hi << 8);
- uint8_t sector_number = m_hdc->read(0x03);
+ int hi = (m_hdc->read(generic_space(), 0x05)) & 0x07;
+ uint16_t cylinder = (m_hdc->read(generic_space(), 0x04)) | (hi << 8);
+ uint8_t sector_number = m_hdc->read(generic_space(), 0x03);
hard_disk_file *local_hard_disk;
local_hard_disk = rainbow_hdc_file(0); // one hard disk for now.
@@ -1812,7 +1812,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_write_sector)
else
m_hdc_write_gate = true;
- int drv = ((m_hdc->read(0x06)) & (8 + 16)) >> 3; // get DRIVE from SDH register
+ int drv = ((m_hdc->read(generic_space(), 0x06)) & (8 + 16)) >> 3; // get DRIVE from SDH register
if (state == 0 && wg_last == 1 && drv == 0) // Check correct state transition and DRIVE 0 ....
{
@@ -1866,13 +1866,13 @@ int rainbow_state::do_write_sector()
feedback = 10;
output().set_value("led1", 1); // OFF
- uint8_t sdh = (m_hdc->read(0x06));
+ uint8_t sdh = (m_hdc->read(generic_space(), 0x06));
- int hi = (m_hdc->read(0x05)) & 0x07;
- uint16_t cylinder = (m_hdc->read(0x04)) | (hi << 8);
+ int hi = (m_hdc->read(generic_space(), 0x05)) & 0x07;
+ uint16_t cylinder = (m_hdc->read(generic_space(), 0x04)) | (hi << 8);
- int sector_number = m_hdc->read(0x03);
- int sector_count = m_hdc->read(0x02); // (1 = single sector)
+ int sector_number = m_hdc->read(generic_space(), 0x03);
+ int sector_count = m_hdc->read(generic_space(), 0x02); // (1 = single sector)
if (!(cylinder <= info->cylinders && // filter invalid cylinders
SECTOR_SIZES[(sdh >> 5) & 0x03] == info->sectorbytes // 512, may not vary
@@ -1943,7 +1943,7 @@ READ8_MEMBER(rainbow_state::hd_status_68_r)
data = 0xa0; // A0 : OK, DRIVE IS READY (!)
int my_offset = 0x07;
- int stat = m_hdc->read(my_offset);
+ int stat = m_hdc->read(space, my_offset);
// logerror("(x68) WD1010 register %04x (STATUS) read, result : %04x\n", my_offset, stat);
// NOTE: SEEK COMPLETE IS CURRENTLY HARD WIRED / NOT FULLY EMULATED -
@@ -2043,14 +2043,14 @@ positioned over cylinder 0 (the data track furthest away from the spindle).
*/
READ8_MEMBER(rainbow_state::hd_status_69_r)
{
- int hs = m_hdc->read(0x06) & (1 + 2 + 4); // SDH bits 0-2 = HEAD #
+ int hs = m_hdc->read(space, 0x06) & (1 + 2 + 4); // SDH bits 0-2 = HEAD #
// logerror("(x69 READ) %i = HEAD SELECT WD1010\n", hs);
uint8_t data = (hs << 1);
// DRIVE SELECT: 2 bits in SDH register of WDx010 could address 4 drives.
// External circuit supports 1 drive here (DRIVE 0 selected or deselected)
- int drv = ((m_hdc->read(0x06) >> 3) & 0x01); // 0x03 gives error R6 with DIAG.DISK
+ int drv = ((m_hdc->read(space, 0x06) >> 3) & 0x01); // 0x03 gives error R6 with DIAG.DISK
if (drv == 0)
data |= 1; // logerror("(x69 READ) %i = _DRIVE # 0_ SELECT! \n", drv);
@@ -2064,7 +2064,7 @@ READ8_MEMBER(rainbow_state::hd_status_69_r)
data |= 64;
// Fake TRACK 0 signal (normally FROM DRIVE)
- if ((m_hdc->read(0x04) == 0) && (m_hdc->read(0x05) == 0)) // CYL.LO - CYL.HI
+ if ((m_hdc->read(space, 0x04) == 0) && (m_hdc->read(space, 0x05) == 0)) // CYL.LO - CYL.HI
data |= 128; // logerror("(x69 READ) TRACK 00 detected\n");
return data;
@@ -2947,8 +2947,11 @@ READ8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_r)
break;
case 6:
+ data = m_hgdc->read(space, offset & 0x00);
+ break;
+
case 7:
- data = m_hgdc->read(offset & 0x01);
+ data = m_hgdc->read(space, offset & 0x01);
break;
default:
@@ -3166,7 +3169,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
case 6:
case 7:
- m_hgdc->write(offset & 0x01, data);
+ m_hgdc->write(space, offset & 0x01, data);
break;
} // switch
@@ -3197,26 +3200,26 @@ void rainbow_state::upd7220_map(address_map &map)
map(0x00000, 0x3ffff).rw(FUNC(rainbow_state::vram_r), FUNC(rainbow_state::vram_w)).share("vram");
}
-void rainbow_state::rainbow(machine_config &config)
-{
+MACHINE_CONFIG_START(rainbow_state::rainbow)
config.set_default_layout(layout_rainbow);
/* basic machine hardware */
- I8088(config, m_i8088, 24.0734_MHz_XTAL / 5); // approximately 4.815 MHz
- m_i8088->set_addrmap(AS_PROGRAM, &rainbow_state::rainbow8088_map);
- m_i8088->set_addrmap(AS_IO, &rainbow_state::rainbow8088_io);
- m_i8088->set_irq_acknowledge_callback(FUNC(rainbow_state::irq_callback));
+ MCFG_DEVICE_ADD("maincpu", I8088, 24.0734_MHz_XTAL / 5) // approximately 4.815 MHz
+ MCFG_DEVICE_PROGRAM_MAP(rainbow8088_map)
+ MCFG_DEVICE_IO_MAP(rainbow8088_io)
+ MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(rainbow_state, irq_callback)
- Z80(config, m_z80, 24.0734_MHz_XTAL / 6);
- m_z80->set_addrmap(AS_PROGRAM, &rainbow_state::rainbowz80_mem);
- m_z80->set_addrmap(AS_IO, &rainbow_state::rainbowz80_io);
+ MCFG_DEVICE_ADD("subcpu", Z80, 24.0734_MHz_XTAL / 6)
+ MCFG_DEVICE_PROGRAM_MAP(rainbowz80_mem)
+ MCFG_DEVICE_IO_MAP(rainbowz80_io)
/* video hardware */
- screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
- screen.set_raw(24.0734_MHz_XTAL / 6, 442, 0, 400, 264, 0, 240); // ~NTSC compatible video timing (?)
- screen.set_screen_update(FUNC(rainbow_state::screen_update_rainbow));
- screen.set_palette("vt100_video:palette");
- GFXDECODE(config, "gfxdecode", "vt100_video:palette", gfx_rainbow);
+ MCFG_SCREEN_ADD("screen", RASTER)
+ MCFG_SCREEN_RAW_PARAMS(24.0734_MHz_XTAL / 6, 442, 0, 400, 264, 0, 240) // ~NTSC compatible video timing (?)
+
+ MCFG_SCREEN_UPDATE_DRIVER(rainbow_state, screen_update_rainbow)
+ MCFG_SCREEN_PALETTE("vt100_video:palette")
+ MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "vt100_video:palette", gfx_rainbow)
RAINBOW_VIDEO(config, m_crtc, 24.0734_MHz_XTAL);
m_crtc->set_screen("screen");
@@ -3230,31 +3233,31 @@ void rainbow_state::rainbow(machine_config &config)
m_hgdc->vsync_wr_callback().set(FUNC(rainbow_state::GDC_vblank_irq)); // "The vsync callback line needs to be below the 7220 DEVICE_ADD line."
m_hgdc->set_addrmap(0, &rainbow_state::upd7220_map);
- m_hgdc->set_display_pixels(FUNC(rainbow_state::hgdc_display_pixels));
+ m_hgdc->set_display_pixels_callback(FUNC(rainbow_state::hgdc_display_pixels), this);
m_hgdc->set_screen(m_screen2); // set_screen needs to be added after 7720 device in the machine config, not after the screen.
- PALETTE(config, m_palette2).set_entries(32);
+ MCFG_PALETTE_ADD("palette2", 32)
- SCREEN(config, m_screen2, SCREEN_TYPE_RASTER);
- m_screen2->set_video_attributes(VIDEO_UPDATE_AFTER_VBLANK | VIDEO_ALWAYS_UPDATE);
+ MCFG_SCREEN_ADD("screen2", RASTER)
+ MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK | VIDEO_ALWAYS_UPDATE)
// VR241 color monitor is specified for 20 MHz bandwidth ( 60 Hz / 15.72 kHz horizontal rate )
// - sufficient for 800 x 240 non-interlaced at 60 Hz (non interlaced).
- //m_screen2->set_raw(31188000 / 2 , 992, 0, 800, 262, 0, 240);
+ //MCFG_SCREEN_RAW_PARAMS(31188000 / 2 , 992, 0, 800, 262, 0, 240)
// Alternate configuration:
- m_screen2->set_raw(31188000 / 4 , 496, 0, 400, 262, 0, 240);
+ MCFG_SCREEN_RAW_PARAMS(31188000 / 4 , 496, 0, 400, 262, 0, 240)
- m_screen2->set_screen_update("upd7220", FUNC(upd7220_device::screen_update));
+ MCFG_SCREEN_UPDATE_DEVICE("upd7220", upd7220_device, screen_update)
FD1793(config, m_fdc, 24.0734_MHz_XTAL / 24); // no separate 1 Mhz quartz
- FLOPPY_CONNECTOR(config, FD1793_TAG ":0", rainbow_floppies, "525qd", rainbow_state::floppy_formats);
- FLOPPY_CONNECTOR(config, FD1793_TAG ":1", rainbow_floppies, "525qd", rainbow_state::floppy_formats);
- FLOPPY_CONNECTOR(config, FD1793_TAG ":2", rainbow_floppies, "525qd", rainbow_state::floppy_formats);
- FLOPPY_CONNECTOR(config, FD1793_TAG ":3", rainbow_floppies, "525qd", rainbow_state::floppy_formats);
- //FLOPPY_CONNECTOR(config, FD1793_TAG ":2", rainbow_floppies, "525dd", rainbow_state::floppy_formats);
- //FLOPPY_CONNECTOR(config, FD1793_TAG ":3", rainbow_floppies, "35dd", rainbow_state::floppy_formats);
- SOFTWARE_LIST(config, "flop_list").set_original("rainbow");
+ MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":0", rainbow_floppies, "525qd", rainbow_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":1", rainbow_floppies, "525qd", rainbow_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":2", rainbow_floppies, "525qd", rainbow_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":3", rainbow_floppies, "525qd", rainbow_state::floppy_formats)
+ //MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":2", rainbow_floppies, "525dd", rainbow_state::floppy_formats)
+ //MCFG_FLOPPY_DRIVE_ADD(FD1793_TAG ":3", rainbow_floppies, "35dd", rainbow_state::floppy_formats)
+ MCFG_SOFTWARE_LIST_ADD("flop_list", "rainbow")
/// ********************************* HARD DISK CONTROLLER *****************************************
WD2010(config, m_hdc, 5000000); // 10 Mhz quartz on controller (divided by 2 for WCLK)
@@ -3277,14 +3280,18 @@ void rainbow_state::rainbow(machine_config &config)
m_hdc->in_sc_callback().set_constant(1); // SEEK COMPLETE (VCC = complete)
m_hdc->in_tk000_callback().set_constant(1); // TRACK 00 signal (= from drive)
- HARDDISK(config, "decharddisk1");
+ MCFG_HARDDISK_ADD("decharddisk1")
/// ******************************** / HARD DISK CONTROLLER ****************************************
- CORVUS_HDC(config, m_corvus_hdc, 0);
- HARDDISK(config, "harddisk1", "corvus_hdd");
- HARDDISK(config, "harddisk2", "corvus_hdd");
- HARDDISK(config, "harddisk3", "corvus_hdd");
- HARDDISK(config, "harddisk4", "corvus_hdd");
+ MCFG_DEVICE_ADD("corvus", CORVUS_HDC, 0)
+ MCFG_HARDDISK_ADD("harddisk1")
+ MCFG_HARDDISK_INTERFACE("corvus_hdd")
+ MCFG_HARDDISK_ADD("harddisk2")
+ MCFG_HARDDISK_INTERFACE("corvus_hdd")
+ MCFG_HARDDISK_ADD("harddisk3")
+ MCFG_HARDDISK_INTERFACE("corvus_hdd")
+ MCFG_HARDDISK_ADD("harddisk4")
+ MCFG_HARDDISK_INTERFACE("corvus_hdd")
DS1315(config, m_rtc, 0); // DS1315 (ClikClok for DEC-100 B) * OPTIONAL *
@@ -3328,10 +3335,10 @@ void rainbow_state::rainbow(machine_config &config)
prtbrg.set_stages(8);
prtbrg.count_out_cb().set(FUNC(rainbow_state::bitrate_counter_w));
- TIMER(config, "motor").configure_periodic(FUNC(rainbow_state::hd_motor_tick), attotime::from_hz(60));
+ MCFG_TIMER_DRIVER_ADD_PERIODIC("motor", rainbow_state, hd_motor_tick, attotime::from_hz(60))
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
-}
+MACHINE_CONFIG_END
//----------------------------------------------------------------------------------------
// 'Rainbow 100-A' (system module 70-19974-00, PSU H7842-A)